Searched refs:AVR (Results 1 - 25 of 27) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRELFStreamer.cpp16 if (Features[AVR::ELFArchAVR1])
18 else if (Features[AVR::ELFArchAVR2])
20 else if (Features[AVR::ELFArchAVR25])
22 else if (Features[AVR::ELFArchAVR3])
24 else if (Features[AVR::ELFArchAVR31])
26 else if (Features[AVR::ELFArchAVR35])
28 else if (Features[AVR::ELFArchAVR4])
30 else if (Features[AVR::ELFArchAVR5])
32 else if (Features[AVR::ELFArchAVR51])
34 else if (Features[AVR
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H A DAVRELFObjectWriter.cpp1 //===-- AVRELFObjectWriter.cpp - AVR ELF Writer ---------------------------===//
22 /// Writes AVR machine code into an ELF32 object file.
79 case AVR::fixup_32:
81 case AVR::fixup_7_pcrel:
83 case AVR::fixup_13_pcrel:
85 case AVR::fixup_16:
87 case AVR::fixup_16_pm:
89 case AVR::fixup_lo8_ldi:
91 case AVR::fixup_hi8_ldi:
93 case AVR
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H A DAVRInstPrinter.cpp1 //===-- AVRInstPrinter.cpp - Convert AVR MCInst to assembly syntax --------===//
9 // This class prints an AVR MCInst to a .s file.
44 case AVR::LDRdPtr:
45 case AVR::LDRdPtrPi:
46 case AVR::LDRdPtrPd:
51 if (Opcode == AVR::LDRdPtrPd)
56 if (Opcode == AVR::LDRdPtrPi)
59 case AVR::STPtrRr:
65 case AVR::STPtrPiRr:
66 case AVR
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H A DAVRMCExpr.cpp1 //===-- AVRMCExpr.cpp - AVR specific MC expression classes ----------------===//
144 AVR::Fixups AVRMCExpr::getFixupKind() const {
145 AVR::Fixups Kind = AVR::Fixups::LastTargetFixupKind;
149 Kind = isNegated() ? AVR::fixup_lo8_ldi_neg : AVR::fixup_lo8_ldi;
152 Kind = isNegated() ? AVR::fixup_hi8_ldi_neg : AVR::fixup_hi8_ldi;
155 Kind = isNegated() ? AVR::fixup_hh8_ldi_neg : AVR
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H A DAVRAsmBackend.cpp1 //===-- AVRAsmBackend.cpp - AVR Asm Backend ------------------------------===//
82 AVR::fixups::adjustBranchTarget(Value);
95 AVR::fixups::adjustBranchTarget(Value);
254 case AVR::fixup_7_pcrel:
257 case AVR::fixup_13_pcrel:
260 case AVR::fixup_call:
263 case AVR::fixup_ldi:
266 case AVR::fixup_lo8_ldi:
269 case AVR::fixup_lo8_ldi_pm:
270 case AVR
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H A DAVRMCCodeEmitter.cpp1 //===-- AVRMCCodeEmitter.cpp - Convert AVR Code to Machine Code -----------===//
77 bool IsRegX = MI.getOperand(0).getReg() == AVR::R27R26 ||
78 MI.getOperand(1).getReg() == AVR::R27R26;
80 bool IsPredec = Opcode == AVR::LDRdPtrPd || Opcode == AVR::STPtrPdRr;
81 bool IsPostinc = Opcode == AVR::LDRdPtrPi || Opcode == AVR::STPtrPiRr;
91 template <AVR::Fixups Fixup>
109 AVR::fixups::adjustBranchTarget(target);
122 case AVR
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H A DAVRFixupKinds.h1 //===-- AVRFixupKinds.h - AVR Specific Fixup Entries ------------*- C++ -*-===//
15 namespace AVR { namespace in namespace:llvm
24 /// MCFixupKindInfo Infos[AVR::NumTargetFixupKinds]
27 /// A 32-bit AVR fixup.
37 /// The nonmenclature is that AVR branch targets are
136 /// All branch targets in AVR are rightshifted by 1 to take advantage
145 } // end of namespace llvm::AVR
H A DAVRInstPrinter.h1 //===- AVRInstPrinter.h - Convert AVR MCInst to assembly syntax -*- C++ -*-===//
9 // This class prints an AVR MCInst to a .s file.
22 /// Prints AVR instructions to a textual stream.
37 unsigned AltIdx = AVR::NoRegAltName);
H A DAVRMCCodeEmitter.h1 //===-- AVRMCCodeEmitter.h - Convert AVR Code to Machine Code -------------===//
36 /// Writes AVR machine code to a stream.
50 template <AVR::Fixups Fixup>
72 template <AVR::Fixups Fixup, unsigned Offset>
H A DAVRAsmBackend.h1 //===-- AVRAsmBackend.h - AVR Asm Backend --------------------------------===//
9 // \file The AVR assembly backend implementation.
30 /// Utilities for manipulating generated AVR machine code.
50 return AVR::NumTargetFixupKinds;
H A DAVRMCExpr.h1 //===-- AVRMCExpr.h - AVR specific MC expression classes --------*- C++ -*-===//
18 /// A expression in AVR machine code.
40 /// Creates an AVR machine code expression.
50 AVR::Fixups getFixupKind() const;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp1 //===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===//
9 // This file contains the AVR implementation of the TargetRegisterInfo class.
23 #include "AVR.h"
57 Reserved.set(AVR::R0);
58 Reserved.set(AVR::R1);
59 Reserved.set(AVR::R1R0);
62 Reserved.set(AVR::SPL);
63 Reserved.set(AVR::SPH);
64 Reserved.set(AVR::SP);
75 Reserved.set(AVR
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H A DAVRFrameLowering.cpp1 //===-- AVRFrameLowering.cpp - AVR Frame Information ----------------------===//
9 // This file contains the AVR implementation of TargetFrameLowering class.
15 #include "AVR.h"
64 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs))
71 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
72 .addReg(AVR::R29R28, RegState::Kill)
80 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
81 .addReg(AVR::R1R0, RegState::Kill)
84 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR
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H A DAVRInstrInfo.cpp1 //===-- AVRInstrInfo.cpp - AVR Instruction Information --------------------===//
9 // This file contains the AVR implementation of the TargetInstrInfo class.
27 #include "AVR.h"
39 : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI() {}
49 // Not all AVR devices support the 16-bit `MOVW` instruction.
50 if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) {
52 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg)
61 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo)
63 BuildMI(MBB, MI, DL, get(AVR
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H A DAVRExpandPseudoInsts.cpp15 #include "AVR.h"
28 #define AVR_EXPAND_PSEUDO_NAME "AVR pseudo instruction expansion pass"
33 /// actual AVR instructions.
54 const unsigned SCRATCH_REGISTER = AVR::R0;
56 const unsigned ZERO_REGISTER = AVR::R1;
211 if (Op == AVR::ANDIRdK && ImmVal == 0xff)
215 if (Op == AVR::ORIRdK && ImmVal == 0x0)
259 bool AVRExpandPseudo::expand<AVR::ADDWRdRr>(Block &MBB, BlockIt MBBI) {
260 return expandArith(AVR::ADDRdRr, AVR
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H A DAVRISelLowering.cpp1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
9 // This file defines the interfaces that AVR uses to lower LLVM code into a
26 #include "AVR.h"
38 addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
39 addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
47 setStackPointerRegisterToSaveRestore(AVR::SP);
159 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
274 assert(!VT.isVector() && "No AVR SetCC type for vectors!");
421 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
441 /// Returns appropriate AVR CM
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H A DAVRRelaxMemOperations.cpp14 #include "AVR.h"
26 #define AVR_RELAX_MEM_OPS_NAME "AVR memory operation relaxation pass"
88 bool AVRRelaxMem::relax<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
99 buildMI(MBB, MBBI, AVR::PUSHWRr)
103 buildMI(MBB, MBBI, AVR::SBCIWRdK)
110 buildMI(MBB, MBBI, AVR::STWPtrRr)
115 buildMI(MBB, MBBI, AVR::POPWRd)
133 RELAX(AVR::STDWPtrQRr);
H A DAVRTargetObjectFile.cpp1 //===-- AVRTargetObjectFile.cpp - AVR Object Files ------------------------===//
18 #include "AVR.h"
33 if (AVR::isProgramMemoryAddress(GO) && !GO->hasSection())
H A DAVRISelDAGToDAG.cpp1 //===-- AVRISelDAGToDAG.cpp - A dag to dag inst selector for AVR ----------===//
9 // This file defines an instruction selector for the AVR target.
13 #include "AVR.h"
26 /// Lowers LLVM IR (in DAG form) to AVR MC instructions (in DAG form).
33 return "AVR DAG->DAG Instruction Selection";
144 Opcode = (isPre) ? AVR::LDRdPtrPd : AVR::LDRdPtrPi;
152 Opcode = (isPre) ? AVR::LDWRdPtrPd : AVR::LDWRdPtrPi;
185 Opcode = AVR
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H A DAVR.h1 //===-- AVR.h - Top-level interface for AVR representation ------*- C++ -*-===//
10 // AVR back-end.
36 /// Contains the AVR backend.
37 namespace AVR { namespace in namespace:llvm
39 /// An integer that identifies all of the supported AVR address spaces.
53 } // end of namespace AVR
H A DAVRAsmPrinter.cpp1 //===-- AVRAsmPrinter.cpp - AVR LLVM assembly writer ----------------------===//
10 // of machine-dependent LLVM code to GAS-format AVR assembly language.
14 #include "AVR.h"
37 /// An AVR assembly code printer.
44 StringRef getPassName() const override { return "AVR Assembly Printer"; }
121 Reg = TRI.getSubReg(Reg, ByteNumber % BytesPerReg ? AVR::sub_hi
122 : AVR::sub_lo);
151 if (MI->getOperand(OpNum).getReg() == AVR::R31R30) {
154 assert(MI->getOperand(OpNum).getReg() == AVR::R29R28 &&
/freebsd-11-stable/contrib/llvm-project/lld/ELF/Arch/
H A DAVR.cpp1 //===- AVR.cpp ------------------------------------------------------------===//
9 // AVR is a Harvard-architecture 8-bit micrcontroller designed for small
10 // baremetal programs. All AVR-family processors have 32 8-bit registers.
11 // The tiniest AVR has 32 byte RAM and 1 KiB program memory, and the largest
23 // Note that the current AVR support is very preliminary so you can't
44 class AVR final : public TargetInfo {
46 AVR();
53 AVR::AVR() { noneRel = R_AVR_NONE; } function in class:lld::elf::AVR
55 RelExpr AVR
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/freebsd-11-stable/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DAVR.h1 //===--- AVR.h - AVR Tool and ToolChain Implementations ---------*- C++ -*-===//
42 namespace AVR { namespace in namespace:clang::driver::tools
46 : GnuTool("AVR::Linker", "avr-ld", TC), Triple(Triple),
60 } // end namespace AVR
H A DAVR.cpp1 //===--- AVR.cpp - AVR ToolChain Implementations ----------------*- C++ -*-===//
9 #include "AVR.h"
30 // TODO: Consider merging this into the AVR device table
31 // array in Targets/AVR.cpp.
46 /// AVR Toolchain
97 return new tools::AVR::Linker(getTriple(), *this, LinkStdlib);
100 void AVR::Linker::ConstructJob(Compilation &C, const JobAction &JA,
105 // Compute information about the target AVR.
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp1 //===---- AVRAsmParser.cpp - Parse AVR assembly to MCInst instructions ----===//
9 #include "AVR.h"
40 /// Parses AVR assembly from a stream.
76 unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) { argument
77 MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID];
102 /// An parsed AVR assembly operand.
339 // GCC supports case insensitive register names. Some of the AVR registers
343 if (RegNum == AVR::NoRegister) {
346 if (RegNum == AVR::NoRegister) {
356 if (RegNum == AVR
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