Searched refs:ANY_EXTEND_VECTOR_INREG (Results 1 - 13 of 13) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 549 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an
558 ANY_EXTEND_VECTOR_INREG, enumerator in enum:llvm::ISD::NodeType
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 105 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, T, Custom);
138 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, T, Custom);
1436 assert(Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG);
1580 case ISD::ANY_EXTEND_VECTOR_INREG: return LowerHvxExtend(Op, DAG);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 66 case ISD::ANY_EXTEND_VECTOR_INREG:
392 case ISD::ANY_EXTEND_VECTOR_INREG:
859 case ISD::ANY_EXTEND_VECTOR_INREG:
1978 case ISD::ANY_EXTEND_VECTOR_INREG:
2785 case ISD::ANY_EXTEND_VECTOR_INREG:
3251 return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, WidenVT, InOp);
3361 case ISD::ANY_EXTEND_VECTOR_INREG:
3375 case ISD::ANY_EXTEND_VECTOR_INREG:
4315 return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, InOp);
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| H A D | LegalizeVectorOps.cpp | 110 /// Implement expansion for ANY_EXTEND_VECTOR_INREG.
439 case ISD::ANY_EXTEND_VECTOR_INREG:
851 case ISD::ANY_EXTEND_VECTOR_INREG:
1086 "ANY_EXTEND_VECTOR_INREG vector size mismatch");
1118 SDValue Op = DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Src);
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| H A D | SelectionDAGDumper.cpp | 323 case ISD::ANY_EXTEND_VECTOR_INREG: return "any_extend_vector_inreg";
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| H A D | TargetLowering.cpp | 1695 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND;
1728 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND;
1759 case ISD::ANY_EXTEND_VECTOR_INREG: {
1764 bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG;
2512 case ISD::ANY_EXTEND_VECTOR_INREG:
2525 if (Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG &&
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| H A D | LegalizeIntegerTypes.cpp | 110 case ISD::ANY_EXTEND_VECTOR_INREG:
4372 case ISD::ANY_EXTEND_VECTOR_INREG:
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| H A D | DAGCombiner.cpp | 10606 if ((N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG ||
18920 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND_VECTOR_INREG, OutVT))
18922 DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG,
18946 if (Opcode != ISD::ANY_EXTEND_VECTOR_INREG &&
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| H A D | SelectionDAG.cpp | 4688 case ISD::ANY_EXTEND_VECTOR_INREG:
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 697 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 879 case ISD::ANY_EXTEND_VECTOR_INREG: {
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| H A D | X86ISelLowering.cpp | 2015 setTargetDAGCombine(ISD::ANY_EXTEND_VECTOR_INREG);
6005 case ISD::ANY_EXTEND_VECTOR_INREG:
6006 return ISD::ANY_EXTEND_VECTOR_INREG;
7470 case ISD::ANY_EXTEND_VECTOR_INREG: {
7481 (ISD::ANY_EXTEND == Opcode || ISD::ANY_EXTEND_VECTOR_INREG == Opcode);
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 5512 Opcode == ISD::ANY_EXTEND_VECTOR_INREG) &&
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