Searched refs:WRITE4 (Results 1 - 25 of 29) sorted by relevance

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/freebsd-10.3-release/sys/arm/freescale/vybrid/
H A Dvf_dcu4.c228 WRITE4(sc, DCU_INT_STATUS, reg);
293 WRITE4(sc, DCU_DISP_SIZE, reg);
298 WRITE4(sc, DCU_HSYN_PARA, reg);
303 WRITE4(sc, DCU_VSYN_PARA, reg);
305 WRITE4(sc, DCU_BGND, 0);
306 WRITE4(sc, DCU_DIV_RATIO, panel->clk_div);
309 WRITE4(sc, DCU_SYNPOL, reg);
315 WRITE4(sc, DCU_THRESHOLD, reg);
318 WRITE4(sc, DCU_INT_MASK, 0xffffffff);
322 WRITE4(s
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H A Dvf_anadig.c143 WRITE4(sc, pll_ctrl, reg);
151 WRITE4(sc, pll_ctrl, reg);
171 WRITE4(sc, ANADIG_PLL4_CTRL, reg);
172 WRITE4(sc, ANADIG_PLL4_NUM, mfn);
173 WRITE4(sc, ANADIG_PLL4_DENOM, mfd);
211 WRITE4(sc, ANADIG_REG_3P0, reg);
216 WRITE4(sc, USB_MISC(0), reg);
220 WRITE4(sc, USB_MISC(1), reg);
H A Dvf_common.h31 #define WRITE4(_sc, _reg, _val) \ macro
H A Dvf_nfc.c201 WRITE4(sc, NFC_SECSZ, 2048);
222 WRITE4(sc, NFC_CFG, reg);
245 WRITE4(sc, NFC_CMD2, reg);
261 WRITE4(sc, NFC_CMD1, reg);
268 WRITE4(sc, NFC_CMD2, reg);
274 WRITE4(sc, NFC_CMD2, reg);
282 WRITE4(sc, NFC_CAR, reg);
292 WRITE4(sc, NFC_RAR, reg);
297 WRITE4(sc, NFC_CMD2, reg);
H A Dvf_sai.c362 WRITE4(sc, I2S_TCR2, reg);
627 WRITE4(sc, I2S_TCSR, reg);
631 WRITE4(sc, I2S_TCR3, reg);
634 WRITE4(sc, I2S_TCR1, reg);
640 WRITE4(sc, I2S_TCR2, reg);
646 WRITE4(sc, I2S_TCR3, reg);
655 WRITE4(sc, I2S_TCR4, reg);
664 WRITE4(sc, I2S_TCR5, reg);
670 WRITE4(sc, I2S_TCSR, reg);
H A Dvf_ccm.c382 WRITE4(sc, clk->sel_reg, reg);
389 WRITE4(sc, clk->reg, reg);
464 WRITE4(sc, CCM_CCR, reg);
478 WRITE4(sc, CCM_CCGR(i), 0xffffffff);
H A Dvf_gpio.c267 WRITE4(sc, GPIO_PTOR(i), (1 << (i % 32)));
291 WRITE4(sc, GPIO_PCOR(pin->gp_pin),
337 WRITE4(sc, GPIO_PSOR(i), (1 << (i % 32)));
339 WRITE4(sc, GPIO_PCOR(i), (1 << (i % 32)));
H A Dvf_tcon.c84 WRITE4(tcon_sc, TCON0_CTRL1, TCON_BYPASS);
H A Dvf_edma.c201 WRITE4(sc, DMA_ERQ, reg);
248 WRITE4(sc, DMA_ERQ, reg);
253 WRITE4(sc, DMA_EEI, reg);
H A Dvf_src.c96 WRITE4(src_sc, SRC_SCR, SW_RST);
H A Dvf_port.c123 WRITE4(sc, PORT_PCR(i), reg);
180 WRITE4(sc, PORT_PCR(pnum), reg);
H A Dvf_iomuxc.c162 WRITE4(sc, IOMUXC(pin), pin_cfg);
/freebsd-10.3-release/sys/arm/freescale/imx/
H A Dimx6_sdma.c68 #define WRITE4(_sc, _reg, _val) \ macro
95 WRITE4(sc, SDMAARM_INTR, pending);
113 WRITE4(sc, SDMAARM_HSTART, (1 << i));
138 WRITE4(sc, SDMAARM_HSTART, (1 << chn));
150 WRITE4(sc, SDMAARM_STOP_STAT, (1 << chn));
219 WRITE4(sc, SDMAARM_EVTOVR, reg);
227 WRITE4(sc, SDMAARM_HOSTOVR, reg);
235 WRITE4(sc, SDMAARM_DSPOVR, reg);
263 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);
264 WRITE4(s
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H A Dimx_gpt.c59 #define WRITE4(_sc, _r, _v) \ macro
64 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
66 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
190 WRITE4(sc, IMX_GPT_CR, 0);
191 WRITE4(sc, IMX_GPT_IR, 0);
201 WRITE4(sc, IMX_GPT_CR, ctlreg);
211 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR);
224 WRITE4(sc, IMX_GPT_PR, prescale);
227 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL);
230 WRITE4(s
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H A Dimx6_audmux.c59 #define WRITE4(_sc, _reg, _val) \ macro
110 WRITE4(sc, AUDMUX_PTCR(audmux_port), reg);
114 WRITE4(sc, AUDMUX_PDCR(audmux_port), reg);
H A Dimx_gpio.c66 #define WRITE4(_sc, _r, _v) \ macro
71 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
73 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
339 WRITE4(sc, IMX_GPIO_DR_REG,
355 WRITE4(sc, IMX_GPIO_ISR_REG, input);
H A Dimx6_ssi.c67 #define WRITE4(_sc, _reg, _val) \ macro
532 WRITE4(sc, SSI_SIER, reg);
549 WRITE4(sc, SSI_SIER, reg);
686 WRITE4(sc, SSI_STCCR, reg);
691 WRITE4(sc, SSI_SFCSR, reg);
704 WRITE4(sc, SSI_STCR, reg);
711 WRITE4(sc, SSI_SCR, reg);
/freebsd-10.3-release/sys/dev/hatm/
H A Dif_hatm.c513 WRITE4(sc, HE_REGO_RESET_CNTL, 0x00);
515 WRITE4(sc, HE_REGO_RESET_CNTL, 0xff);
548 WRITE4(sc, HE_REGO_HOST_CNTL, v);
587 WRITE4(sc, HE_REGO_LB_SWAP, v);
606 WRITE4(sc, HE_REGO_HOST_CNTL, val);
611 WRITE4(sc, HE_REGO_HOST_CNTL, val | readtab[i]);
618 WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++] |
622 WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++] |
629 WRITE4(sc, HE_REGO_HOST_CNTL, val);
635 WRITE4(s
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H A Dif_hatmvar.h476 #define WRITE4(SC,OFF,VAL) bus_space_write_4(SC->memt, SC->memh, (OFF), (VAL)) macro
488 #define WRITE_SUNI(SC,OFF,VAL) WRITE4(SC, HE_REGO_SUNI + 4 * (OFF), (VAL))
492 WRITE4(SC, HE_REGO_LB_MEM_ADDR, (OFF)); \
493 WRITE4(SC, HE_REGO_LB_MEM_ACCESS, \
501 WRITE4(SC, HE_REGO_LB_MEM_ADDR, (OFF)); \
502 WRITE4(SC, HE_REGO_LB_MEM_DATA, (VAL)); \
503 WRITE4(SC, HE_REGO_LB_MEM_ACCESS, \
511 WRITE4(SC, HE_REGO_CON_DAT, (VAL)); \
512 WRITE4(SC, HE_REGO_CON_CTL, \
520 WRITE4(S
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/freebsd-10.3-release/sys/arm/samsung/exynos/
H A Dexynos5_common.h31 #define WRITE4(_sc, _reg, _val) \ macro
H A Dexynos5_fimd.c265 WRITE4(sc,VIDCON0,reg);
282 WRITE4(sc, VIDW00ADD0B0, reg);
284 WRITE4(sc, VIDW00ADD1B0, reg);
285 WRITE4(sc, VIDW00ADD2, sc->sc_info.fb_stride);
289 WRITE4(sc,VIDOSD0B,reg);
292 WRITE4(sc,VIDOSD0C,reg);
297 WRITE4(sc,SHADOWCON,reg);
302 WRITE4(sc,WINCON0,reg);
305 WRITE4(sc, DPCLKCON, DPCLKCON_EN);
H A Dexynos5_pad.c78 #define WRITE4(_sc, _port, _reg, _val) \ macro
289 WRITE4(sc, gpio_map[i].port, gpio_map[i].pend, reg);
343 WRITE4(sc, bank.port, bank.con, reg);
358 WRITE4(sc, bank.port, bank.ext_con, reg);
363 WRITE4(sc, bank.port, bank.mask, reg);
581 WRITE4(sc, bank.port, bank.con + 0x4, reg);
618 WRITE4(sc, bank.port, bank.con, reg);
623 WRITE4(sc, bank.port, bank.con, reg);
677 WRITE4(sc, bank.port, bank.con + 0x4, reg);
/freebsd-10.3-release/sys/dev/agp/
H A Dagp_ati.c59 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v) macro
233 WRITE4(ATI_GART_FEATURE_ID, 0x00060000);
238 WRITE4(ATI_GART_BASE, sc->ag_pdir);
259 WRITE4(ATI_GART_BASE, 0);
347 WRITE4(ATI_GART_CACHE_CNTRL, 1);
H A Dagp_amd.c59 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v) macro
253 WRITE4(AGP_AMD751_ATTBASE, gatt->ag_pdir);
288 WRITE4(AGP_AMD751_ATTBASE, 0);
371 WRITE4(AGP_AMD751_TLBCTRL, 1);
/freebsd-10.3-release/sys/dev/fatm/
H A Dif_fatm.c192 WRITE4(sc, q->q.card + FATMOC_GETOC3_BUF, 0);
194 WRITE4(sc, q->q.card + FATMOC_OP,
281 WRITE4(sc, q->q.card + FATMOC_GETOC3_BUF, sc->reg_mem.paddr);
283 WRITE4(sc, q->q.card + FATMOC_OP,
381 WRITE4(sc, FATMO_HIMR, 1);
419 WRITE4(sc, FATMO_APP_BASE, FATMO_COMMON_ORIGIN);
422 WRITE4(sc, FATMO_UART_TO_960, XMIT_READY);
425 WRITE4(sc, FATMO_UART_TO_HOST, XMIT_READY);
428 WRITE4(sc, FATMO_BOOT_STATUS, COLD_START);
579 WRITE4(s
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