dev/hatm/if_hatm.c

513 	WRITE4(sc, HE_REGO_RESET_CNTL, 0x00);
515 	WRITE4(sc, HE_REGO_RESET_CNTL, 0xff);
548 		WRITE4(sc, HE_REGO_HOST_CNTL, v);
587 	WRITE4(sc, HE_REGO_LB_SWAP, v);
606 	WRITE4(sc, HE_REGO_HOST_CNTL, val);
611 		WRITE4(sc, HE_REGO_HOST_CNTL, val | readtab[i]);
618 		WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++] |
622 		WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++] |
629 	WRITE4(sc, HE_REGO_HOST_CNTL, val);
635 		WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++]);
641 		WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++]);
645 	WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++]);
733 	WRITE4(sc, HE_REGO_IRQ_BASE(group), 0);
734 	WRITE4(sc, HE_REGO_IRQ_HEAD(group), 0);
735 	WRITE4(sc, HE_REGO_IRQ_CNTL(group), 0);
736 	WRITE4(sc, HE_REGO_IRQ_DATA(group), 0);
762 	WRITE4(sc, HE_REGO_IRQ_BASE(group), q->mem.paddr);
763 	WRITE4(sc, HE_REGO_IRQ_HEAD(group),
766 	WRITE4(sc, HE_REGO_IRQ_CNTL(group), q->line);
767 	WRITE4(sc, HE_REGO_IRQ_DATA(group), 0);
806 	WRITE4(sc, HE_REGO_TSRB_BA, sc->tsrb);
807 	WRITE4(sc, HE_REGO_TSRC_BA, sc->tsrc);
808 	WRITE4(sc, HE_REGO_TSRD_BA, sc->tsrd);
809 	WRITE4(sc, HE_REGO_TMABR_BA, tabr);
810 	WRITE4(sc, HE_REGO_TPD_BA, mtpd);
812 	WRITE4(sc, HE_REGO_RCMRSRB_BA, sc->rsrb);
813 	WRITE4(sc, HE_REGO_RCMLBM_BA, mlbm);
814 	WRITE4(sc, HE_REGO_RCMABR_BA, rabr);
851 	WRITE4(sc, HE_REGO_RLBF_H(num), lbufd_index);
870 	WRITE4(sc, HE_REGO_RLBF_T(num), lbufd_index - 2);
871 	WRITE4(sc, HE_REGO_RLBF_C(num), numbuffs);
904 	WRITE4(sc, HE_REGO_TLBF_H, lbufd_index);
922 	WRITE4(sc, HE_REGO_TLBF_T, lbufd_index - 1);
936 			WRITE4(sc, HE_REGO_INMQ_S(n), 0x10*n+0x000f);
937 			WRITE4(sc, HE_REGO_INMQ_L(n), 0x10*n+0x200f);
941 			WRITE4(sc, HE_REGO_INMQ_S(n), n);
942 			WRITE4(sc, HE_REGO_INMQ_L(n), n+0x8);
1119 	WRITE4(sc, HE_REGO_RBP_S(large, group), 0);
1120 	WRITE4(sc, HE_REGO_RBP_T(large, group), 0);
1121 	WRITE4(sc, HE_REGO_RBP_QI(large, group), 1);
1122 	WRITE4(sc, HE_REGO_RBP_BL(large, group), 0);
1144 	WRITE4(sc, HE_REGO_RBP_S(large, group), q->mem.paddr);
1145 	WRITE4(sc, HE_REGO_RBP_T(large, group), 0);
1146 	WRITE4(sc, HE_REGO_RBP_QI(large, group),
1150 	WRITE4(sc, HE_REGO_RBP_BL(large, group), (q->bsize >> 2) & ~1);
1159 	WRITE4(sc, HE_REGO_RBRQ_ST(group), 0);
1160 	WRITE4(sc, HE_REGO_RBRQ_H(group), 0);
1161 	WRITE4(sc, HE_REGO_RBRQ_Q(group), (1 << HE_REGS_RBRQ_THRESH));
1162 	WRITE4(sc, HE_REGO_RBRQ_I(group), 0);
1181 	WRITE4(sc, HE_REGO_RBRQ_ST(group), rq->mem.paddr);
1182 	WRITE4(sc, HE_REGO_RBRQ_H(group), 0);
1183 	WRITE4(sc, HE_REGO_RBRQ_Q(group),
1186 	WRITE4(sc, HE_REGO_RBRQ_I(group),
1197 	WRITE4(sc, HE_REGO_TBRQ_B_T(group), 0);
1198 	WRITE4(sc, HE_REGO_TBRQ_H(group), 0);
1199 	WRITE4(sc, HE_REGO_TBRQ_S(group), 0);
1200 	WRITE4(sc, HE_REGO_TBRQ_THRESH(group), 1);
1219 	WRITE4(sc, HE_REGO_TBRQ_B_T(group), tq->mem.paddr);
1220 	WRITE4(sc, HE_REGO_TBRQ_H(group), 0);
1221 	WRITE4(sc, HE_REGO_TBRQ_S(group), tq->size - 1);
1222 	WRITE4(sc, HE_REGO_TBRQ_THRESH(group), tq->thresh);
1239 	WRITE4(sc, HE_REGO_TPDRQ_H, tq->mem.paddr);
1240 	WRITE4(sc, HE_REGO_TPDRQ_T, 0);
1241 	WRITE4(sc, HE_REGO_TPDRQ_S, tq->size - 1);
1619 	WRITE4(sc, HE_REGO_SUNI + 4 * reg, regval);
1998 		WRITE4(sc, HE_REGO_SDRAM_CNTL, HE_REGM_SDRAM_64BIT);
2000 		WRITE4(sc, HE_REGO_SDRAM_CNTL, 0);
2006 	WRITE4(sc, HE_REGO_LB_SWAP, v);
2014 	WRITE4(sc, HE_REGO_GRP_1_0_MAP, 0);
2015 	WRITE4(sc, HE_REGO_GRP_3_2_MAP, 0);
2016 	WRITE4(sc, HE_REGO_GRP_5_4_MAP, 0);
2017 	WRITE4(sc, HE_REGO_GRP_7_6_MAP, 0);
2027 	WRITE4(sc, HE_REGO_HOST_CNTL, v);
2069 		WRITE4(sc, HE_REGO_LBARB,
2079 		WRITE4(sc, HE_REGO_SDRAMCON,
2085 		WRITE4(sc, HE_REGO_RCMCONFIG,
2089 		WRITE4(sc, HE_REGO_TCMCONFIG,
2094 		WRITE4(sc, HE_REGO_LBARB,
2104 		WRITE4(sc, HE_REGO_SDRAMCON,
2109 		WRITE4(sc, HE_REGO_RCMCONFIG,
2113 		WRITE4(sc, HE_REGO_TCMCONFIG,
2118 	WRITE4(sc, HE_REGO_LBCONFIG, (sc->cells_per_lbuf * 48));
2120 	WRITE4(sc, HE_REGO_RLBC_H, 0);
2121 	WRITE4(sc, HE_REGO_RLBC_T, 0);
2122 	WRITE4(sc, HE_REGO_RLBC_H2, 0);
2124 	WRITE4(sc, HE_REGO_RXTHRSH, 512);
2125 	WRITE4(sc, HE_REGO_LITHRSH, 256);
2127 	WRITE4(sc, HE_REGO_RLBF0_C, sc->r0_numbuffs);
2128 	WRITE4(sc, HE_REGO_RLBF1_C, sc->r1_numbuffs);
2131 		WRITE4(sc, HE_REGO_RCCONFIG,
2135 		WRITE4(sc, HE_REGO_TXCONFIG,
2140 		WRITE4(sc, HE_REGO_RCCONFIG,
2145 		WRITE4(sc, HE_REGO_TXCONFIG,
2152 	WRITE4(sc, HE_REGO_TXAAL5_PROTO, 0);
2155 		WRITE4(sc, HE_REGO_RHCONFIG,
2160 		WRITE4(sc, HE_REGO_RHCONFIG,
2178 	WRITE4(sc, HE_REGO_MCC, 0);
2179 	WRITE4(sc, HE_REGO_OEC, 0);
2180 	WRITE4(sc, HE_REGO_DCC, 0);
2181 	WRITE4(sc, HE_REGO_CEC, 0);
2225 	WRITE4(sc, HE_REGO_UBUFF_BA, (sc->he622 ? 0x104780 : 0x800));
2232 	WRITE4(sc, HE_REGO_HSP_BA, sc->hsp_mem.paddr);
2244 	WRITE4(sc, HE_REGO_RCCONFIG, v);
2297 	WRITE4(sc, HE_REGO_RCCONFIG, v);
2299 	WRITE4(sc, HE_REGO_RHCONFIG, (0x2 << HE_REGS_RHCONFIG_PTMR_PRE));
2305 	WRITE4(sc, HE_REGO_HOST_CNTL, v);