| /netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | radeon_uvd_v1_0.c | 271 uint32_t rb_bufsz; local
382 rb_bufsz = order_base_2(ring->ring_size);
383 rb_bufsz = (0x1 << 8) | rb_bufsz;
384 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
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| H A D | radeon_ni_dma.c | 196 u32 rb_bufsz; local
215 rb_bufsz = order_base_2(ring->ring_size / 4);
216 rb_cntl = rb_bufsz << 1;
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| H A D | radeon_r600_dma.c | 129 u32 rb_bufsz; local
136 rb_bufsz = order_base_2(ring->ring_size / 4);
137 rb_cntl = rb_bufsz << 1;
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| H A D | radeon_cik_sdma.c | 374 u32 rb_bufsz; local
393 rb_bufsz = order_base_2(ring->ring_size / 4);
394 rb_cntl = rb_bufsz << 1;
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| H A D | radeon_r600.c | 2752 u32 rb_bufsz; local
2762 rb_bufsz = order_base_2(ring->ring_size / 8);
2763 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2814 u32 rb_bufsz; local
2818 rb_bufsz = order_base_2(ring_size / 8);
2819 ring_size = (1 << (rb_bufsz + 1)) * 4;
3504 u32 rb_bufsz; local
3507 rb_bufsz = order_base_2(ring_size / 4);
3508 ring_size = (1 << rb_bufsz) * 4;
3710 int rb_bufsz; local
[all...] |
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_cik_ih.c | 114 int rb_bufsz; local
132 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
136 (rb_bufsz << 1));
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| H A D | amdgpu_ih.c | 49 u32 rb_bufsz; local
53 rb_bufsz = order_base_2(ring_size / 4);
54 ring_size = (1 << rb_bufsz) * 4;
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| H A D | amdgpu_si_ih.c | 68 int rb_bufsz; local
80 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
84 (rb_bufsz << 1) |
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| H A D | amdgpu_iceland_ih.c | 114 int rb_bufsz; local
134 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
137 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
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| H A D | amdgpu_cz_ih.c | 115 int rb_bufsz; local
134 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
137 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
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| H A D | amdgpu_tonga_ih.c | 111 int rb_bufsz; local
130 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
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| H A D | amdgpu_uvd_v4_2.c | 262 uint32_t rb_bufsz; local
372 rb_bufsz = order_base_2(ring->ring_size);
373 rb_bufsz = (0x1 << 8) | rb_bufsz;
374 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
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| H A D | amdgpu_vcn_v2_5.c | 760 uint32_t rb_bufsz, tmp; local
856 rb_bufsz = order_base_2(ring->ring_size);
857 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
892 uint32_t rb_bufsz, tmp; local
1036 rb_bufsz = order_base_2(ring->ring_size);
1037 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1133 uint32_t offset, size, tmp, i, rb_bufsz; local
1250 rb_bufsz = order_base_2(ring->ring_size);
1251 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
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| H A D | amdgpu_uvd_v5_0.c | 300 uint32_t rb_bufsz, tmp; local
397 rb_bufsz = order_base_2(ring->ring_size);
399 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
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| H A D | amdgpu_navi10_ih.c | 83 int rb_bufsz = order_base_2(ih->ring_size / 4); local
91 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
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| H A D | amdgpu_vcn_v1_0.c | 788 uint32_t rb_bufsz, tmp; local
907 rb_bufsz = order_base_2(ring->ring_size);
908 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
962 uint32_t rb_bufsz, tmp; local
1065 rb_bufsz = order_base_2(ring->ring_size);
1066 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
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| H A D | amdgpu_vcn_v2_0.c | 753 uint32_t rb_bufsz, tmp; local
843 rb_bufsz = order_base_2(ring->ring_size);
844 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
879 uint32_t rb_bufsz, tmp; local
1004 rb_bufsz = order_base_2(ring->ring_size);
1005 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
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| H A D | amdgpu_vega10_ih.c | 173 int rb_bufsz = order_base_2(ih->ring_size / 4); local
181 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
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| H A D | amdgpu_sdma_v2_4.c | 420 u32 rb_bufsz; local
444 rb_bufsz = order_base_2(ring->ring_size / 4);
446 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
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| H A D | amdgpu_si_dma.c | 139 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; local
150 rb_bufsz = order_base_2(ring->ring_size / 4);
151 rb_cntl = rb_bufsz << 1;
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| H A D | amdgpu_cik_sdma.c | 441 u32 rb_bufsz; local
467 rb_bufsz = order_base_2(ring->ring_size / 4);
468 rb_cntl = rb_bufsz << 1;
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| H A D | amdgpu_uvd_v6_0.c | 707 uint32_t rb_bufsz, tmp; local
816 rb_bufsz = order_base_2(ring->ring_size);
817 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
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| H A D | amdgpu_gfx_v10_0.c | 2774 u32 rb_bufsz; local
2790 rb_bufsz = order_base_2(ring->ring_size / 8);
2791 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2792 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2831 rb_bufsz = order_base_2(ring->ring_size / 8);
2832 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2833 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2984 uint32_t rb_bufsz; local
3034 rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
3036 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
[all...] |
| H A D | amdgpu_gfx_v6_0.c | 2098 u32 rb_bufsz; local
2114 rb_bufsz = order_base_2(ring->ring_size / 8);
2115 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2195 u32 rb_bufsz; local
2203 rb_bufsz = order_base_2(ring->ring_size / 8);
2204 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2223 rb_bufsz = order_base_2(ring->ring_size / 8);
2224 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
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| H A D | amdgpu_uvd_v7_0.c | 940 uint32_t rb_bufsz, tmp; local
1068 rb_bufsz = order_base_2(ring->ring_size);
1069 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
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