/freebsd-10.2-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | MachineOperand.h | 188 return isReg() ? 0 : SubReg_TargetFlags; 191 assert(!isReg() && "Register operands can't have target flags"); 196 assert(!isReg() && "Register operands can't have target flags"); 223 /// isReg - Tests if this is a MO_Register operand. 224 bool isReg() const { return OpKind == MO_Register; } function in class:llvm::MachineOperand 260 assert(isReg() && "This is not a register operand!"); 265 assert(isReg() && "Wrong MachineOperand accessor"); 270 assert(isReg() && "Wrong MachineOperand accessor"); 275 assert(isReg() && "Wrong MachineOperand accessor"); 280 assert(isReg() [all...] |
H A D | LiveVariables.h | 215 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) { 251 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
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/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.cpp | 30 static bool isReg(const MCInst &MI, unsigned OpNo) { function 31 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); 164 if (Op.isReg()) { 249 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && 251 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS)); 254 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); 257 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); 260 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); 263 return isReg<Mip [all...] |
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/ |
H A D | LiveRegUnits.cpp | 51 if (O->isReg()) { 64 if (!O->isReg() || !O->readsReg() || O->isUndef()) 81 if (O->isReg()) {
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H A D | AntiDepBreaker.h | 64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
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H A D | DeadMachineInstructionElim.cpp | 68 if (MO.isReg() && MO.isDef()) { 125 if (!MO.isReg() || !MO.isDef()) 154 if (MO.isReg() && MO.isDef()) { 173 if (MO.isReg() && MO.isUse()) {
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H A D | MachineInstr.cpp | 92 assert(isReg() && "Wrong MachineOperand accessor"); 113 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); 116 if (isReg() && isOnRegUseList()) 139 bool WasReg = isReg(); 580 if (Operands[i].isReg()) 589 if (Operands[i].isReg()) 642 bool isImpReg = Op.isReg() && Op.isImplicit(); 644 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { 689 if (NewMO->isReg()) { 724 if (Operands[i].isReg()) [all...] |
H A D | ProcessImplicitDefs.cpp | 71 if (MO->isReg() && MO->isUse() && MO->readsReg()) 106 if (!MO->isReg())
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H A D | TargetInstrInfo.cpp | 123 if (HasDef && !MI->getOperand(0).isReg()) 134 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && 193 if (!MI->getOperand(SrcOpIdx1).isReg() || 194 !MI->getOperand(SrcOpIdx2).isReg()) 228 if (MO.isReg()) { 484 if (!MI->getNumOperands() || !MI->getOperand(0).isReg()) 522 if (!MO.isReg()) continue;
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H A D | MachineInstrBundle.cpp | 54 if (MO.isReg() && MO.isInternalRead()) 126 if (!MO.isReg()) 257 if (!MO.isReg() || MO.getReg() != Reg) 294 if (!MO.isReg())
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H A D | StackMaps.cpp | 33 HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && 40 while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() && 58 !(MI->getOperand(ScratchIdx).isReg() && 117 if (MOI->isRegMask() || (MOI->isReg() && MOI->isImplicit()))
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/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 120 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 131 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 143 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 155 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 166 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 178 assert(MI.getOperand(OpNo+1).isReg()); 196 assert(MI.getOperand(OpNo+1).isReg()); 213 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups); 248 if (MO.isReg()) {
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/freebsd-10.2-release/contrib/llvm/lib/Target/Sparc/InstPrinter/ |
H A D | SparcInstPrinter.cpp | 49 if (!MI->getOperand(0).isReg()) 69 if (MO.isReg()) { 96 if (MO.isReg() && MO.getReg() == SP::G0)
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/freebsd-10.2-release/contrib/llvm/include/llvm/MC/MCParser/ |
H A D | MCParsedAsmOperand.h | 47 /// isReg - Is this a register operand? 48 virtual bool isReg() const = 0;
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/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 252 bool isReg() const { return Kind == CV_Register; } function in class:__anon2502::CountValue 256 assert(isReg() && "Wrong CountValue accessor"); 260 assert(isReg() && "Wrong CountValue accessor"); 270 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); } 527 if (Op1.isReg()) { 564 if (InitialValue->isReg()) { 591 if (InitialValue->isReg()) { 598 if (EndValue->isReg()) { 624 if (Start->isReg()) { 629 if (End->isReg()) { [all...] |
H A D | HexagonNewValueJump.cpp | 150 if (II->getOperand(i).isReg() && 474 MI->getOperand(0).isReg() && 482 isSecondOpReg = MI->getOperand(2).isReg(); 516 if (MI->getOperand(0).isReg() && 573 if (MO.isReg() && MO.isUse()) { 580 if (localMO.isReg() && localMO.isUse() && 635 if (cmpInstr->getOperand(0).isReg() && 638 if (cmpInstr->getOperand(1).isReg() &&
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H A D | HexagonVLIWPacketizer.cpp | 356 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) { 483 if (MI->getOperand(opNum).isReg() && 489 if (MI->getOperand(opNum).isReg() && 498 assert(MI->getOperand(1).isReg() && 504 assert(MI->getOperand(0).isReg() && 547 if (GetStoreValueOperand(MI).isReg() && 611 if ( PacketMI->getOperand(opNum).isReg()) 623 if ( MI->getOperand(opNum).isReg()) 677 if (MI->getOperand(opNum).isReg() && 691 GetStoreValueOperand(MI).isReg() [all...] |
H A D | HexagonCopyToCombine.cpp | 120 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isReg()); 131 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm()); 142 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isGlobal()); 214 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill()) 371 if (!Op.isReg() || !Op.isUse() || !Op.getReg()) 401 if (!Op.isReg() || !Op.isDef() || !Op.getReg()) 540 bool IsHiReg = HiOperand.isReg(); 541 bool IsLoReg = LoOperand.isReg();
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/freebsd-10.2-release/contrib/llvm/include/llvm/MC/ |
H A D | MCInst.h | 56 bool isReg() const { return Kind == kRegister; } function in class:llvm::MCOperand 64 assert(isReg() && "This is not a register operand!"); 70 assert(isReg() && "This is not a register operand!");
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H A D | MachineLocation.h | 53 bool isReg() const { return IsRegister; } function
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/freebsd-10.2-release/contrib/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCCodeEmitter.cpp | 104 if (MO.isReg()) 130 if (MO.isReg() || MO.isImm()) 164 if (MO.isReg() || MO.isImm())
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/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCCodeEmitter.cpp | 187 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 203 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 216 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 233 assert(MI.getOperand(OpNo+1).isReg()); 249 assert(MI.getOperand(OpNo+1).isReg()); 276 if (MO.isReg()) {
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/freebsd-10.2-release/contrib/llvm/lib/MC/ |
H A D | MCInst.cpp | 22 else if (isReg())
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/freebsd-10.2-release/contrib/llvm/lib/Target/XCore/InstPrinter/ |
H A D | XCoreInstPrinter.cpp | 74 if (Op.isReg()) {
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/freebsd-10.2-release/contrib/llvm/lib/Target/MSP430/InstPrinter/ |
H A D | MSP430InstPrinter.cpp | 49 if (Op.isReg()) {
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