Searched refs:isPredicated (Results 1 - 25 of 26) sorted by relevance

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/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h133 virtual bool isPredicated(const MachineInstr *MI) const;
134 virtual bool isPredicated(unsigned Opcode) const;
H A DHexagonVLIWPacketizer.cpp465 if (!QII->isPredicated(MI))
599 if (QII->isPredicated(PacketMI)) {
600 if (!QII->isPredicated(MI))
816 if(!QII->isPredicated(*VIN)) continue;
846 assert(QII->isPredicated(MI) && "Must be predicated instruction");
1202 else if (QII->isPredicated(I) &&
1203 QII->isPredicated(J) &&
H A DHexagonInstrInfo.cpp147 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
979 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const { function in class:HexagonInstrInfo
985 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const { function in class:HexagonInstrInfo
994 assert(isPredicated(MI));
1011 assert(isPredicated(MI));
1018 assert(isPredicated(Opcode));
1522 (isPredicated(MI) && isPredicatedNew(MI)));
1536 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
H A DHexagonPeephole.cpp246 if (QII->isPredicated(MI)) {
H A DHexagonNewValueJump.cpp117 if (QII->isPredicated(II))
/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h186 bool isPredicated(const MachineInstr *MI) const;
H A DPPCInstrInfo.cpp908 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const { function in class:PPCInstrInfo
927 return !isPredicated(MI);
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/
H A DCriticalAntiDepBreaker.cpp165 TII->isPredicated(MI);
218 if (!TII->isPredicated(MI)) {
567 TII->isPredicated(MI))
H A DTargetSchedule.cpp272 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
H A DIfConversion.cpp675 bool isPredicated = TII->isPredicated(I); local
682 if (!isPredicated) {
697 if (BBI.ClobbersPred && !isPredicated) {
1488 if (I->isDebugValue() || TII->isPredicated(I))
1544 if (!TII->isPredicated(I) && !MI->isDebugValue()) {
H A DRegisterScavenging.cpp123 bool isPred = TII->isPredicated(MI);
H A DAggressiveAntiDepBreaker.cpp368 TII->isPredicated(MI)) {
435 TII->isPredicated(MI);
H A DTargetInstrInfo.cpp210 return !isPredicated(MI);
H A DBranchFolding.cpp1544 TII->isPredicated(PI))
1625 if (TII->isPredicated(TIB))
H A DMachineVerifier.cpp581 !TII->isPredicated(getBundleStart(&MBB->back()))) {
720 if (MI->isTerminator() && !TII->isPredicated(MI)) {
H A DMachineBasicBlock.cpp646 // is possible. The isPredicated check is needed because this code can be
649 return empty() || !back().isBarrier() || TII->isPredicated(&back());
/freebsd-10.2-release/contrib/llvm/lib/Target/R600/
H A DAMDGPUInstrInfo.h129 bool isPredicated(const MachineInstr *MI) const;
H A DR600InstrInfo.h160 bool isPredicated(const MachineInstr *MI) const;
H A DAMDGPUInstrInfo.cpp242 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const { function in class:AMDGPUInstrInfo
H A DR600Packetizer.cpp86 if (TII->isPredicated(BI))
H A DR600InstrInfo.cpp897 R600InstrInfo::isPredicated(const MachineInstr *MI) const {
/freebsd-10.2-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp169 return !isPredicated(MI);
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp286 while (isPredicated(I) || I->isTerminator()) {
319 CantAnalyze = !isPredicated(I);
327 if (!isPredicated(I) &&
437 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { function in class:ARMBaseInstrInfo
2237 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2244 isPredicated(PotentialAND))
2311 if (isPredicated(MI))
2447 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
3947 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
3952 if (Subtarget.isCortexA9() && !isPredicated(M
[all...]
H A DARMBaseInstrInfo.h75 bool isPredicated(const MachineInstr *MI) const;
/freebsd-10.2-release/contrib/llvm/include/llvm/Target/
H A DTargetInstrInfo.h670 /// isPredicated - Returns true if the instruction is already predicated.
672 virtual bool isPredicated(const MachineInstr *MI) const { function in class:llvm::TargetInstrInfo

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