Searched refs:i16 (Results 1 - 25 of 51) sorted by relevance

123

/freebsd-10.2-release/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/
H A Dtst.signedkeyspos.d66 @i16["mouse", (short)-2] = sum(-2);
67 @i16["dog", (short)-2] = sum(-22);
68 @i16["cat", (short)-2] = sum(-222);
69 @i16["mouse", (short)-1] = sum(-1);
70 @i16["dog", (short)-1] = sum(-11);
71 @i16["cat", (short)-1] = sum(-111);
72 @i16["mouse", (short)0] = sum(0);
73 @i16["dog", (short)0] = sum(10);
74 @i16["cat", (short)0] = sum(100);
75 @i16["mous
[all...]
H A Dtst.signedkeys.d101 @i16[(short)-2] = sum(-2);
102 @i16[(short)-1] = sum(-1);
103 @i16[(short)0] = sum(0);
104 @i16[(short)1] = sum(1);
105 @i16[(short)2] = sum(2);
/freebsd-10.2-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp268 MVT::i16, AM.Disp,
271 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
274 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
276 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
281 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i16);
317 case MVT::i16:
342 case MVT::i16:
350 VT, MVT::i16, MVT::Other,
365 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
371 VT, MVT::i16, MV
[all...]
H A DMSP430ISelLowering.cpp68 addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
84 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
93 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
98 setOperationAction(ISD::SRA, MVT::i16, Custom);
99 setOperationAction(ISD::SHL, MVT::i16, Custom);
100 setOperationAction(ISD::SRL, MVT::i16, Custom);
103 setOperationAction(ISD::ROTL, MVT::i16, Expand);
104 setOperationAction(ISD::ROTR, MVT::i16, Expand);
105 setOperationAction(ISD::GlobalAddress, MVT::i16, Custo
[all...]
/freebsd-10.2-release/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp261 case MVT::i16:
290 case MVT::i16:
320 case MVT::i16:
343 case MVT::i16:
372 case MVT::i16:
395 case MVT::i16:
503 case MVT::i16:
527 case MVT::i16:
557 case MVT::i16:
581 case MVT::i16
[all...]
H A DNVPTXISelLowering.cpp126 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
138 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
164 setOperationAction(ISD::ROTL, MVT::i16, Expand);
165 setOperationAction(ISD::ROTR, MVT::i16, Expand);
168 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
197 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
224 setOperationAction(ISD::CTLZ, MVT::i16, Legal);
227 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Legal);
230 setOperationAction(ISD::CTTZ, MVT::i16, Expan
[all...]
/freebsd-10.2-release/contrib/netbsd-tests/include/
H A Dt_inttypes.c41 int16_t i16 = 0; local
75 PRINT(PRId16, i16);
90 PRINT(PRIi16, i16);
166 SCAN(SCNd16, i16);
181 SCAN(SCNi16, i16);
/freebsd-10.2-release/contrib/netbsd-tests/ipf/
H A Dt_filter_parse.sh101 test_case i16 itest text ipf
127 atf_add_test_case i16
/freebsd-10.2-release/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/typedef/
H A Dtst.TypedefDataAssign.d85 new_int16 i16;
/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp276 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
458 case MVT::i16:
584 case MVT::i16:
750 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
771 case MVT::i16:
929 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
951 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
1090 if (DestVT != MVT::i16 && DestVT != MVT::i8)
1314 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1338 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetV
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H A DPPCISelDAGToDAG.cpp1032 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1038 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
1044 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1049 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
1066 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1072 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
1078 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
1084 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp306 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
307 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
308 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 },
309 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 },
337 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 },
338 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 },
339 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 },
340 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 },
361 // i16 -> i64 requires two dependent operations.
362 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16,
[all...]
H A DARMSelectionDAGInfo.cpp98 VT = MVT::i16;
121 VT = MVT::i16;
H A DARMFastISel.cpp604 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
835 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
952 case MVT::i16:
1073 case MVT::i16:
1198 case MVT::i16:
1468 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1504 case MVT::i16:
1531 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1649 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1656 if (SrcVT == MVT::i16 || SrcV
[all...]
/freebsd-10.2-release/sys/contrib/octeon-sdk/
H A Dcvmx-fau.h301 uint64_t i16; member in union:__anon7332
304 result.i16 = cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value));
/freebsd-10.2-release/contrib/llvm/include/llvm/CodeGen/
H A DValueTypes.h45 i16 = 3, // This is a 16 bit integer value enumerator in enum:llvm::MVT::SimpleValueType
77 v1i16 = 26, // 1 x i16
78 v2i16 = 27, // 2 x i16
79 v4i16 = 28, // 4 x i16
80 v8i16 = 29, // 8 x i16
81 v16i16 = 30, // 16 x i16
82 v32i16 = 31, // 32 x i16
285 case v32i16: return i16;
380 case i16 :
490 return MVT::i16;
[all...]
/freebsd-10.2-release/contrib/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp619 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
622 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1319 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1321 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1741 // A special case for i16, which needs truncating as, in most cases, it's
1744 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1805 case MVT::i16:
1943 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
2007 if (LdVT == MVT::i16) return X86::DEC16m;
2013 if (LdVT == MVT::i16) retur
[all...]
H A DX86SelectionDAGInfo.cpp93 AVT = MVT::i16;
215 AVT = MVT::i16;
H A DX86FastISel.cpp194 case MVT::i16:
257 case MVT::i16: Opc = X86::MOV16mr; break;
310 case MVT::i16: Opc = X86::MOV16mi; break;
841 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16)
928 case MVT::i16: return X86::CMP16rr;
946 case MVT::i16: return X86::CMP16ri;
1094 case MVT::i16: MovInst = X86::MOVZX32rr16; break;
1208 case MVT::i16: TestOpc = X86::TEST16ri; break;
1318 const static unsigned NumTypes = 4; // i8, i16, i32, i64
1361 }, // i16
[all...]
H A DX86ISelLowering.cpp225 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
288 addRegisterClass(MVT::i16, &X86::GR16RegClass);
297 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
301 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
317 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 // SSE has no i16 to fp conversion, only i32
339 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
343 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
347 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promot
[all...]
/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp118 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
156 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
231 LocVT == MVT::i16) {
621 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
869 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
1165 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
1166 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
1167 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
1168 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
1302 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Lega
[all...]
H A DHexagonVarargsCallingConvention.h49 LocVT == MVT::i16 ||
/freebsd-10.2-release/sys/cddl/contrib/opensolaris/uts/common/os/
H A Dfm.c230 uint16_t i16; local
267 (void) nvpair_value_int16(nvp, (void *)&i16);
268 c = fm_printf(d + 1, c, cols, "%x", i16);
272 (void) nvpair_value_uint16(nvp, &i16);
273 c = fm_printf(d + 1, c, cols, "%x", i16);
/freebsd-10.2-release/contrib/llvm/lib/IR/
H A DValueTypes.cpp117 case MVT::i16: return "i16";
188 case MVT::i16: return Type::getInt16Ty(Context);
/freebsd-10.2-release/contrib/llvm/lib/Target/R600/
H A DAMDILISelLowering.cpp44 (int)MVT::i16,
63 (int)MVT::i16,
298 } else if (OVT.getScalarType() == MVT::i16
315 } else if (OVT.getScalarType() == MVT::i16) {

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