Lines Matching refs:i16
225 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
288 addRegisterClass(MVT::i16, &X86::GR16RegClass);
297 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
301 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
317 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 // SSE has no i16 to fp conversion, only i32
339 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
343 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
347 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
362 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
366 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
374 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
441 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
447 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
468 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
487 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
502 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
509 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
515 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
521 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
1070 // i8 and i16 vectors are custom , because the source register and source
1729 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1816 MVT::i16));
4827 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4829 // Generate shuffles which repeat i16 and i8 several times until they can be
4895 // All i16 and i8 vector types can't be used directly by a generic shuffle
4897 // which repeat i16 and i8 several times until they fit in i32, and then can
4900 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5247 MVT::i16, Op.getOperand(i-1));
5250 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5251 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5254 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5744 DAG.getConstant(Immediate, MVT::i16));
5790 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5791 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5792 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5931 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6477 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6479 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6574 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6585 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6588 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6592 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6593 DAG.getConstant(0xFF00, MVT::i16));
6600 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6603 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6607 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6608 DAG.getConstant(0x00FF, MVT::i16));
6609 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
7601 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7704 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
8484 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8803 DstTy.getSimpleVT() >= MVT::i16 &&
8828 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
9661 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9688 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9689 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9690 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9752 // the encoding for the i16 version is larger than the i32 version.
9753 // Also promote i16 to i32 for performance / code size reason.
9755 LHS.getValueType() == MVT::i16)
9937 // But there is no compare instruction for i8 and i16 elements.
12131 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12146 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12160 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12294 Ops, array_lengthof(Ops), MVT::i16,
12298 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12303 DAG.getNode(ISD::SRL, DL, MVT::i16,
12304 DAG.getNode(ISD::AND, DL, MVT::i16,
12305 CWD, DAG.getConstant(0x800, MVT::i16)),
12308 DAG.getNode(ISD::SRL, DL, MVT::i16,
12309 DAG.getNode(ISD::AND, DL, MVT::i16,
12310 CWD, DAG.getConstant(0x400, MVT::i16)),
12314 DAG.getNode(ISD::AND, DL, MVT::i16,
12315 DAG.getNode(ISD::ADD, DL, MVT::i16,
12316 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12317 DAG.getConstant(1, MVT::i16)),
12318 DAG.getConstant(3, MVT::i16));
13149 // i16, or i32.
13150 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
13215 case MVT::i16: Reg = X86::AX; size = 2; break;
13999 case MVT::i16:
14030 // i16 instructions are longer (0x66 prefix) and potentially slower.
14031 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
14149 case MVT::i16: return X86::LCMPXCHG16;
14162 case MVT::i16: return X86::MOV16rm;
14255 case MVT::i16: return X86::CMOV_GR16;
14476 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
16418 Vec = DAG.getNode(ISD::BITCAST, dl, MVT::i16, Vec);
16763 // The same situation for all 128 and 256-bit vectors of i8 and i16
16767 OpVT.getVectorElementType() == MVT::i16)) {
16903 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
17246 // This is efficient for any integer data type (including i8/i16) and
17264 // for any integer data type, including i8/i16.
17940 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
19208 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19209 /// instruction encodings are longer and some i16 instructions are slow.
19213 if (VT != MVT::i16)
19240 if (VT != MVT::i16)
19378 // rorw $$8, ${0:w} --> llvm.bswap.i16
19738 if (VT == MVT::i16)
19750 if (VT == MVT::i16)
19761 if (VT == MVT::i16)
19769 if (VT == MVT::i16)