Searched refs:WRITE_REG32 (Results 1 - 12 of 12) sorted by relevance
/freebsd-10.1-release/sys/dev/qlxge/ |
H A D | qls_hw.c | 269 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); 270 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower); 279 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); 280 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_upper); 289 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); 295 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, value); 334 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); 335 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower); 345 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value); 346 WRITE_REG32(h [all...] |
H A D | qls_dump.c | 406 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg | Q81_CTL_PROC_ADDR_READ); 430 WRITE_REG32(ha, Q81_CTL_PROC_DATA, data); 432 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg); 614 WRITE_REG32(ha, Q81_CTL_XG_SERDES_ADDR, \ 820 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ 832 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ 857 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i)); 873 WRITE_REG32(ha, Q81_CTL_XGMAC_ADDR, (reg | Q81_XGMAC_ADDR_R)); 1233 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ 1246 WRITE_REG32(h [all...] |
H A D | qls_isr.c | 363 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, Q81_CTL_HCS_CMD_CLR_RTH_INTR);
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H A D | qls_hw.h | 925 #define WRITE_REG32(ha, reg, val) bus_write_4((ha->pci_reg), reg, val) macro 932 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRE_MASK_VALUE | idx)) 939 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRD_MASK_VALUE | idx))
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/freebsd-10.1-release/sys/dev/qlxgb/ |
H A D | qla_hw.h | 801 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->rds_rsp[i].producer_reg +\ 805 WRITE_REG32(ha, (ha->hw.tx_prod_reg + 0x1b2000), val) 808 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->sds_rsp[i].consumer_reg +\ 813 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F0, 0xFFFFFFFF);\ 815 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F1, 0xFFFFFFFF);\ 822 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x1);\ 829 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x0);\
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H A D | qla_reg.h | 234 #define WRITE_REG32(ha, reg, val) \ macro
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/freebsd-10.1-release/sys/dev/qlxgbe/ |
H A D | ql_inline.h | 66 WRITE_REG32(ha, id_reg, id_val);
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H A D | ql_isr.c | 734 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0); 779 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0); 780 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); 785 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0); 786 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
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H A D | ql_ioctl.c | 115 WRITE_REG32(ha, u.rv->reg, u.rv->val);
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H A D | ql_misc.c | 70 WRITE_REG32(ha, wnd_reg, addr); 87 WRITE_REG32(ha, Q8_WILD_CARD, *val); 1221 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0); 1291 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0);
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H A D | ql_hw.c | 567 WRITE_REG32(ha, (Q8_HOST_MBOX0 + (i << 2)), *h_mbox); 571 WRITE_REG32(ha, Q8_HOST_MBOX_CNTRL, 0x1); 602 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0); 603 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); 1863 WRITE_REG32(ha, Q8_MBOX_INT_ENABLE, BIT_2); 1864 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
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H A D | ql_hw.h | 205 #define WRITE_REG32(ha, reg, val) \ macro 1544 WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val)
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