1227064Sbz/* 2250340Sdavidcs * Copyright (c) 2011-2013 Qlogic Corporation 3227064Sbz * All rights reserved. 4227064Sbz * 5227064Sbz * Redistribution and use in source and binary forms, with or without 6227064Sbz * modification, are permitted provided that the following conditions 7227064Sbz * are met: 8227064Sbz * 9227064Sbz * 1. Redistributions of source code must retain the above copyright 10227064Sbz * notice, this list of conditions and the following disclaimer. 11227064Sbz * 2. Redistributions in binary form must reproduce the above copyright 12227064Sbz * notice, this list of conditions and the following disclaimer in the 13227064Sbz * documentation and/or other materials provided with the distribution. 14227064Sbz * 15227064Sbz * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16227064Sbz * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17227064Sbz * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18227064Sbz * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19227064Sbz * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20227064Sbz * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21227064Sbz * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22227064Sbz * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23227064Sbz * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24227064Sbz * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25227064Sbz * POSSIBILITY OF SUCH DAMAGE. 26227064Sbz * 27227064Sbz * $FreeBSD$ 28227064Sbz */ 29227064Sbz/* 30227064Sbz * File: qla_reg.h 31227064Sbz * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 32227064Sbz */ 33227064Sbz 34227064Sbz#ifndef _QLA_REG_H_ 35227064Sbz#define _QLA_REG_H_ 36227064Sbz 37227064Sbz/* 38227064Sbz * Begin Definitions for QLA82xx Registers 39227064Sbz */ 40227064Sbz 41227064Sbz/* 42227064Sbz * Register offsets for QLA8022 43227064Sbz */ 44227064Sbz 45227064Sbz/****************************** 46227064Sbz * PCIe Registers 47227064Sbz ******************************/ 48227064Sbz#define Q8_CRB_WINDOW_2M 0x130060 49227064Sbz 50227064Sbz#define Q8_INT_VECTOR 0x130100 51227064Sbz#define Q8_INT_MASK 0x130104 52227064Sbz 53227064Sbz#define Q8_INT_TARGET_STATUS_F0 0x130118 54227064Sbz#define Q8_INT_TARGET_MASK_F0 0x130128 55227064Sbz#define Q8_INT_TARGET_STATUS_F1 0x130160 56227064Sbz#define Q8_INT_TARGET_MASK_F1 0x130170 57227064Sbz#define Q8_INT_TARGET_STATUS_F2 0x130164 58227064Sbz#define Q8_INT_TARGET_MASK_F2 0x130174 59227064Sbz#define Q8_INT_TARGET_STATUS_F3 0x130168 60227064Sbz#define Q8_INT_TARGET_MASK_F3 0x130178 61227064Sbz#define Q8_INT_TARGET_STATUS_F4 0x130360 62227064Sbz#define Q8_INT_TARGET_MASK_F4 0x130370 63227064Sbz#define Q8_INT_TARGET_STATUS_F5 0x130364 64227064Sbz#define Q8_INT_TARGET_MASK_F5 0x130374 65227064Sbz#define Q8_INT_TARGET_STATUS_F6 0x130368 66227064Sbz#define Q8_INT_TARGET_MASK_F6 0x130378 67227064Sbz#define Q8_INT_TARGET_STATUS_F7 0x13036C 68227064Sbz#define Q8_INT_TARGET_MASK_F7 0x13037C 69227064Sbz 70227064Sbz#define Q8_SEM2_LOCK 0x13C010 71227064Sbz#define Q8_SEM2_UNLOCK 0x13C014 72227064Sbz#define Q8_SEM3_LOCK 0x13C018 73227064Sbz#define Q8_SEM3_UNLOCK 0x13C01C 74227064Sbz#define Q8_SEM5_LOCK 0x13C028 75227064Sbz#define Q8_SEM5_UNLOCK 0x13C02C 76227064Sbz#define Q8_SEM7_LOCK 0x13C038 77227064Sbz#define Q8_SEM7_UNLOCK 0x13C03C 78227064Sbz 79227064Sbz/* Valid bit for a SEM<N>_LOCK registers */ 80227064Sbz#define SEM_LOCK_BIT 0x00000001 81227064Sbz 82227064Sbz 83227064Sbz#define Q8_ROM_LOCKID 0x1B2100 84227064Sbz 85227064Sbz/******************************* 86227064Sbz * Firmware Interface Registers 87227064Sbz *******************************/ 88227064Sbz#define Q8_FW_VER_MAJOR 0x1B2150 89227064Sbz#define Q8_FW_VER_MINOR 0x1B2154 90227064Sbz#define Q8_FW_VER_SUB 0x1B2158 91227064Sbz#define Q8_FW_VER_BUILD 0x1B2168 92227064Sbz 93227064Sbz#define Q8_CMDPEG_STATE 0x1B2250 94227064Sbz#define Q8_RCVPEG_STATE 0x1B233C 95227064Sbz/* 96227064Sbz * definitions for Q8_CMDPEG_STATE 97227064Sbz */ 98227064Sbz#define CMDPEG_PHAN_INIT_COMPLETE 0xFF01 99227064Sbz 100227064Sbz#define Q8_ROM_STATUS 0x1A0004 101227064Sbz/* 102227064Sbz * definitions for Q8_ROM_STATUS 103227064Sbz * bit definitions for Q8_UNM_ROMUSB_GLB_STATUS 104227064Sbz * 31:3 Reserved; Rest as below 105227064Sbz */ 106227064Sbz#define ROM_STATUS_RDY 0x0004 107227064Sbz#define ROM_STATUS_DONE 0x0002 108227064Sbz#define ROM_STATUS_AUTO_ROM_SHDW 0x0001 109227064Sbz 110227064Sbz#define Q8_ASIC_RESET 0x1A0008 111227064Sbz/* 112227064Sbz * definitions for Q8_ASIC_RESET 113227064Sbz */ 114227064Sbz#define ASIC_RESET_RST_XDMA 0x00800000 /* Reset XDMA */ 115227064Sbz#define ASIC_RESET_PEG_ICACHE 0x00000020 /* Reset PEG_ICACHE */ 116227064Sbz#define ASIC_RESET_PEG_DCACHE 0x00000010 /* Reset PEG_DCACHE */ 117227064Sbz#define ASIC_RESET_PEG_3 0x00000008 /* Reset PEG_3 */ 118227064Sbz#define ASIC_RESET_PEG_2 0x00000004 /* Reset PEG_2 */ 119227064Sbz#define ASIC_RESET_PEG_1 0x00000002 /* Reset PEG_1 */ 120227064Sbz#define ASIC_RESET_PEG_0 0x00000001 /* Reset PEG_0 */ 121227064Sbz 122227064Sbz#define Q8_COLD_BOOT 0x1B21FC 123227064Sbz/* 124227064Sbz * definitions for Q8_COLD_BOOT 125227064Sbz */ 126227064Sbz#define COLD_BOOT_VALUE 0x12345678 127227064Sbz 128227064Sbz 129227064Sbz#define Q8_MIU_TEST_AGT_CTRL 0x180090 130227064Sbz#define Q8_MIU_TEST_AGT_ADDR_LO 0x180094 131227064Sbz#define Q8_MIU_TEST_AGT_ADDR_HI 0x180098 132227064Sbz#define Q8_MIU_TEST_AGT_WRDATA_LO 0x1800A0 133227064Sbz#define Q8_MIU_TEST_AGT_WRDATA_HI 0x1800A4 134227064Sbz#define Q8_MIU_TEST_AGT_RDDATA_LO 0x1800A8 135227064Sbz#define Q8_MIU_TEST_AGT_RDDATA_HI 0x1800AC 136227064Sbz#define Q8_MIU_TEST_AGT_WRDATA_ULO 0x1800B0 137227064Sbz#define Q8_MIU_TEST_AGT_WRDATA_UHI 0x1800B4 138227064Sbz#define Q8_MIU_TEST_AGT_RDDATA_ULO 0x1800B8 139227064Sbz#define Q8_MIU_TEST_AGT_RDDATA_UHI 0x1800BC 140227064Sbz 141227064Sbz#define Q8_PEG_0_RESET 0x160018 142227064Sbz#define Q8_PEG_0_CLR1 0x160008 143227064Sbz#define Q8_PEG_0_CLR2 0x16000C 144227064Sbz#define Q8_PEG_1_CLR1 0x161008 145227064Sbz#define Q8_PEG_1_CLR2 0x16100C 146227064Sbz#define Q8_PEG_2_CLR1 0x162008 147227064Sbz#define Q8_PEG_2_CLR2 0x16200C 148227064Sbz#define Q8_PEG_3_CLR1 0x163008 149227064Sbz#define Q8_PEG_3_CLR2 0x16300C 150227064Sbz#define Q8_PEG_4_CLR1 0x164008 151227064Sbz#define Q8_PEG_4_CLR2 0x16400C 152227064Sbz#define Q8_PEG_D_RESET1 0x1650EC 153227064Sbz#define Q8_PEG_D_RESET2 0x16504C 154227064Sbz#define Q8_PEG_HALT_STATUS1 0x1B20A8 155227064Sbz#define Q8_PEG_HALT_STATUS2 0x1B20AC 156227064Sbz#define Q8_FIRMWARE_HEARTBEAT 0x1B20B0 157227064Sbz#define Q8_PEG_I_RESET 0x16604C 158227064Sbz 159227064Sbz#define Q8_CRB_MAC_BLOCK_START 0x1B21C0 160227064Sbz 161227064Sbz/*************************************************** 162227064Sbz * Flash ROM Access Registers ( Indirect Registers ) 163227064Sbz ***************************************************/ 164227064Sbz 165227064Sbz#define Q8_ROM_INSTR_OPCODE 0x03310004 166227064Sbz/* 167227064Sbz * bit definitions for Q8_ROM_INSTR_OPCODE 168227064Sbz * 31:8 Reserved; Rest Below 169227064Sbz */ 170227064Sbz#define ROM_OPCODE_WR_STATUS_REG 0x01 171227064Sbz#define ROM_OPCODE_PROG_PAGE 0x02 172227064Sbz#define ROM_OPCODE_RD_BYTE 0x03 173227064Sbz#define ROM_OPCODE_WR_DISABLE 0x04 174227064Sbz#define ROM_OPCODE_RD_STATUS_REG 0x05 175227064Sbz#define ROM_OPCODE_WR_ENABLE 0x06 176227064Sbz#define ROM_OPCODE_FAST_RD 0x0B 177227064Sbz#define ROM_OPCODE_REL_DEEP_PWR_DWN 0xAB 178227064Sbz#define ROM_OPCODE_BULK_ERASE 0xC7 179227064Sbz#define ROM_OPCODE_DEEP_PWR_DWN 0xC9 180227064Sbz#define ROM_OPCODE_SECTOR_ERASE 0xD8 181227064Sbz 182227064Sbz#define Q8_ROM_ADDRESS 0x03310008 183227064Sbz/* 184227064Sbz * bit definitions for Q8_ROM_ADDRESS 185227064Sbz * 31:24 Reserved; 186227064Sbz * 23:0 Physical ROM Address in bytes 187227064Sbz */ 188227064Sbz 189227064Sbz#define Q8_ROM_ADDR_BYTE_COUNT 0x03310010 190227064Sbz/* 191227064Sbz * bit definitions for Q8_ROM_ADDR_BYTE_COUNT 192227064Sbz * 31:2 Reserved; 193227064Sbz * 1:0 max address bytes for ROM Interface 194227064Sbz */ 195227064Sbz 196227064Sbz#define Q8_ROM_DUMMY_BYTE_COUNT 0x03310014 197227064Sbz/* 198227064Sbz * bit definitions for Q8_ROM_DUMMY_BYTE_COUNT 199227064Sbz * 31:2 Reserved; 200227064Sbz * 1:0 dummy bytes for ROM Instructions 201227064Sbz */ 202227064Sbz 203227064Sbz#define Q8_ROM_RD_DATA 0x03310018 204250340Sdavidcs#define Q8_ROM_WR_DATA 0x0331000C 205250340Sdavidcs#define Q8_ROM_DIRECT_WINDOW 0x03310030 206250340Sdavidcs#define Q8_ROM_DIRECT_DATA_OFFSET 0x03310000 207227064Sbz 208250340Sdavidcs 209227064Sbz#define Q8_NX_CDRP_CMD_RSP 0x1B2218 210227064Sbz#define Q8_NX_CDRP_ARG1 0x1B221C 211227064Sbz#define Q8_NX_CDRP_ARG2 0x1B2220 212227064Sbz#define Q8_NX_CDRP_ARG3 0x1B2224 213227064Sbz#define Q8_NX_CDRP_SIGNATURE 0x1B2228 214227064Sbz 215227064Sbz#define Q8_LINK_STATE 0x1B2298 216227064Sbz#define Q8_LINK_SPEED_0 0x1B22E8 217227064Sbz/* 218227064Sbz * Macros for reading and writing registers 219227064Sbz */ 220227064Sbz 221227064Sbz#if defined(__i386__) || defined(__amd64__) 222227064Sbz#define Q8_MB() __asm volatile("mfence" ::: "memory") 223227064Sbz#define Q8_WMB() __asm volatile("sfence" ::: "memory") 224227064Sbz#define Q8_RMB() __asm volatile("lfence" ::: "memory") 225227064Sbz#else 226227064Sbz#define Q8_MB() 227227064Sbz#define Q8_WMB() 228227064Sbz#define Q8_RMB() 229227064Sbz#endif 230227064Sbz 231227064Sbz#define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) 232227064Sbz#define READ_OFFSET32(ha, off) READ_REG32(ha, off) 233227064Sbz 234227064Sbz#define WRITE_REG32(ha, reg, val) \ 235227064Sbz {\ 236227064Sbz bus_write_4((ha->pci_reg), reg, val);\ 237227064Sbz bus_read_4((ha->pci_reg), reg);\ 238227064Sbz } 239227064Sbz 240227064Sbz#define WRITE_REG32_MB(ha, reg, val) \ 241227064Sbz {\ 242227064Sbz Q8_WMB();\ 243227064Sbz bus_write_4((ha->pci_reg), reg, val);\ 244227064Sbz } 245227064Sbz 246227064Sbz#define WRITE_OFFSET32(ha, off, val)\ 247227064Sbz {\ 248227064Sbz bus_write_4((ha->pci_reg), off, val);\ 249227064Sbz bus_read_4((ha->pci_reg), off);\ 250227064Sbz } 251227064Sbz 252227064Sbz#endif /* #ifndef _QLA_REG_H_ */ 253