Searched refs:VirtReg (Results 1 - 25 of 25) sorted by relevance

/freebsd-10.1-release/contrib/llvm/lib/CodeGen/
H A DLiveRegMatrix.cpp72 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { argument
73 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
75 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
76 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
80 Matrix[*Units].unify(VirtReg);
86 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { argument
87 unsigned PhysReg = VRM->getPhys(VirtReg.reg);
88 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
90 VRM->clearVirt(VirtReg
99 checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg) argument
117 checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg) argument
130 query(LiveInterval &VirtReg, unsigned RegUnit) argument
138 checkInterference(LiveInterval &VirtReg, unsigned PhysReg) argument
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H A DLiveIntervalUnion.cpp28 void LiveIntervalUnion::unify(LiveInterval &VirtReg) { argument
29 if (VirtReg.empty())
34 LiveInterval::iterator RegPos = VirtReg.begin();
35 LiveInterval::iterator RegEnd = VirtReg.end();
39 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
49 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
51 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
55 void LiveIntervalUnion::extract(LiveInterval &VirtReg) { argument
56 if (VirtReg.empty())
61 LiveInterval::iterator RegPos = VirtReg
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H A DRegAllocBase.cpp87 while (LiveInterval *VirtReg = dequeue()) {
88 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
91 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
92 DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
93 LIS->removeInterval(VirtReg->reg);
104 << MRI->getRegClass(VirtReg->reg)->getName()
105 << ':' << *VirtReg << '\n');
108 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
114 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg);
123 VRM->assignVirt2Phys(VirtReg
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H A DAllocationOrder.cpp29 AllocationOrder::AllocationOrder(unsigned VirtReg, argument
35 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
36 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
H A DRegAllocFast.cpp72 unsigned VirtReg; // Virtual register number. member in struct:__anon2287::RAFast::LiveReg
78 : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {}
81 return TargetRegisterInfo::virtReg2Index(VirtReg);
167 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
172 void killVirtReg(unsigned VirtReg);
174 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
180 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { argument
181 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
183 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const {
184 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
201 getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) argument
256 killVirtReg(unsigned VirtReg) argument
266 spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) argument
499 assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) argument
510 const unsigned VirtReg = LRI->VirtReg; local
582 defineVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument
615 reloadVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument
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H A DRegAllocBasic.cpp104 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
113 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
166 // that interfere with VirtReg. The newly spilled or split live intervals are
168 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, argument
176 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
182 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight)
188 " interferences with " << VirtReg << "\n");
222 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, argument
228 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
231 switch (Matrix->checkInterference(VirtReg, PhysRe
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H A DRegisterCoalescer.h68 CoalescerPair(unsigned VirtReg, unsigned PhysReg, argument
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
H A DRegAllocGreedy.cpp139 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
140 return ExtraRegInfo[VirtReg.reg].Stage;
143 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { argument
145 ExtraRegInfo[VirtReg.reg].Stage = Stage;
266 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
359 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { argument
360 if (VRM->hasPhys(VirtReg)) {
361 Matrix->unassign(LIS->getInterval(VirtReg));
369 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { argument
370 if (!VRM->hasPhys(VirtReg))
456 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
499 canReassign(LiveInterval &VirtReg, unsigned PrevReg) argument
558 canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, bool IsHint, EvictionCost &MaxCost) argument
640 evictInterference(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl<unsigned> &NewVRegs) argument
681 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs, unsigned CostPerUseLimit) argument
1172 tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
1307 tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
1359 tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
1493 tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
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H A DVirtRegMap.cpp81 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) { argument
82 unsigned Hint = MRI->getSimpleHint(VirtReg);
87 return getPhys(VirtReg) == Hint;
90 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) { argument
91 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
240 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); local
241 if (MRI->reg_nodbg_empty(VirtReg))
243 LiveInterval &LI = LIS->getInterval(VirtReg);
248 unsigned PhysReg = VRM->getPhys(VirtReg);
308 unsigned VirtReg local
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H A DAllocationOrder.h34 /// Create a new AllocationOrder for VirtReg.
35 /// @param VirtReg Virtual register to allocate for.
38 AllocationOrder(unsigned VirtReg,
H A DRegAllocBase.h83 /// enqueue - Add VirtReg to the priority queue of unassigned registers.
93 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
H A DLiveDebugVariables.cpp309 /// lookupVirtReg - Find the EC leader for VirtReg or null.
310 UserValue *lookupVirtReg(unsigned VirtReg);
347 void mapVirtReg(unsigned VirtReg, UserValue *EC);
438 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { argument
439 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs");
440 UserValue *&Leader = virtRegToEqClass[VirtReg];
444 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { argument
445 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg))
879 unsigned VirtReg = Loc.getReg(); local
880 if (VRM.isAssignedReg(VirtReg)
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H A DTargetRegisterInfo.cpp264 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, argument
270 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
282 // Check that Phys is a valid hint in VirtReg's register class.
288 // from VirtReg's register class if they aren't in the allocation order. The
H A DInlineSpiller.cpp835 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, argument
838 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
844 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
860 markValueUsed(&VirtReg, ParentVNI);
865 // If the instruction also writes VirtReg.reg, it had better not require the
869 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops);
871 markValueUsed(&VirtReg, ParentVNI);
898 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
H A DMachineBasicBlock.cpp362 unsigned VirtReg = I->getOperand(0).getReg(); local
363 if (!MRI.constrainRegClass(VirtReg, RC))
365 return VirtReg;
369 unsigned VirtReg = MRI.createVirtualRegister(RC); local
370 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
374 return VirtReg;
H A DPHIElimination.cpp197 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
199 static bool isImplicitlyDefined(unsigned VirtReg, argument
201 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(VirtReg),
H A DMachineTraceMetrics.cpp625 DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp)
627 assert(TargetRegisterInfo::isVirtualRegister(VirtReg));
628 MachineRegisterInfo::def_iterator DefI = MRI->def_begin(VirtReg);
/freebsd-10.1-release/contrib/llvm/include/llvm/CodeGen/
H A DLiveRegMatrix.h98 /// VirtReg is live across a call, and PhysReg isn't call-preserved.
102 /// Check for interference before assigning VirtReg to PhysReg.
103 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg).
106 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
108 /// Assign VirtReg to PhysReg.
109 /// This will mark VirtReg's live range as occupied in the LiveRegMatrix and
111 void assign(LiveInterval &VirtReg, unsigned PhysReg);
113 /// Unassign VirtReg from its PhysReg.
114 /// Assuming that VirtReg was previously assigned to a PhysReg, this undoes
116 void unassign(LiveInterval &VirtReg);
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H A DLiveIntervalUnion.h87 void unify(LiveInterval &VirtReg);
90 void extract(LiveInterval &VirtReg);
107 LiveInterval *VirtReg; member in class:llvm::LiveIntervalUnion::Query
108 LiveInterval::iterator VirtRegI; // current position in VirtReg
117 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {}
120 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
126 VirtReg = NULL;
137 if (UserTag == UTag && VirtReg == VReg &&
144 VirtReg = VReg;
150 assert(VirtReg
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H A DVirtRegMap.h129 /// @brief returns true if VirtReg is assigned to its preferred physreg.
130 bool hasPreferredPhys(unsigned VirtReg);
132 /// @brief returns true if VirtReg has a known preferred register.
133 /// This returns false if VirtReg has a preference that is a virtual
135 bool hasKnownPreference(unsigned VirtReg);
147 /// getOriginal - Return the original virtual register that VirtReg descends
151 unsigned getOriginal(unsigned VirtReg) const {
152 unsigned Orig = getPreSplitReg(VirtReg);
153 return Orig ? Orig : VirtReg;
H A DScheduleDAGInstrs.h35 unsigned VirtReg; member in struct:llvm::VReg2SUnit
38 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
41 return TargetRegisterInfo::virtReg2Index(VirtReg);
H A DRegisterPressure.h420 bool hasUntiedDef(unsigned VirtReg) const {
421 return UntiedDefs.count(VirtReg);
/freebsd-10.1-release/contrib/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h130 void getRegAllocationHints(unsigned VirtReg,
H A DARMBaseRegisterInfo.cpp210 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, argument
216 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
227 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
/freebsd-10.1-release/contrib/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h638 /// VirtReg. These registers are effectively moved to the front of the
641 /// The Order argument is the allocation order for VirtReg's register class
649 /// order for VirtReg. There may be target-independent hints.
650 virtual void getRegAllocationHints(unsigned VirtReg,

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