/freebsd-10.1-release/contrib/llvm/utils/TableGen/ |
H A D | AsmWriterInst.cpp | 128 CGI.TheDef->getName() + "'!"); 167 + CGI.TheDef->getName() + "'"); 174 + CGI.TheDef->getName() + "'"); 182 PrintFatalError("Bad operand modifier name in '"+ CGI.TheDef->getName() + "'"); 187 + CGI.TheDef->getName() + "'"); 191 PrintFatalError("Stray '$' in '" + CGI.TheDef->getName() +
|
H A D | CodeGenIntrinsics.h | 27 Record *TheDef; // The actual record defining this intrinsic. member in struct:llvm::CodeGenIntrinsic
|
H A D | InstrInfoEmitter.cpp | 211 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable")) { 225 OperandMap[OpList].push_back(Namespace + "::" + Inst->TheDef->getName()); 370 Record *Inst = (*II)->TheDef; 403 InstrNames.add(Instr->TheDef->getName()); 416 OS << InstrNames.get(Instr->TheDef->getName()) << "U, "; 483 << Inst.TheDef->getValueAsInt("Size") << ",\t0"; 516 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags"); 524 PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName()); 531 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); 537 std::vector<Record*> DefList = Inst.TheDef [all...] |
H A D | CodeGenSchedule.h | 40 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or 41 /// may not be empty. TheDef is null for inferred sequences, and Sequence must 49 Record *TheDef; member in struct:llvm::CodeGenSchedRW 59 : Index(0), TheDef(0), IsRead(false), IsAlias(false), 62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) { 77 : Index(Idx), Name(Name), TheDef(0), IsRead(Read), IsAlias(false), 83 assert((!HasVariants || TheDef) && "Variant write needs record def"); 88 return TheDef || !Sequence.empty();
|
H A D | AsmMatcherEmitter.cpp | 402 /// TheDef - This is the definition of the instruction or InstAlias that this 404 Record *const TheDef; member in struct:__anon3826::MatchableInfo 445 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI), 450 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias), 573 Record *TheDef; member in struct:__anon3826::SubtargetFeatureInfo 578 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {} 582 return "Feature_" + TheDef->getName(); 690 errs() << TheDef [all...] |
H A D | CodeGenInstruction.cpp | 28 CGIOperandList::CGIOperandList(Record *R) : TheDef(R) { 136 PrintFatalError("'" + TheDef->getName() + "' does not have an operand named '$" + 156 PrintFatalError(TheDef->getName() + ": Illegal operand name: '" + Op + "'"); 166 PrintFatalError(TheDef->getName() + ": illegal empty suboperand name in '" +Op +"'"); 176 PrintFatalError(TheDef->getName() + ": Illegal to refer to" 186 PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'"); 194 PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'"); 293 : TheDef(R), Operands(R), InferredFrom(0) { 532 CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
|
H A D | CodeGenSchedule.cpp | 81 if ((*RI)->match((*I)->TheDef->getName())) 82 Elts.insert((*I)->TheDef); 221 Record *SchedDef = (*I)->TheDef; 300 findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence, 353 if (I->TheDef == Def) 361 Record *ReadDef = SchedReads[i].TheDef; 416 SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1; 442 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases " 445 AliasDef = AliasRW.TheDef; [all...] |
H A D | AsmWriterEmitter.cpp | 107 << FirstInst.CGI->TheDef->getName() << ":\n"; 110 << SimilarInsts[i].CGI->TheDef->getName() << ":\n"; 121 FirstInst.CGI->TheDef->getName(), 127 AWI.CGI->TheDef->getName(), 170 InstrsForCase[idx] += Inst->CGI->TheDef->getName(); 177 InstrsForCase.push_back(Inst->CGI->TheDef->getName()); 403 << NumberedInstructions[i]->TheDef->getName() << "\n"; 417 << NumberedInstructions[i]->TheDef->getName() << "\n"; 533 AsmName = Reg.TheDef->getValueAsString("AsmName"); 539 Reg.TheDef [all...] |
H A D | CodeGenInstruction.h | 128 Record *TheDef; // The actual record containing this OperandList. member in class:llvm::CGIOperandList 202 Record *TheDef; // The actual record defining this instruction. member in class:llvm::CodeGenInstruction 282 Record *TheDef; // The actual record defining this InstAlias. member in class:llvm::CodeGenInstAlias
|
H A D | SubtargetEmitter.cpp | 676 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes")) 677 return SchedWrite.TheDef; 684 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) { 685 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); 690 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases " 693 AliasDef = AliasRW.TheDef; 705 || SchedWrite.TheDef == (*WRI)->getValueAsDef("WriteType")) { 719 + SchedWrite.TheDef->getName()); 729 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance")) 730 return SchedRead.TheDef; [all...] |
H A D | CodeGenRegisters.h | 37 Record *const TheDef; member in class:llvm::CodeGenSubRegIndex 111 Record *TheDef; member in struct:llvm::CodeGenRegister 124 // Extract more information from TheDef. This is used to build an object 250 Record *TheDef; member in class:llvm::CodeGenRegisterClass 285 Record *getDef() const { return TheDef; }
|
H A D | CodeGenRegisters.cpp | 34 : TheDef(R), EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) { 44 : TheDef(0), Name(N), Namespace(Nspace), Size(-1), Offset(-1), 57 if (!TheDef) 60 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf"); 63 PrintFatalError(TheDef->getLoc(), 69 PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries"); 73 TheDef->getValueAsListOfDefs("CoveringSubRegIndices"); 76 PrintFatalError(TheDef->getLoc(), 107 : TheDef(R), 118 std::vector<Record*> SRIs = TheDef [all...] |
H A D | RegisterInfoEmitter.cpp | 76 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace"); 324 Record *Reg = Regs[i]->TheDef; 342 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace"); 391 Record *Reg = Regs[i]->TheDef; 447 Record *Reg = Regs[i]->TheDef; 455 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace"); 839 OS << " { " << getQualifiedName(Roots.front()->TheDef); 841 OS << ", " << getQualifiedName(Roots[r]->TheDef); 915 Record *Reg = Regs[i]->TheDef; 1219 << int(AllocatableRegs.count(Reg.TheDef)) << " },\ [all...] |
H A D | FixedLenDecoderEmitter.cpp | 375 BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst"); 383 AllInstructions[Opcode]->TheDef->getValueAsBitsInit("SoftFail"); 395 return AllInstructions[Opcode]->TheDef->getName(); 831 << NumberedInstructions->at(Opc)->TheDef->getName() << "\n"; 1000 getBitsField(*AllInstructions[Opcodes[i]]->TheDef, "Inst")); 1151 AllInstructions[Opc]->TheDef->getValueAsListInit("Predicates"); 1179 AllInstructions[Opc]->TheDef->getValueAsListInit("Predicates"); 1246 AllInstructions[Opc]->TheDef->getValueAsBitsInit("SoftFail"); 1248 BitsInit *InstBits = AllInstructions[Opc]->TheDef->getValueAsBitsInit("Inst"); 1269 StringRef Name = AllInstructions[Opc]->TheDef [all...] |
H A D | PseudoLoweringEmitter.cpp | 211 << Source.TheDef->getName() << ": {\n" 215 << Dest.TheDef->getName() << ");\n";
|
H A D | CodeGenTarget.cpp | 297 return Rec1->TheDef->getName() < Rec2->TheDef->getName(); 426 TheDef = R;
|
H A D | CodeGenDAGPatterns.h | 734 if (Intrinsics[i].TheDef == R) return Intrinsics[i]; 736 if (TgtIntrinsics[i].TheDef == R) return TgtIntrinsics[i]; 750 if (Intrinsics[i].TheDef == R) return i; 752 if (TgtIntrinsics[i].TheDef == R) return i + Intrinsics.size();
|
H A D | CodeEmitterGen.cpp | 262 Record *R = CGI->TheDef;
|
H A D | CodeGenMapTable.cpp | 375 Record *CurInstr = NumberedInstructions[i]->TheDef;
|
H A D | CodeGenDAGPatterns.cpp | 2681 assert(!DAGInsts.count(CGI.TheDef) && "Instruction already parsed!"); 2684 TreePattern *I = new TreePattern(CGI.TheDef, Pat, true, *this); 3006 const TreePattern *Pattern = getInstruction(InstInfo.TheDef).getPattern(); 3014 Errors += InferFromPattern(InstInfo, PatInfo, InstInfo.TheDef); 3064 PrintError(InstInfo.TheDef->getLoc(), 3067 PrintError(InstInfo.TheDef->getLoc(), 3070 PrintError(InstInfo.TheDef->getLoc(), 3133 InstInfo.InferredFrom != InstInfo.TheDef &&
|
H A D | DAGISelMatcherEmitter.cpp | 453 OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n"; 458 OS << getQualifiedName(Reg->TheDef) << ",\n";
|
H A D | IntrinsicEmitter.cpp | 747 PrintFatalError("Intrinsic '" + Ints[i].TheDef->getName() +
|
H A D | X86RecognizableInstr.cpp | 221 Rec = insn.TheDef; 297 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
|
H A D | DAGISelMatcherGen.cpp | 852 AddMatcher(new EmitNodeMatcher(II.Namespace+"::"+II.TheDef->getName(),
|