1193323Sed//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This tablegen backend is responsible for emitting a description of a target 11193323Sed// register file for a code generator. It uses instances of the Register, 12193323Sed// RegisterAliases, and RegisterClass classes to gather this information. 13193323Sed// 14193323Sed//===----------------------------------------------------------------------===// 15193323Sed 16239462Sdim#include "CodeGenRegisters.h" 17193323Sed#include "CodeGenTarget.h" 18234353Sdim#include "SequenceToOffsetTable.h" 19226633Sdim#include "llvm/ADT/BitVector.h" 20239462Sdim#include "llvm/ADT/STLExtras.h" 21193323Sed#include "llvm/ADT/StringExtras.h" 22234982Sdim#include "llvm/ADT/Twine.h" 23224145Sdim#include "llvm/Support/Format.h" 24239462Sdim#include "llvm/TableGen/Error.h" 25239462Sdim#include "llvm/TableGen/Record.h" 26239462Sdim#include "llvm/TableGen/TableGenBackend.h" 27195340Sed#include <algorithm> 28193323Sed#include <set> 29239462Sdim#include <vector> 30193323Sedusing namespace llvm; 31193323Sed 32239462Sdimnamespace { 33239462Sdimclass RegisterInfoEmitter { 34239462Sdim RecordKeeper &Records; 35239462Sdimpublic: 36239462Sdim RegisterInfoEmitter(RecordKeeper &R) : Records(R) {} 37239462Sdim 38239462Sdim // runEnums - Print out enum values for all of the registers. 39239462Sdim void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 40239462Sdim 41239462Sdim // runMCDesc - Print out MC register descriptions. 42239462Sdim void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 43239462Sdim 44239462Sdim // runTargetHeader - Emit a header fragment for the register info emitter. 45239462Sdim void runTargetHeader(raw_ostream &o, CodeGenTarget &Target, 46239462Sdim CodeGenRegBank &Bank); 47239462Sdim 48239462Sdim // runTargetDesc - Output the target register and register file descriptions. 49239462Sdim void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, 50239462Sdim CodeGenRegBank &Bank); 51239462Sdim 52239462Sdim // run - Output the register file description. 53239462Sdim void run(raw_ostream &o); 54239462Sdim 55239462Sdimprivate: 56239462Sdim void EmitRegMapping(raw_ostream &o, 57239462Sdim const std::vector<CodeGenRegister*> &Regs, bool isCtor); 58239462Sdim void EmitRegMappingTables(raw_ostream &o, 59239462Sdim const std::vector<CodeGenRegister*> &Regs, 60239462Sdim bool isCtor); 61239462Sdim void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 62239462Sdim const std::string &ClassName); 63243830Sdim void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, 64243830Sdim const std::string &ClassName); 65239462Sdim}; 66239462Sdim} // End anonymous namespace 67239462Sdim 68193323Sed// runEnums - Print out enum values for all of the registers. 69234982Sdimvoid RegisterInfoEmitter::runEnums(raw_ostream &OS, 70234982Sdim CodeGenTarget &Target, CodeGenRegBank &Bank) { 71224145Sdim const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters(); 72193323Sed 73234982Sdim // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 74234353Sdim assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 75234353Sdim 76224145Sdim std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace"); 77193323Sed 78239462Sdim emitSourceFileHeader("Target Register Enum Values", OS); 79224145Sdim 80224145Sdim OS << "\n#ifdef GET_REGINFO_ENUM\n"; 81224145Sdim OS << "#undef GET_REGINFO_ENUM\n"; 82224145Sdim 83193323Sed OS << "namespace llvm {\n\n"; 84193323Sed 85226633Sdim OS << "class MCRegisterClass;\n" 86234353Sdim << "extern const MCRegisterClass " << Namespace 87234353Sdim << "MCRegisterClasses[];\n\n"; 88226633Sdim 89193323Sed if (!Namespace.empty()) 90193323Sed OS << "namespace " << Namespace << " {\n"; 91208599Srdivacky OS << "enum {\n NoRegister,\n"; 92193323Sed 93193323Sed for (unsigned i = 0, e = Registers.size(); i != e; ++i) 94224145Sdim OS << " " << Registers[i]->getName() << " = " << 95224145Sdim Registers[i]->EnumValue << ",\n"; 96224145Sdim assert(Registers.size() == Registers[Registers.size()-1]->EnumValue && 97221345Sdim "Register enum value mismatch!"); 98208599Srdivacky OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 99208599Srdivacky OS << "};\n"; 100193323Sed if (!Namespace.empty()) 101193323Sed OS << "}\n"; 102208599Srdivacky 103226633Sdim ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses(); 104224145Sdim if (!RegisterClasses.empty()) { 105234353Sdim 106234353Sdim // RegisterClass enums are stored as uint16_t in the tables. 107234353Sdim assert(RegisterClasses.size() <= 0xffff && 108234353Sdim "Too many register classes to fit in tables"); 109234353Sdim 110224145Sdim OS << "\n// Register classes\n"; 111208599Srdivacky if (!Namespace.empty()) 112208599Srdivacky OS << "namespace " << Namespace << " {\n"; 113224145Sdim OS << "enum {\n"; 114224145Sdim for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 115224145Sdim if (i) OS << ",\n"; 116226633Sdim OS << " " << RegisterClasses[i]->getName() << "RegClassID"; 117224145Sdim OS << " = " << i; 118224145Sdim } 119224145Sdim OS << "\n };\n"; 120224145Sdim if (!Namespace.empty()) 121224145Sdim OS << "}\n"; 122224145Sdim } 123224145Sdim 124263508Sdim const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices(); 125224145Sdim // If the only definition is the default NoRegAltName, we don't need to 126224145Sdim // emit anything. 127224145Sdim if (RegAltNameIndices.size() > 1) { 128224145Sdim OS << "\n// Register alternate name indices\n"; 129224145Sdim if (!Namespace.empty()) 130224145Sdim OS << "namespace " << Namespace << " {\n"; 131224145Sdim OS << "enum {\n"; 132224145Sdim for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 133224145Sdim OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 134224145Sdim OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 135208599Srdivacky OS << "};\n"; 136208599Srdivacky if (!Namespace.empty()) 137208599Srdivacky OS << "}\n"; 138208599Srdivacky } 139224145Sdim 140234353Sdim ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices(); 141234353Sdim if (!SubRegIndices.empty()) { 142234353Sdim OS << "\n// Subregister indices\n"; 143234353Sdim std::string Namespace = 144234353Sdim SubRegIndices[0]->getNamespace(); 145234353Sdim if (!Namespace.empty()) 146234353Sdim OS << "namespace " << Namespace << " {\n"; 147234353Sdim OS << "enum {\n NoSubRegister,\n"; 148239462Sdim for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) 149234353Sdim OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; 150239462Sdim OS << " NUM_TARGET_SUBREGS\n};\n"; 151234353Sdim if (!Namespace.empty()) 152234353Sdim OS << "}\n"; 153234353Sdim } 154224145Sdim 155193323Sed OS << "} // End llvm namespace \n"; 156224145Sdim OS << "#endif // GET_REGINFO_ENUM\n\n"; 157193323Sed} 158193323Sed 159234353Sdimvoid RegisterInfoEmitter:: 160234353SdimEmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 161234353Sdim const std::string &ClassName) { 162234353Sdim unsigned NumRCs = RegBank.getRegClasses().size(); 163234353Sdim unsigned NumSets = RegBank.getNumRegPressureSets(); 164234353Sdim 165234353Sdim OS << "/// Get the weight in units of pressure for this register class.\n" 166234353Sdim << "const RegClassWeight &" << ClassName << "::\n" 167234353Sdim << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 168234353Sdim << " static const RegClassWeight RCWeightTable[] = {\n"; 169234353Sdim for (unsigned i = 0, e = NumRCs; i != e; ++i) { 170234353Sdim const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i]; 171234353Sdim const CodeGenRegister::Set &Regs = RC.getMembers(); 172234353Sdim if (Regs.empty()) 173234353Sdim OS << " {0, 0"; 174234353Sdim else { 175234353Sdim std::vector<unsigned> RegUnits; 176234353Sdim RC.buildRegUnitSet(RegUnits); 177234353Sdim OS << " {" << (*Regs.begin())->getWeight(RegBank) 178234353Sdim << ", " << RegBank.getRegUnitSetWeight(RegUnits); 179234353Sdim } 180234353Sdim OS << "}, \t// " << RC.getName() << "\n"; 181234353Sdim } 182234353Sdim OS << " {0, 0} };\n" 183234353Sdim << " return RCWeightTable[RC->getID()];\n" 184234353Sdim << "}\n\n"; 185234353Sdim 186249423Sdim // Reasonable targets (not ARMv7) have unit weight for all units, so don't 187249423Sdim // bother generating a table. 188249423Sdim bool RegUnitsHaveUnitWeight = true; 189249423Sdim for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 190249423Sdim UnitIdx < UnitEnd; ++UnitIdx) { 191249423Sdim if (RegBank.getRegUnit(UnitIdx).Weight > 1) 192249423Sdim RegUnitsHaveUnitWeight = false; 193249423Sdim } 194249423Sdim OS << "/// Get the weight in units of pressure for this register unit.\n" 195249423Sdim << "unsigned " << ClassName << "::\n" 196249423Sdim << "getRegUnitWeight(unsigned RegUnit) const {\n" 197249423Sdim << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 198249423Sdim << " && \"invalid register unit\");\n"; 199249423Sdim if (!RegUnitsHaveUnitWeight) { 200249423Sdim OS << " static const uint8_t RUWeightTable[] = {\n "; 201249423Sdim for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 202249423Sdim UnitIdx < UnitEnd; ++UnitIdx) { 203249423Sdim const RegUnit &RU = RegBank.getRegUnit(UnitIdx); 204249423Sdim assert(RU.Weight < 256 && "RegUnit too heavy"); 205249423Sdim OS << RU.Weight << ", "; 206249423Sdim } 207249423Sdim OS << "0 };\n" 208249423Sdim << " return RUWeightTable[RegUnit];\n"; 209249423Sdim } 210249423Sdim else { 211249423Sdim OS << " // All register units have unit weight.\n" 212249423Sdim << " return 1;\n"; 213249423Sdim } 214249423Sdim OS << "}\n\n"; 215249423Sdim 216234353Sdim OS << "\n" 217234353Sdim << "// Get the number of dimensions of register pressure.\n" 218234353Sdim << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n" 219234353Sdim << " return " << NumSets << ";\n}\n\n"; 220234353Sdim 221239462Sdim OS << "// Get the name of this register unit pressure set.\n" 222239462Sdim << "const char *" << ClassName << "::\n" 223239462Sdim << "getRegPressureSetName(unsigned Idx) const {\n" 224239462Sdim << " static const char *PressureNameTable[] = {\n"; 225239462Sdim for (unsigned i = 0; i < NumSets; ++i ) { 226263508Sdim OS << " \"" << RegBank.getRegSetAt(i).Name << "\",\n"; 227239462Sdim } 228239462Sdim OS << " 0 };\n" 229239462Sdim << " return PressureNameTable[Idx];\n" 230239462Sdim << "}\n\n"; 231239462Sdim 232234353Sdim OS << "// Get the register unit pressure limit for this dimension.\n" 233234353Sdim << "// This limit must be adjusted dynamically for reserved registers.\n" 234234353Sdim << "unsigned " << ClassName << "::\n" 235234353Sdim << "getRegPressureSetLimit(unsigned Idx) const {\n" 236234353Sdim << " static const unsigned PressureLimitTable[] = {\n"; 237234353Sdim for (unsigned i = 0; i < NumSets; ++i ) { 238263508Sdim const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 239263508Sdim OS << " " << RegUnits.Weight << ", \t// " << i << ": " 240263508Sdim << RegUnits.Name << "\n"; 241234353Sdim } 242234353Sdim OS << " 0 };\n" 243234353Sdim << " return PressureLimitTable[Idx];\n" 244234353Sdim << "}\n\n"; 245234353Sdim 246249423Sdim // This table may be larger than NumRCs if some register units needed a list 247249423Sdim // of unit sets that did not correspond to a register class. 248249423Sdim unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists(); 249249423Sdim OS << "/// Table of pressure sets per register class or unit.\n" 250249423Sdim << "static const int RCSetsTable[] = {\n "; 251249423Sdim std::vector<unsigned> RCSetStarts(NumRCUnitSets); 252249423Sdim for (unsigned i = 0, StartIdx = 0, e = NumRCUnitSets; i != e; ++i) { 253234353Sdim RCSetStarts[i] = StartIdx; 254234353Sdim ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); 255263508Sdim std::vector<unsigned> PSets; 256263508Sdim PSets.reserve(PSetIDs.size()); 257234353Sdim for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(), 258234353Sdim PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { 259263508Sdim PSets.push_back(RegBank.getRegPressureSet(*PSetI).Order); 260263508Sdim } 261263508Sdim std::sort(PSets.begin(), PSets.end()); 262263508Sdim for (unsigned j = 0, e = PSets.size(); j < e; ++j) { 263263508Sdim OS << PSets[j] << ", "; 264234353Sdim ++StartIdx; 265234353Sdim } 266249423Sdim OS << "-1, \t// #" << RCSetStarts[i] << " "; 267249423Sdim if (i < NumRCs) 268249423Sdim OS << RegBank.getRegClasses()[i]->getName(); 269249423Sdim else { 270249423Sdim OS << "inferred"; 271249423Sdim for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(), 272249423Sdim PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { 273263508Sdim OS << "~" << RegBank.getRegSetAt(*PSetI).Name; 274249423Sdim } 275249423Sdim } 276249423Sdim OS << "\n "; 277234353Sdim ++StartIdx; 278234353Sdim } 279249423Sdim OS << "-1 };\n\n"; 280249423Sdim 281249423Sdim OS << "/// Get the dimensions of register pressure impacted by this " 282249423Sdim << "register class.\n" 283249423Sdim << "/// Returns a -1 terminated array of pressure set IDs\n" 284249423Sdim << "const int* " << ClassName << "::\n" 285249423Sdim << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; 286234353Sdim OS << " static const unsigned RCSetStartTable[] = {\n "; 287234353Sdim for (unsigned i = 0, e = NumRCs; i != e; ++i) { 288234353Sdim OS << RCSetStarts[i] << ","; 289234353Sdim } 290234353Sdim OS << "0 };\n" 291234353Sdim << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n" 292234353Sdim << " return &RCSetsTable[SetListStart];\n" 293234353Sdim << "}\n\n"; 294249423Sdim 295249423Sdim OS << "/// Get the dimensions of register pressure impacted by this " 296249423Sdim << "register unit.\n" 297249423Sdim << "/// Returns a -1 terminated array of pressure set IDs\n" 298249423Sdim << "const int* " << ClassName << "::\n" 299249423Sdim << "getRegUnitPressureSets(unsigned RegUnit) const {\n" 300249423Sdim << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 301249423Sdim << " && \"invalid register unit\");\n"; 302249423Sdim OS << " static const unsigned RUSetStartTable[] = {\n "; 303249423Sdim for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 304249423Sdim UnitIdx < UnitEnd; ++UnitIdx) { 305249423Sdim OS << RCSetStarts[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx] << ","; 306249423Sdim } 307249423Sdim OS << "0 };\n" 308249423Sdim << " unsigned SetListStart = RUSetStartTable[RegUnit];\n" 309249423Sdim << " return &RCSetsTable[SetListStart];\n" 310249423Sdim << "}\n\n"; 311234353Sdim} 312234353Sdim 313226633Sdimvoid 314234353SdimRegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS, 315234353Sdim const std::vector<CodeGenRegister*> &Regs, 316234353Sdim bool isCtor) { 317226633Sdim // Collect all information about dwarf register numbers 318263508Sdim typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy; 319226633Sdim DwarfRegNumsMapTy DwarfRegNums; 320226633Sdim 321226633Sdim // First, just pull all provided information to the map 322226633Sdim unsigned maxLength = 0; 323226633Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 324226633Sdim Record *Reg = Regs[i]->TheDef; 325226633Sdim std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 326226633Sdim maxLength = std::max((size_t)maxLength, RegNums.size()); 327226633Sdim if (DwarfRegNums.count(Reg)) 328234982Sdim PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 329234982Sdim getQualifiedName(Reg) + "specified multiple times"); 330226633Sdim DwarfRegNums[Reg] = RegNums; 331226633Sdim } 332226633Sdim 333226633Sdim if (!maxLength) 334226633Sdim return; 335226633Sdim 336226633Sdim // Now we know maximal length of number list. Append -1's, where needed 337226633Sdim for (DwarfRegNumsMapTy::iterator 338226633Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) 339226633Sdim for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 340226633Sdim I->second.push_back(-1); 341226633Sdim 342234353Sdim std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace"); 343234353Sdim 344234353Sdim OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; 345234353Sdim 346226633Sdim // Emit reverse information about the dwarf register numbers. 347226633Sdim for (unsigned j = 0; j < 2; ++j) { 348234353Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 349234353Sdim OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 350234353Sdim OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 351234353Sdim OS << i << "Dwarf2L[]"; 352234353Sdim 353234353Sdim if (!isCtor) { 354234353Sdim OS << " = {\n"; 355234353Sdim 356234353Sdim // Store the mapping sorted by the LLVM reg num so lookup can be done 357234353Sdim // with a binary search. 358234353Sdim std::map<uint64_t, Record*> Dwarf2LMap; 359234353Sdim for (DwarfRegNumsMapTy::iterator 360234353Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 361234353Sdim int DwarfRegNo = I->second[i]; 362234353Sdim if (DwarfRegNo < 0) 363234353Sdim continue; 364234353Sdim Dwarf2LMap[DwarfRegNo] = I->first; 365234353Sdim } 366234353Sdim 367234353Sdim for (std::map<uint64_t, Record*>::iterator 368234353Sdim I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I) 369234353Sdim OS << " { " << I->first << "U, " << getQualifiedName(I->second) 370234353Sdim << " },\n"; 371234353Sdim 372234353Sdim OS << "};\n"; 373234353Sdim } else { 374234353Sdim OS << ";\n"; 375234353Sdim } 376234353Sdim 377234353Sdim // We have to store the size in a const global, it's used in multiple 378234353Sdim // places. 379234353Sdim OS << "extern const unsigned " << Namespace 380234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize"; 381234353Sdim if (!isCtor) 382234353Sdim OS << " = sizeof(" << Namespace 383234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 384234353Sdim << "Dwarf2L)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n"; 385234353Sdim else 386234353Sdim OS << ";\n\n"; 387234353Sdim } 388234353Sdim } 389234353Sdim 390234353Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 391234353Sdim Record *Reg = Regs[i]->TheDef; 392234353Sdim const RecordVal *V = Reg->getValue("DwarfAlias"); 393234353Sdim if (!V || !V->getValue()) 394234353Sdim continue; 395234353Sdim 396243830Sdim DefInit *DI = cast<DefInit>(V->getValue()); 397234353Sdim Record *Alias = DI->getDef(); 398234353Sdim DwarfRegNums[Reg] = DwarfRegNums[Alias]; 399234353Sdim } 400234353Sdim 401234353Sdim // Emit information about the dwarf register numbers. 402234353Sdim for (unsigned j = 0; j < 2; ++j) { 403234353Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 404234353Sdim OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 405234353Sdim OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 406234353Sdim OS << i << "L2Dwarf[]"; 407234353Sdim if (!isCtor) { 408234353Sdim OS << " = {\n"; 409234353Sdim // Store the mapping sorted by the Dwarf reg num so lookup can be done 410234353Sdim // with a binary search. 411234353Sdim for (DwarfRegNumsMapTy::iterator 412234353Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 413234353Sdim int RegNo = I->second[i]; 414234353Sdim if (RegNo == -1) // -1 is the default value, don't emit a mapping. 415234353Sdim continue; 416234353Sdim 417234353Sdim OS << " { " << getQualifiedName(I->first) << ", " << RegNo 418234353Sdim << "U },\n"; 419234353Sdim } 420234353Sdim OS << "};\n"; 421234353Sdim } else { 422234353Sdim OS << ";\n"; 423234353Sdim } 424234353Sdim 425234353Sdim // We have to store the size in a const global, it's used in multiple 426234353Sdim // places. 427234353Sdim OS << "extern const unsigned " << Namespace 428234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; 429234353Sdim if (!isCtor) 430234353Sdim OS << " = sizeof(" << Namespace 431234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 432234353Sdim << "L2Dwarf)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n"; 433234353Sdim else 434234353Sdim OS << ";\n\n"; 435234353Sdim } 436234353Sdim } 437234353Sdim} 438234353Sdim 439234353Sdimvoid 440234353SdimRegisterInfoEmitter::EmitRegMapping(raw_ostream &OS, 441234353Sdim const std::vector<CodeGenRegister*> &Regs, 442234353Sdim bool isCtor) { 443234353Sdim // Emit the initializer so the tables from EmitRegMappingTables get wired up 444234353Sdim // to the MCRegisterInfo object. 445234353Sdim unsigned maxLength = 0; 446234353Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 447234353Sdim Record *Reg = Regs[i]->TheDef; 448234353Sdim maxLength = std::max((size_t)maxLength, 449234353Sdim Reg->getValueAsListOfInts("DwarfNumbers").size()); 450234353Sdim } 451234353Sdim 452234353Sdim if (!maxLength) 453234353Sdim return; 454234353Sdim 455234353Sdim std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace"); 456234353Sdim 457234353Sdim // Emit reverse information about the dwarf register numbers. 458234353Sdim for (unsigned j = 0; j < 2; ++j) { 459226633Sdim OS << " switch ("; 460226633Sdim if (j == 0) 461226633Sdim OS << "DwarfFlavour"; 462226633Sdim else 463226633Sdim OS << "EHFlavour"; 464226633Sdim OS << ") {\n" 465226633Sdim << " default:\n" 466234353Sdim << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 467226633Sdim 468226633Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 469226633Sdim OS << " case " << i << ":\n"; 470234353Sdim OS << " "; 471234353Sdim if (!isCtor) 472234353Sdim OS << "RI->"; 473234353Sdim std::string Tmp; 474234353Sdim raw_string_ostream(Tmp) << Namespace 475234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 476234353Sdim << "Dwarf2L"; 477234353Sdim OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; 478234353Sdim if (j == 0) 479226633Sdim OS << "false"; 480226633Sdim else 481226633Sdim OS << "true"; 482234353Sdim OS << ");\n"; 483226633Sdim OS << " break;\n"; 484226633Sdim } 485226633Sdim OS << " }\n"; 486226633Sdim } 487226633Sdim 488226633Sdim // Emit information about the dwarf register numbers. 489226633Sdim for (unsigned j = 0; j < 2; ++j) { 490226633Sdim OS << " switch ("; 491226633Sdim if (j == 0) 492226633Sdim OS << "DwarfFlavour"; 493226633Sdim else 494226633Sdim OS << "EHFlavour"; 495226633Sdim OS << ") {\n" 496226633Sdim << " default:\n" 497234353Sdim << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 498226633Sdim 499226633Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 500226633Sdim OS << " case " << i << ":\n"; 501234353Sdim OS << " "; 502234353Sdim if (!isCtor) 503234353Sdim OS << "RI->"; 504234353Sdim std::string Tmp; 505234353Sdim raw_string_ostream(Tmp) << Namespace 506234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 507234353Sdim << "L2Dwarf"; 508234353Sdim OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; 509234353Sdim if (j == 0) 510226633Sdim OS << "false"; 511226633Sdim else 512226633Sdim OS << "true"; 513234353Sdim OS << ");\n"; 514226633Sdim OS << " break;\n"; 515226633Sdim } 516226633Sdim OS << " }\n"; 517226633Sdim } 518226633Sdim} 519226633Sdim 520226633Sdim// Print a BitVector as a sequence of hex numbers using a little-endian mapping. 521226633Sdim// Width is the number of bits per hex number. 522226633Sdimstatic void printBitVectorAsHex(raw_ostream &OS, 523226633Sdim const BitVector &Bits, 524226633Sdim unsigned Width) { 525226633Sdim assert(Width <= 32 && "Width too large"); 526226633Sdim unsigned Digits = (Width + 3) / 4; 527226633Sdim for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 528226633Sdim unsigned Value = 0; 529226633Sdim for (unsigned j = 0; j != Width && i + j != e; ++j) 530226633Sdim Value |= Bits.test(i + j) << j; 531226633Sdim OS << format("0x%0*x, ", Digits, Value); 532226633Sdim } 533226633Sdim} 534226633Sdim 535226633Sdim// Helper to emit a set of bits into a constant byte array. 536226633Sdimclass BitVectorEmitter { 537226633Sdim BitVector Values; 538226633Sdimpublic: 539226633Sdim void add(unsigned v) { 540226633Sdim if (v >= Values.size()) 541226633Sdim Values.resize(((v/8)+1)*8); // Round up to the next byte. 542226633Sdim Values[v] = true; 543226633Sdim } 544226633Sdim 545226633Sdim void print(raw_ostream &OS) { 546226633Sdim printBitVectorAsHex(OS, Values, 8); 547226633Sdim } 548226633Sdim}; 549226633Sdim 550234353Sdimstatic void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 551234353Sdim OS << getEnumName(VT); 552234353Sdim} 553234353Sdim 554239462Sdimstatic void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { 555239462Sdim OS << Idx->EnumValue; 556239462Sdim} 557239462Sdim 558239462Sdim// Differentially encoded register and regunit lists allow for better 559239462Sdim// compression on regular register banks. The sequence is computed from the 560239462Sdim// differential list as: 561224145Sdim// 562239462Sdim// out[0] = InitVal; 563239462Sdim// out[n+1] = out[n] + diff[n]; // n = 0, 1, ... 564239462Sdim// 565239462Sdim// The initial value depends on the specific list. The list is terminated by a 566239462Sdim// 0 differential which means we can't encode repeated elements. 567239462Sdim 568239462Sdimtypedef SmallVector<uint16_t, 4> DiffVec; 569239462Sdim 570239462Sdim// Differentially encode a sequence of numbers into V. The starting value and 571239462Sdim// terminating 0 are not added to V, so it will have the same size as List. 572239462Sdimstatic 573239462SdimDiffVec &diffEncode(DiffVec &V, unsigned InitVal, ArrayRef<unsigned> List) { 574239462Sdim assert(V.empty() && "Clear DiffVec before diffEncode."); 575239462Sdim uint16_t Val = uint16_t(InitVal); 576239462Sdim for (unsigned i = 0; i != List.size(); ++i) { 577239462Sdim uint16_t Cur = List[i]; 578239462Sdim V.push_back(Cur - Val); 579239462Sdim Val = Cur; 580239462Sdim } 581239462Sdim return V; 582239462Sdim} 583239462Sdim 584239462Sdimtemplate<typename Iter> 585239462Sdimstatic 586239462SdimDiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) { 587239462Sdim assert(V.empty() && "Clear DiffVec before diffEncode."); 588239462Sdim uint16_t Val = uint16_t(InitVal); 589239462Sdim for (Iter I = Begin; I != End; ++I) { 590239462Sdim uint16_t Cur = (*I)->EnumValue; 591239462Sdim V.push_back(Cur - Val); 592239462Sdim Val = Cur; 593239462Sdim } 594239462Sdim return V; 595239462Sdim} 596239462Sdim 597239462Sdimstatic void printDiff16(raw_ostream &OS, uint16_t Val) { 598239462Sdim OS << Val; 599239462Sdim} 600239462Sdim 601243830Sdim// Try to combine Idx's compose map into Vec if it is compatible. 602243830Sdim// Return false if it's not possible. 603243830Sdimstatic bool combine(const CodeGenSubRegIndex *Idx, 604243830Sdim SmallVectorImpl<CodeGenSubRegIndex*> &Vec) { 605243830Sdim const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); 606243830Sdim for (CodeGenSubRegIndex::CompMap::const_iterator 607243830Sdim I = Map.begin(), E = Map.end(); I != E; ++I) { 608243830Sdim CodeGenSubRegIndex *&Entry = Vec[I->first->EnumValue - 1]; 609243830Sdim if (Entry && Entry != I->second) 610243830Sdim return false; 611243830Sdim } 612243830Sdim 613243830Sdim // All entries are compatible. Make it so. 614243830Sdim for (CodeGenSubRegIndex::CompMap::const_iterator 615243830Sdim I = Map.begin(), E = Map.end(); I != E; ++I) 616243830Sdim Vec[I->first->EnumValue - 1] = I->second; 617243830Sdim return true; 618243830Sdim} 619243830Sdim 620243830Sdimstatic const char *getMinimalTypeForRange(uint64_t Range) { 621243830Sdim assert(Range < 0xFFFFFFFFULL && "Enum too large"); 622243830Sdim if (Range > 0xFFFF) 623243830Sdim return "uint32_t"; 624243830Sdim if (Range > 0xFF) 625243830Sdim return "uint16_t"; 626243830Sdim return "uint8_t"; 627243830Sdim} 628243830Sdim 629243830Sdimvoid 630243830SdimRegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, 631243830Sdim CodeGenRegBank &RegBank, 632243830Sdim const std::string &ClName) { 633243830Sdim ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); 634243830Sdim OS << "unsigned " << ClName 635243830Sdim << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n"; 636243830Sdim 637243830Sdim // Many sub-register indexes are composition-compatible, meaning that 638243830Sdim // 639243830Sdim // compose(IdxA, IdxB) == compose(IdxA', IdxB) 640243830Sdim // 641243830Sdim // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. 642243830Sdim // The illegal entries can be use as wildcards to compress the table further. 643243830Sdim 644243830Sdim // Map each Sub-register index to a compatible table row. 645243830Sdim SmallVector<unsigned, 4> RowMap; 646243830Sdim SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows; 647243830Sdim 648243830Sdim for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 649243830Sdim unsigned Found = ~0u; 650243830Sdim for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 651243830Sdim if (combine(SubRegIndices[i], Rows[r])) { 652243830Sdim Found = r; 653243830Sdim break; 654243830Sdim } 655243830Sdim } 656243830Sdim if (Found == ~0u) { 657243830Sdim Found = Rows.size(); 658243830Sdim Rows.resize(Found + 1); 659243830Sdim Rows.back().resize(SubRegIndices.size()); 660243830Sdim combine(SubRegIndices[i], Rows.back()); 661243830Sdim } 662243830Sdim RowMap.push_back(Found); 663243830Sdim } 664243830Sdim 665243830Sdim // Output the row map if there is multiple rows. 666243830Sdim if (Rows.size() > 1) { 667243830Sdim OS << " static const " << getMinimalTypeForRange(Rows.size()) 668243830Sdim << " RowMap[" << SubRegIndices.size() << "] = {\n "; 669243830Sdim for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) 670243830Sdim OS << RowMap[i] << ", "; 671243830Sdim OS << "\n };\n"; 672243830Sdim } 673243830Sdim 674243830Sdim // Output the rows. 675243830Sdim OS << " static const " << getMinimalTypeForRange(SubRegIndices.size()+1) 676243830Sdim << " Rows[" << Rows.size() << "][" << SubRegIndices.size() << "] = {\n"; 677243830Sdim for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 678243830Sdim OS << " { "; 679243830Sdim for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) 680243830Sdim if (Rows[r][i]) 681243830Sdim OS << Rows[r][i]->EnumValue << ", "; 682243830Sdim else 683243830Sdim OS << "0, "; 684243830Sdim OS << "},\n"; 685243830Sdim } 686243830Sdim OS << " };\n\n"; 687243830Sdim 688243830Sdim OS << " --IdxA; assert(IdxA < " << SubRegIndices.size() << ");\n" 689243830Sdim << " --IdxB; assert(IdxB < " << SubRegIndices.size() << ");\n"; 690243830Sdim if (Rows.size() > 1) 691243830Sdim OS << " return Rows[RowMap[IdxA]][IdxB];\n"; 692243830Sdim else 693243830Sdim OS << " return Rows[0][IdxB];\n"; 694243830Sdim OS << "}\n\n"; 695243830Sdim} 696243830Sdim 697239462Sdim// 698224145Sdim// runMCDesc - Print out MC register descriptions. 699224145Sdim// 700224145Sdimvoid 701224145SdimRegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 702224145Sdim CodeGenRegBank &RegBank) { 703239462Sdim emitSourceFileHeader("MC Register Information", OS); 704224145Sdim 705224145Sdim OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 706224145Sdim OS << "#undef GET_REGINFO_MC_DESC\n"; 707224145Sdim 708234353Sdim const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); 709224145Sdim 710263508Sdim ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); 711263508Sdim // The lists of sub-registers and super-registers go in the same array. That 712263508Sdim // allows us to share suffixes. 713234353Sdim typedef std::vector<const CodeGenRegister*> RegVec; 714224145Sdim 715239462Sdim // Differentially encoded lists. 716239462Sdim SequenceToOffsetTable<DiffVec> DiffSeqs; 717239462Sdim SmallVector<DiffVec, 4> SubRegLists(Regs.size()); 718239462Sdim SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); 719239462Sdim SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); 720239462Sdim SmallVector<unsigned, 4> RegUnitInitScale(Regs.size()); 721239462Sdim 722239462Sdim // Keep track of sub-register names as well. These are not differentially 723239462Sdim // encoded. 724239462Sdim typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec; 725263508Sdim SequenceToOffsetTable<SubRegIdxVec, CodeGenSubRegIndex::Less> SubRegIdxSeqs; 726239462Sdim SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); 727239462Sdim 728239462Sdim SequenceToOffsetTable<std::string> RegStrings; 729239462Sdim 730234353Sdim // Precompute register lists for the SequenceToOffsetTable. 731234353Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 732234353Sdim const CodeGenRegister *Reg = Regs[i]; 733224145Sdim 734239462Sdim RegStrings.add(Reg->getName()); 735239462Sdim 736234353Sdim // Compute the ordered sub-register list. 737234353Sdim SetVector<const CodeGenRegister*> SR; 738234353Sdim Reg->addSubRegsPreOrder(SR, RegBank); 739239462Sdim diffEncode(SubRegLists[i], Reg->EnumValue, SR.begin(), SR.end()); 740239462Sdim DiffSeqs.add(SubRegLists[i]); 741224145Sdim 742239462Sdim // Compute the corresponding sub-register indexes. 743239462Sdim SubRegIdxVec &SRIs = SubRegIdxLists[i]; 744239462Sdim for (unsigned j = 0, je = SR.size(); j != je; ++j) 745239462Sdim SRIs.push_back(Reg->getSubRegIndex(SR[j])); 746239462Sdim SubRegIdxSeqs.add(SRIs); 747239462Sdim 748234353Sdim // Super-registers are already computed. 749234353Sdim const RegVec &SuperRegList = Reg->getSuperRegs(); 750239462Sdim diffEncode(SuperRegLists[i], Reg->EnumValue, 751239462Sdim SuperRegList.begin(), SuperRegList.end()); 752239462Sdim DiffSeqs.add(SuperRegLists[i]); 753224145Sdim 754239462Sdim // Differentially encode the register unit list, seeded by register number. 755239462Sdim // First compute a scale factor that allows more diff-lists to be reused: 756239462Sdim // 757239462Sdim // D0 -> (S0, S1) 758239462Sdim // D1 -> (S2, S3) 759239462Sdim // 760239462Sdim // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial 761239462Sdim // value for the differential decoder is the register number multiplied by 762239462Sdim // the scale. 763239462Sdim // 764239462Sdim // Check the neighboring registers for arithmetic progressions. 765239462Sdim unsigned ScaleA = ~0u, ScaleB = ~0u; 766239462Sdim ArrayRef<unsigned> RUs = Reg->getNativeRegUnits(); 767239462Sdim if (i > 0 && Regs[i-1]->getNativeRegUnits().size() == RUs.size()) 768239462Sdim ScaleB = RUs.front() - Regs[i-1]->getNativeRegUnits().front(); 769239462Sdim if (i+1 != Regs.size() && 770239462Sdim Regs[i+1]->getNativeRegUnits().size() == RUs.size()) 771239462Sdim ScaleA = Regs[i+1]->getNativeRegUnits().front() - RUs.front(); 772239462Sdim unsigned Scale = std::min(ScaleB, ScaleA); 773239462Sdim // Default the scale to 0 if it can't be encoded in 4 bits. 774239462Sdim if (Scale >= 16) 775239462Sdim Scale = 0; 776239462Sdim RegUnitInitScale[i] = Scale; 777239462Sdim DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg->EnumValue, RUs)); 778224145Sdim } 779224145Sdim 780234353Sdim // Compute the final layout of the sequence table. 781239462Sdim DiffSeqs.layout(); 782239462Sdim SubRegIdxSeqs.layout(); 783234353Sdim 784234353Sdim OS << "namespace llvm {\n\n"; 785234353Sdim 786234353Sdim const std::string &TargetName = Target.getName(); 787234353Sdim 788239462Sdim // Emit the shared table of differential lists. 789249423Sdim OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; 790239462Sdim DiffSeqs.emit(OS, printDiff16); 791234353Sdim OS << "};\n\n"; 792234353Sdim 793239462Sdim // Emit the table of sub-register indexes. 794239462Sdim OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 795239462Sdim SubRegIdxSeqs.emit(OS, printSubRegIndex); 796239462Sdim OS << "};\n\n"; 797239462Sdim 798263508Sdim // Emit the table of sub-register index sizes. 799263508Sdim OS << "extern const MCRegisterInfo::SubRegCoveredBits " 800263508Sdim << TargetName << "SubRegIdxRanges[] = {\n"; 801263508Sdim OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; 802263508Sdim for (ArrayRef<CodeGenSubRegIndex*>::const_iterator 803263508Sdim SRI = SubRegIndices.begin(), SRE = SubRegIndices.end(); 804263508Sdim SRI != SRE; ++SRI) { 805263508Sdim OS << " { " << (*SRI)->Offset << ", " 806263508Sdim << (*SRI)->Size 807263508Sdim << " },\t// " << (*SRI)->getName() << "\n"; 808263508Sdim } 809263508Sdim OS << "};\n\n"; 810263508Sdim 811239462Sdim // Emit the string table. 812239462Sdim RegStrings.layout(); 813239462Sdim OS << "extern const char " << TargetName << "RegStrings[] = {\n"; 814239462Sdim RegStrings.emit(OS, printChar); 815239462Sdim OS << "};\n\n"; 816239462Sdim 817234353Sdim OS << "extern const MCRegisterDesc " << TargetName 818224145Sdim << "RegDesc[] = { // Descriptors\n"; 819263508Sdim OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0 },\n"; 820224145Sdim 821234353Sdim // Emit the register descriptors now. 822224145Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 823234353Sdim const CodeGenRegister *Reg = Regs[i]; 824239462Sdim OS << " { " << RegStrings.get(Reg->getName()) << ", " 825239462Sdim << DiffSeqs.get(SubRegLists[i]) << ", " 826239462Sdim << DiffSeqs.get(SuperRegLists[i]) << ", " 827239462Sdim << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 828239462Sdim << (DiffSeqs.get(RegUnitLists[i])*16 + RegUnitInitScale[i]) << " },\n"; 829224145Sdim } 830224145Sdim OS << "};\n\n"; // End of register descriptors... 831224145Sdim 832239462Sdim // Emit the table of register unit roots. Each regunit has one or two root 833239462Sdim // registers. 834239462Sdim OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2] = {\n"; 835239462Sdim for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { 836239462Sdim ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots(); 837239462Sdim assert(!Roots.empty() && "All regunits must have a root register."); 838239462Sdim assert(Roots.size() <= 2 && "More than two roots not supported yet."); 839239462Sdim OS << " { " << getQualifiedName(Roots.front()->TheDef); 840239462Sdim for (unsigned r = 1; r != Roots.size(); ++r) 841239462Sdim OS << ", " << getQualifiedName(Roots[r]->TheDef); 842239462Sdim OS << " },\n"; 843239462Sdim } 844239462Sdim OS << "};\n\n"; 845239462Sdim 846226633Sdim ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); 847226633Sdim 848226633Sdim // Loop over all of the register classes... emitting each one. 849226633Sdim OS << "namespace { // Register classes...\n"; 850226633Sdim 851226633Sdim // Emit the register enum value arrays for each RegisterClass 852226633Sdim for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 853226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 854226633Sdim ArrayRef<Record*> Order = RC.getOrder(); 855226633Sdim 856226633Sdim // Give the register class a legal C name if it's anonymous. 857226633Sdim std::string Name = RC.getName(); 858226633Sdim 859226633Sdim // Emit the register list now. 860226633Sdim OS << " // " << Name << " Register Class...\n" 861234353Sdim << " const uint16_t " << Name 862226633Sdim << "[] = {\n "; 863226633Sdim for (unsigned i = 0, e = Order.size(); i != e; ++i) { 864226633Sdim Record *Reg = Order[i]; 865226633Sdim OS << getQualifiedName(Reg) << ", "; 866226633Sdim } 867226633Sdim OS << "\n };\n\n"; 868226633Sdim 869226633Sdim OS << " // " << Name << " Bit set.\n" 870234353Sdim << " const uint8_t " << Name 871226633Sdim << "Bits[] = {\n "; 872226633Sdim BitVectorEmitter BVE; 873226633Sdim for (unsigned i = 0, e = Order.size(); i != e; ++i) { 874226633Sdim Record *Reg = Order[i]; 875226633Sdim BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); 876226633Sdim } 877226633Sdim BVE.print(OS); 878226633Sdim OS << "\n };\n\n"; 879226633Sdim 880226633Sdim } 881226633Sdim OS << "}\n\n"; 882226633Sdim 883234353Sdim OS << "extern const MCRegisterClass " << TargetName 884234353Sdim << "MCRegisterClasses[] = {\n"; 885226633Sdim 886226633Sdim for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 887226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 888234353Sdim 889234353Sdim // Asserts to make sure values will fit in table assuming types from 890234353Sdim // MCRegisterInfo.h 891234353Sdim assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large."); 892234353Sdim assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large."); 893234353Sdim assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large."); 894234353Sdim 895234353Sdim OS << " { " << '\"' << RC.getName() << "\", " 896234353Sdim << RC.getName() << ", " << RC.getName() << "Bits, " 897234353Sdim << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " 898234353Sdim << RC.getQualifiedName() + "RegClassID" << ", " 899226633Sdim << RC.SpillSize/8 << ", " 900226633Sdim << RC.SpillAlignment/8 << ", " 901226633Sdim << RC.CopyCost << ", " 902234353Sdim << RC.Allocatable << " },\n"; 903226633Sdim } 904226633Sdim 905226633Sdim OS << "};\n\n"; 906226633Sdim 907239462Sdim EmitRegMappingTables(OS, Regs, false); 908239462Sdim 909239462Sdim // Emit Reg encoding table 910239462Sdim OS << "extern const uint16_t " << TargetName; 911239462Sdim OS << "RegEncodingTable[] = {\n"; 912239462Sdim // Add entry for NoRegister 913239462Sdim OS << " 0,\n"; 914239462Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 915239462Sdim Record *Reg = Regs[i]->TheDef; 916239462Sdim BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); 917239462Sdim uint64_t Value = 0; 918239462Sdim for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { 919243830Sdim if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b))) 920239462Sdim Value |= (uint64_t)B->getValue() << b; 921234353Sdim } 922239462Sdim OS << " " << Value << ",\n"; 923234353Sdim } 924239462Sdim OS << "};\n"; // End of HW encoding table 925234353Sdim 926224145Sdim // MCRegisterInfo initialization routine. 927224145Sdim OS << "static inline void Init" << TargetName 928226633Sdim << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 929249423Sdim << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {\n" 930239462Sdim << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 931249423Sdim << Regs.size()+1 << ", RA, PC, " << TargetName << "MCRegisterClasses, " 932239462Sdim << RegisterClasses.size() << ", " 933239462Sdim << TargetName << "RegUnitRoots, " 934239462Sdim << RegBank.getNumNativeRegUnits() << ", " 935239462Sdim << TargetName << "RegDiffLists, " 936239462Sdim << TargetName << "RegStrings, " 937239462Sdim << TargetName << "SubRegIdxLists, " 938243830Sdim << (SubRegIndices.size() + 1) << ",\n" 939263508Sdim << TargetName << "SubRegIdxRanges, " 940239462Sdim << " " << TargetName << "RegEncodingTable);\n\n"; 941224145Sdim 942226633Sdim EmitRegMapping(OS, Regs, false); 943226633Sdim 944226633Sdim OS << "}\n\n"; 945226633Sdim 946224145Sdim OS << "} // End llvm namespace \n"; 947224145Sdim OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 948224145Sdim} 949224145Sdim 950224145Sdimvoid 951224145SdimRegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 952224145Sdim CodeGenRegBank &RegBank) { 953239462Sdim emitSourceFileHeader("Register Information Header Fragment", OS); 954224145Sdim 955224145Sdim OS << "\n#ifdef GET_REGINFO_HEADER\n"; 956224145Sdim OS << "#undef GET_REGINFO_HEADER\n"; 957224145Sdim 958193323Sed const std::string &TargetName = Target.getName(); 959193323Sed std::string ClassName = TargetName + "GenRegisterInfo"; 960193323Sed 961234353Sdim OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n"; 962193323Sed 963193323Sed OS << "namespace llvm {\n\n"; 964193323Sed 965193323Sed OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 966226633Sdim << " explicit " << ClassName 967249423Sdim << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n" 968193323Sed << " virtual bool needsStackRealignment(const MachineFunction &) const\n" 969239462Sdim << " { return false; }\n"; 970239462Sdim if (!RegBank.getSubRegIndices().empty()) { 971243830Sdim OS << " virtual unsigned composeSubRegIndicesImpl" 972243830Sdim << "(unsigned, unsigned) const;\n" 973243830Sdim << " virtual const TargetRegisterClass *" 974239462Sdim "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"; 975239462Sdim } 976243830Sdim OS << " virtual const RegClassWeight &getRegClassWeight(" 977234353Sdim << "const TargetRegisterClass *RC) const;\n" 978249423Sdim << " virtual unsigned getRegUnitWeight(unsigned RegUnit) const;\n" 979243830Sdim << " virtual unsigned getNumRegPressureSets() const;\n" 980243830Sdim << " virtual const char *getRegPressureSetName(unsigned Idx) const;\n" 981243830Sdim << " virtual unsigned getRegPressureSetLimit(unsigned Idx) const;\n" 982243830Sdim << " virtual const int *getRegClassPressureSets(" 983234353Sdim << "const TargetRegisterClass *RC) const;\n" 984249423Sdim << " virtual const int *getRegUnitPressureSets(unsigned RegUnit) const;\n" 985193323Sed << "};\n\n"; 986193323Sed 987226633Sdim ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); 988193323Sed 989193323Sed if (!RegisterClasses.empty()) { 990226633Sdim OS << "namespace " << RegisterClasses[0]->Namespace 991193323Sed << " { // Register classes\n"; 992221345Sdim 993193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 994226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[i]; 995224145Sdim const std::string &Name = RC.getName(); 996193323Sed 997193323Sed // Output the extern for the instance. 998234353Sdim OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; 999193323Sed } 1000193323Sed OS << "} // end of namespace " << TargetName << "\n\n"; 1001193323Sed } 1002193323Sed OS << "} // End llvm namespace \n"; 1003224145Sdim OS << "#endif // GET_REGINFO_HEADER\n\n"; 1004193323Sed} 1005193323Sed 1006224145Sdim// 1007224145Sdim// runTargetDesc - Output the target register and register file descriptions. 1008224145Sdim// 1009224145Sdimvoid 1010224145SdimRegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 1011224145Sdim CodeGenRegBank &RegBank){ 1012239462Sdim emitSourceFileHeader("Target Register and Register Classes Information", OS); 1013193323Sed 1014224145Sdim OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 1015224145Sdim OS << "#undef GET_REGINFO_TARGET_DESC\n"; 1016193323Sed 1017193323Sed OS << "namespace llvm {\n\n"; 1018193323Sed 1019226633Sdim // Get access to MCRegisterClass data. 1020234353Sdim OS << "extern const MCRegisterClass " << Target.getName() 1021234353Sdim << "MCRegisterClasses[];\n"; 1022226633Sdim 1023223017Sdim // Start out by emitting each of the register classes. 1024226633Sdim ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); 1025239462Sdim ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); 1026193323Sed 1027223017Sdim // Collect all registers belonging to any allocatable class. 1028223017Sdim std::set<Record*> AllocatableRegs; 1029223017Sdim 1030226633Sdim // Collect allocatable registers. 1031193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 1032226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 1033224145Sdim ArrayRef<Record*> Order = RC.getOrder(); 1034193323Sed 1035223017Sdim if (RC.Allocatable) 1036224145Sdim AllocatableRegs.insert(Order.begin(), Order.end()); 1037226633Sdim } 1038223017Sdim 1039234353Sdim // Build a shared array of value types. 1040249423Sdim SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs; 1041234353Sdim for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) 1042234353Sdim VTSeqs.add(RegisterClasses[rc]->VTs); 1043234353Sdim VTSeqs.layout(); 1044234353Sdim OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1045234353Sdim VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); 1046234353Sdim OS << "};\n"; 1047221345Sdim 1048243830Sdim // Emit SubRegIndex names, skipping 0. 1049243830Sdim OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; 1050239462Sdim for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 1051239462Sdim OS << SubRegIndices[i]->getName(); 1052243830Sdim if (i + 1 != e) 1053239462Sdim OS << "\", \""; 1054239462Sdim } 1055239462Sdim OS << "\" };\n\n"; 1056239462Sdim 1057243830Sdim // Emit SubRegIndex lane masks, including 0. 1058243830Sdim OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n"; 1059243830Sdim for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 1060243830Sdim OS << format(" 0x%08x, // ", SubRegIndices[i]->LaneMask) 1061243830Sdim << SubRegIndices[i]->getName() << '\n'; 1062243830Sdim } 1063243830Sdim OS << " };\n\n"; 1064243830Sdim 1065239462Sdim OS << "\n"; 1066239462Sdim 1067193323Sed // Now that all of the structs have been emitted, emit the instances. 1068193323Sed if (!RegisterClasses.empty()) { 1069234353Sdim OS << "\nstatic const TargetRegisterClass *const " 1070234353Sdim << "NullRegClasses[] = { NULL };\n\n"; 1071226633Sdim 1072239462Sdim // Emit register class bit mask tables. The first bit mask emitted for a 1073239462Sdim // register class, RC, is the set of sub-classes, including RC itself. 1074239462Sdim // 1075239462Sdim // If RC has super-registers, also create a list of subreg indices and bit 1076239462Sdim // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, 1077239462Sdim // SuperRC, that satisfies: 1078239462Sdim // 1079239462Sdim // For all SuperReg in SuperRC: SuperReg:Idx in RC 1080239462Sdim // 1081239462Sdim // The 0-terminated list of subreg indices starts at: 1082239462Sdim // 1083239462Sdim // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... 1084239462Sdim // 1085239462Sdim // The corresponding bitmasks follow the sub-class mask in memory. Each 1086239462Sdim // mask has RCMaskWords uint32_t entries. 1087239462Sdim // 1088239462Sdim // Every bit mask present in the list has at least one bit set. 1089193323Sed 1090239462Sdim // Compress the sub-reg index lists. 1091239462Sdim typedef std::vector<const CodeGenSubRegIndex*> IdxList; 1092239462Sdim SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); 1093263508Sdim SequenceToOffsetTable<IdxList, CodeGenSubRegIndex::Less> SuperRegIdxSeqs; 1094239462Sdim BitVector MaskBV(RegisterClasses.size()); 1095193323Sed 1096193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 1097226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 1098239462Sdim OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n "; 1099239462Sdim printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1100193323Sed 1101239462Sdim // Emit super-reg class masks for any relevant SubRegIndices that can 1102239462Sdim // project into RC. 1103239462Sdim IdxList &SRIList = SuperRegIdxLists[rc]; 1104239462Sdim for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { 1105239462Sdim CodeGenSubRegIndex *Idx = SubRegIndices[sri]; 1106239462Sdim MaskBV.reset(); 1107239462Sdim RC.getSuperRegClasses(Idx, MaskBV); 1108239462Sdim if (MaskBV.none()) 1109239462Sdim continue; 1110239462Sdim SRIList.push_back(Idx); 1111239462Sdim OS << "\n "; 1112239462Sdim printBitVectorAsHex(OS, MaskBV, 32); 1113239462Sdim OS << "// " << Idx->getName(); 1114239462Sdim } 1115239462Sdim SuperRegIdxSeqs.add(SRIList); 1116234353Sdim OS << "\n};\n\n"; 1117193323Sed } 1118193323Sed 1119239462Sdim OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1120239462Sdim SuperRegIdxSeqs.layout(); 1121239462Sdim SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1122239462Sdim OS << "};\n\n"; 1123239462Sdim 1124226633Sdim // Emit NULL terminated super-class lists. 1125193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 1126226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 1127226633Sdim ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); 1128193323Sed 1129226633Sdim // Skip classes without supers. We can reuse NullRegClasses. 1130226633Sdim if (Supers.empty()) 1131226633Sdim continue; 1132193323Sed 1133234353Sdim OS << "static const TargetRegisterClass *const " 1134226633Sdim << RC.getName() << "Superclasses[] = {\n"; 1135226633Sdim for (unsigned i = 0; i != Supers.size(); ++i) 1136234353Sdim OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n"; 1137234353Sdim OS << " NULL\n};\n\n"; 1138193323Sed } 1139193323Sed 1140224145Sdim // Emit methods. 1141193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 1142226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[i]; 1143224145Sdim if (!RC.AltOrderSelect.empty()) { 1144224145Sdim OS << "\nstatic inline unsigned " << RC.getName() 1145224145Sdim << "AltOrderSelect(const MachineFunction &MF) {" 1146234353Sdim << RC.AltOrderSelect << "}\n\n" 1147249423Sdim << "static ArrayRef<MCPhysReg> " << RC.getName() 1148234353Sdim << "GetRawAllocationOrder(const MachineFunction &MF) {\n"; 1149224145Sdim for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 1150224145Sdim ArrayRef<Record*> Elems = RC.getOrder(oi); 1151234353Sdim if (!Elems.empty()) { 1152249423Sdim OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; 1153234353Sdim for (unsigned elem = 0; elem != Elems.size(); ++elem) 1154234353Sdim OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1155234353Sdim OS << " };\n"; 1156234353Sdim } 1157224145Sdim } 1158226633Sdim OS << " const MCRegisterClass &MCR = " << Target.getName() 1159234353Sdim << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" 1160249423Sdim << " const ArrayRef<MCPhysReg> Order[] = {\n" 1161226633Sdim << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; 1162224145Sdim for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 1163234353Sdim if (RC.getOrder(oi).empty()) 1164249423Sdim OS << "),\n ArrayRef<MCPhysReg>("; 1165234353Sdim else 1166234353Sdim OS << "),\n makeArrayRef(AltOrder" << oi; 1167224145Sdim OS << ")\n };\n const unsigned Select = " << RC.getName() 1168224145Sdim << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 1169224145Sdim << ");\n return Order[Select];\n}\n"; 1170224145Sdim } 1171193323Sed } 1172221345Sdim 1173234353Sdim // Now emit the actual value-initialized register class instances. 1174234353Sdim OS << "namespace " << RegisterClasses[0]->Namespace 1175234353Sdim << " { // Register class instances\n"; 1176234353Sdim 1177234353Sdim for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 1178234353Sdim const CodeGenRegisterClass &RC = *RegisterClasses[i]; 1179234353Sdim OS << " extern const TargetRegisterClass " 1180234353Sdim << RegisterClasses[i]->getName() << "RegClass = {\n " 1181234353Sdim << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName() 1182234353Sdim << "RegClassID],\n " 1183234353Sdim << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " 1184239462Sdim << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " 1185239462Sdim << SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n "; 1186234353Sdim if (RC.getSuperClasses().empty()) 1187234353Sdim OS << "NullRegClasses,\n "; 1188234353Sdim else 1189234353Sdim OS << RC.getName() << "Superclasses,\n "; 1190234353Sdim if (RC.AltOrderSelect.empty()) 1191234353Sdim OS << "0\n"; 1192234353Sdim else 1193234353Sdim OS << RC.getName() << "GetRawAllocationOrder\n"; 1194234353Sdim OS << " };\n\n"; 1195234353Sdim } 1196234353Sdim 1197193323Sed OS << "}\n"; 1198193323Sed } 1199193323Sed 1200193323Sed OS << "\nnamespace {\n"; 1201193323Sed OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 1202193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 1203226633Sdim OS << " &" << RegisterClasses[i]->getQualifiedName() 1204193323Sed << "RegClass,\n"; 1205193323Sed OS << " };\n"; 1206224145Sdim OS << "}\n"; // End of anonymous namespace... 1207193323Sed 1208224145Sdim // Emit extra information about registers. 1209224145Sdim const std::string &TargetName = Target.getName(); 1210234353Sdim OS << "\nstatic const TargetRegisterInfoDesc " 1211234353Sdim << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n"; 1212234353Sdim OS << " { 0, 0 },\n"; 1213221345Sdim 1214224145Sdim const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); 1215193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 1216224145Sdim const CodeGenRegister &Reg = *Regs[i]; 1217234353Sdim OS << " { "; 1218224145Sdim OS << Reg.CostPerUse << ", " 1219223017Sdim << int(AllocatableRegs.count(Reg.TheDef)) << " },\n"; 1220193323Sed } 1221234353Sdim OS << "};\n"; // End of register descriptors... 1222208599Srdivacky 1223224145Sdim 1224193323Sed std::string ClassName = Target.getName() + "GenRegisterInfo"; 1225193323Sed 1226243830Sdim if (!SubRegIndices.empty()) 1227243830Sdim emitComposeSubRegIndices(OS, RegBank, ClassName); 1228210299Sed 1229226633Sdim // Emit getSubClassWithSubReg. 1230239462Sdim if (!SubRegIndices.empty()) { 1231239462Sdim OS << "const TargetRegisterClass *" << ClassName 1232239462Sdim << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 1233239462Sdim << " const {\n"; 1234226633Sdim // Use the smallest type that can hold a regclass ID with room for a 1235226633Sdim // sentinel. 1236226633Sdim if (RegisterClasses.size() < UINT8_MAX) 1237226633Sdim OS << " static const uint8_t Table["; 1238226633Sdim else if (RegisterClasses.size() < UINT16_MAX) 1239226633Sdim OS << " static const uint16_t Table["; 1240226633Sdim else 1241243830Sdim PrintFatalError("Too many register classes."); 1242226633Sdim OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n"; 1243226633Sdim for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) { 1244226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rci]; 1245226633Sdim OS << " {\t// " << RC.getName() << "\n"; 1246226633Sdim for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { 1247234353Sdim CodeGenSubRegIndex *Idx = SubRegIndices[sri]; 1248226633Sdim if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx)) 1249226633Sdim OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName() 1250226633Sdim << " -> " << SRC->getName() << "\n"; 1251226633Sdim else 1252226633Sdim OS << " 0,\t// " << Idx->getName() << "\n"; 1253226633Sdim } 1254226633Sdim OS << " },\n"; 1255226633Sdim } 1256226633Sdim OS << " };\n assert(RC && \"Missing regclass\");\n" 1257226633Sdim << " if (!Idx) return RC;\n --Idx;\n" 1258226633Sdim << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n" 1259226633Sdim << " unsigned TV = Table[RC->getID()][Idx];\n" 1260239462Sdim << " return TV ? getRegClass(TV - 1) : 0;\n}\n\n"; 1261226633Sdim } 1262226633Sdim 1263234353Sdim EmitRegUnitPressure(OS, RegBank, ClassName); 1264234353Sdim 1265193323Sed // Emit the constructor of the class... 1266234353Sdim OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1267249423Sdim OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; 1268239462Sdim OS << "extern const char " << TargetName << "RegStrings[];\n"; 1269239462Sdim OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2];\n"; 1270239462Sdim OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1271263508Sdim OS << "extern const MCRegisterInfo::SubRegCoveredBits " 1272263508Sdim << TargetName << "SubRegIdxRanges[];\n"; 1273239462Sdim OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1274224145Sdim 1275234353Sdim EmitRegMappingTables(OS, Regs, true); 1276234353Sdim 1277234353Sdim OS << ClassName << "::\n" << ClassName 1278249423Sdim << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n" 1279224145Sdim << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" 1280208599Srdivacky << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" 1281263508Sdim << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x"; 1282263508Sdim OS.write_hex(RegBank.CoveringLanes); 1283263508Sdim OS << ") {\n" 1284224145Sdim << " InitMCRegisterInfo(" << TargetName << "RegDesc, " 1285249423Sdim << Regs.size()+1 << ", RA, PC,\n " << TargetName 1286234353Sdim << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" 1287239462Sdim << " " << TargetName << "RegUnitRoots,\n" 1288239462Sdim << " " << RegBank.getNumNativeRegUnits() << ",\n" 1289239462Sdim << " " << TargetName << "RegDiffLists,\n" 1290239462Sdim << " " << TargetName << "RegStrings,\n" 1291239462Sdim << " " << TargetName << "SubRegIdxLists,\n" 1292243830Sdim << " " << SubRegIndices.size() + 1 << ",\n" 1293263508Sdim << " " << TargetName << "SubRegIdxRanges,\n" 1294239462Sdim << " " << TargetName << "RegEncodingTable);\n\n"; 1295193323Sed 1296226633Sdim EmitRegMapping(OS, Regs, true); 1297193323Sed 1298226633Sdim OS << "}\n\n"; 1299193323Sed 1300234353Sdim 1301234353Sdim // Emit CalleeSavedRegs information. 1302234353Sdim std::vector<Record*> CSRSets = 1303234353Sdim Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1304234353Sdim for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) { 1305234353Sdim Record *CSRSet = CSRSets[i]; 1306234353Sdim const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); 1307234353Sdim assert(Regs && "Cannot expand CalleeSavedRegs instance"); 1308234353Sdim 1309234353Sdim // Emit the *_SaveList list of callee-saved registers. 1310249423Sdim OS << "static const MCPhysReg " << CSRSet->getName() 1311234353Sdim << "_SaveList[] = { "; 1312234353Sdim for (unsigned r = 0, re = Regs->size(); r != re; ++r) 1313234353Sdim OS << getQualifiedName((*Regs)[r]) << ", "; 1314234353Sdim OS << "0 };\n"; 1315234353Sdim 1316234353Sdim // Emit the *_RegMask bit mask of call-preserved registers. 1317263508Sdim BitVector Covered = RegBank.computeCoveredRegisters(*Regs); 1318263508Sdim 1319263508Sdim // Check for an optional OtherPreserved set. 1320263508Sdim // Add those registers to RegMask, but not to SaveList. 1321263508Sdim if (DagInit *OPDag = 1322263508Sdim dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) { 1323263508Sdim SetTheory::RecSet OPSet; 1324263508Sdim RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc()); 1325263508Sdim Covered |= RegBank.computeCoveredRegisters( 1326263508Sdim ArrayRef<Record*>(OPSet.begin(), OPSet.end())); 1327263508Sdim } 1328263508Sdim 1329234353Sdim OS << "static const uint32_t " << CSRSet->getName() 1330234353Sdim << "_RegMask[] = { "; 1331263508Sdim printBitVectorAsHex(OS, Covered, 32); 1332234353Sdim OS << "};\n"; 1333234353Sdim } 1334234353Sdim OS << "\n\n"; 1335234353Sdim 1336193323Sed OS << "} // End llvm namespace \n"; 1337224145Sdim OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 1338193323Sed} 1339224145Sdim 1340224145Sdimvoid RegisterInfoEmitter::run(raw_ostream &OS) { 1341224145Sdim CodeGenTarget Target(Records); 1342224145Sdim CodeGenRegBank &RegBank = Target.getRegBank(); 1343224145Sdim RegBank.computeDerivedInfo(); 1344224145Sdim 1345224145Sdim runEnums(OS, Target, RegBank); 1346224145Sdim runMCDesc(OS, Target, RegBank); 1347224145Sdim runTargetHeader(OS, Target, RegBank); 1348224145Sdim runTargetDesc(OS, Target, RegBank); 1349224145Sdim} 1350239462Sdim 1351239462Sdimnamespace llvm { 1352239462Sdim 1353239462Sdimvoid EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { 1354239462Sdim RegisterInfoEmitter(RK).run(OS); 1355239462Sdim} 1356239462Sdim 1357239462Sdim} // End llvm namespace 1358