Searched refs:RD4 (Results 1 - 25 of 30) sorted by relevance

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/freebsd-10.1-release/sys/arm/at91/
H A Dat91_pit.c74 RD4(struct pit_softc *sc, bus_size_t off) function
97 last = PIT_PIV(RD4(sc, PIT_PIIR));
105 piv = PIT_PIV(RD4(sc, PIT_PIIR));
180 if (RD4(sc, PIT_SR) & PIT_PITS_DONE) {
181 icnt = RD4(sc, PIT_PIVR) >> 20;
184 timecount += PIT_PIV(RD4(sc, PIT_MR)) * icnt;
197 piir = RD4(sc, PIT_PIIR); /* Current count | over flows */
199 return (timecount + PIT_PIV(piir) + PIT_PIV(RD4(sc, PIT_MR)) * icnt);
H A Dat91_rtc.c81 RD4(struct at91_rtc_softc *sc, bus_size_t off) function
122 status = RD4(sc, RTC_SR);
178 if (RTC_CALR_CEN(RD4(sc, RTC_CALR)) == 19)
266 if (RD4(sc, RTC_VER) & (RTC_VER_NVTIM | RTC_VER_NVCAL))
276 timr = RD4(sc, RTC_TIMR);
277 calr = RD4(sc, RTC_CALR);
278 timr2 = RD4(sc, RTC_TIMR);
279 calr2 = RD4(sc, RTC_CALR);
310 while ((RD4(sc, RTC_SR) & RTC_SR_SECEV) == 0)
319 while ((RD4(s
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H A Dif_ate.c167 RD4(struct ate_softc *sc, bus_size_t off) function
291 (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII;
294 (RD4(sc, ETHB_UIO) & ETHB_UIO_RMII) == ETHB_UIO_RMII;
621 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) | ETHB_UIO_CLKE);
688 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE);
733 reg = RD4(sc, ETH_CFG);
777 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE);
778 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE);
779 c = RD4(sc, ETH_SCOL);
782 c = RD4(s
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H A Dat91_pio.c77 RD4(struct at91_pio_softc *sc, bus_size_t off) function
178 RD4(sc, PIO_ABSR), RD4(sc, PIO_OSR), RD4(sc, PIO_PSR),
179 RD4(sc, PIO_ODSR));
263 status = RD4(sc, PIO_ISR) & RD4(sc, PIO_IMR);
417 *(uint32_t *)data = RD4(sc, PIO_PDSR);
473 info->output_status = RD4(sc, PIO_ODSR);
474 info->input_status = RD4(s
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H A Dat91_rst.c68 RD4(struct at91_rst_softc *sc, bus_size_t off) function
156 switch (RD4(sc, RST_SR) & RST_SR_RST_MASK) {
191 } else if ((RD4(sc, RST_SR) & RST_SR_NRSTL)) {
206 if (RD4(sc, RST_SR) & RST_SR_URSTS) {
H A Dat91_aic.c62 RD4(struct aic_softc *sc, bus_size_t off) function
88 irq = RD4(sc, IC_IVR);
89 status = RD4(sc, IC_ISR);
H A Dat91_pmc.c174 RD4(struct at91_pmc_softc *sc, bus_size_t off) function
244 if (RD4(sc, CKGR_PLLBR) != value) {
246 while (on && (RD4(sc, PMC_SR) & PMC_IER_LOCKB) != PMC_IER_LOCKB)
263 WR4(sc, CKGR_UCKR, RD4(sc, CKGR_UCKR) | value);
264 while ((RD4(sc, PMC_SR) & PMC_IER_LOCKU) != on)
278 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) != clk->pmc_mask)
281 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) == clk->pmc_mask)
292 while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) != clk->pmc_mask)
295 while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) == clk->pmc_mask)
498 ckgr_val = (RD4(NUL
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H A Dat91_st.c58 RD4(bus_size_t off) function
91 cur1 = RD4(ST_CRTR);
92 cur2 = RD4(ST_CRTR);
114 if (RD4(ST_SR) & ST_SR_PITS) {
H A Dat91_wdt.c68 RD4(struct wdt_softc *sc, bus_size_t off) function
87 if (RD4(sc, WDT_SR) & (WDT_WDUNF | WDT_WDERR)) {
172 wdt_mr = RD4(sc, WDT_MR);
190 wdt_mr = RD4(sc, WDT_MR);
H A Dat91_mci.c194 RD4(struct at91_mci_softc *sc, bus_size_t off) function
282 imr = RD4(sc, MCI_IMR);
283 mr = RD4(sc, MCI_MR) & 0x7fff;
284 sdcr = RD4(sc, MCI_SDCR);
285 dtor = RD4(sc, MCI_DTOR);
305 RD4(sc, MCI_SR);
598 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS);
600 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS);
601 WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv);
705 mr = RD4(s
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H A Dat91_spi.c77 RD4(struct at91_spi_softc *sc, bus_size_t off) function
189 RD4(sc, SPI_RDR);
190 RD4(sc, SPI_SR);
340 err = (RD4(sc, SPI_MR) & ~0x000f0000) | CS_TO_MR(cs);
419 sr = RD4(sc, SPI_SR) & RD4(sc, SPI_IMR);
H A Dat91_twi.c76 RD4(struct at91_twi_softc *sc, bus_size_t off) function
238 status = RD4(sc, TWI_SR);
263 while (!((sr = RD4(sc, TWI_SR)) & bit) && counter-- > 0 &&
368 sr = RD4(sc, TWI_SR);
370 if ((sr = RD4(sc, TWI_SR)) & TWI_SR_RXRDY) {
372 *buf++ = RD4(sc, TWI_RHR) & 0xff;
H A Duart_dev_at91usart.c81 #define RD4(bas, reg) \ macro
281 if (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
311 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
323 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0);
335 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) {
340 c = RD4(bas, USART_RHR) & 0xff;
455 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
654 csr = RD4(&sc->sc_bas, USART_CSR);
753 if (RD4(&sc->sc_bas, PDC_RNCR) == 0) {
756 len = sc->sc_rxfifosz - RD4(
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/freebsd-10.1-release/sys/arm/freescale/imx/
H A Dimx_sdhci.c163 RD4(struct imx_sdhci_softc *sc, bus_size_t off) function
188 wrk32 = RD4(sc, SDHC_PROT_CTRL);
228 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
250 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37);
273 val32 = RD4(sc, SDHCI_INT_STATUS);
274 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
287 wrk32 = RD4(sc, SDHC_VEND_SPEC);
290 wrk32 = RD4(sc, SDHC_PRES_STATE);
297 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
306 val32 = RD4(s
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H A Dimx6_ccm.c66 RD4(struct ccm_softc *sc, bus_size_t off) function
126 reg = RD4(sc, CCM_CGPR);
129 reg = RD4(sc, CCM_CLPCR);
166 WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS);
/freebsd-10.1-release/sys/arm/xilinx/
H A Dzy7_gpio.c96 #define RD4(sc, off) bus_read_4((sc)->mem_res, (off)) macro
168 if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) {
170 if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0)
197 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31)));
201 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) &
205 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) |
210 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31)));
212 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31)));
251 *value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1;
268 RD4(s
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H A Duart_dev_cdnc.c59 #define RD4(bas, reg) \ macro
339 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) &
345 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) &
357 return ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
371 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
378 c = RD4(bas, CDNC_UART_FIFO);
499 modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG) &
521 status = RD4(bas, CDNC_UART_ISTAT_REG);
531 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
533 c = RD4(ba
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H A Dzy7_slcr.c77 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro
124 RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff);
240 bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE);
245 pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE);
261 zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT);
H A Dzy7_devcfg.c87 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro
255 WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) &
268 devcfg_ctl = RD4(sc, ZY7_DEVCFG_CTRL);
282 if ((RD4(sc, ZY7_DEVCFG_STATUS) &
300 while ((RD4(sc, ZY7_DEVCFG_STATUS) &
410 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) &
456 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) &
489 istatus = RD4(sc, ZY7_DEVCFG_INT_STATUS);
490 imask = ~RD4(sc, ZY7_DEVCFG_INT_MASK);
524 pl_done = ((RD4(s
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/freebsd-10.1-release/sys/dev/ffec/
H A Dif_ffec.c209 RD4(struct ffec_softc *sc, bus_size_t off) function
295 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII)
321 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK;
372 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED;
373 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE |
375 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN;
495 ((RD4(sc, FEC_MIBC_REG) & FEC_MIBC_IDLE) == 0))
501 ifp->if_ipackets += RD4(sc, FEC_RMON_R_PACKETS);
502 ifp->if_imcasts += RD4(sc, FEC_RMON_R_MC_PKT);
503 ifp->if_ierrors += RD4(s
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/freebsd-10.1-release/sys/arm/freescale/
H A Dfsl_ocotp.c99 RD4(struct ocotp_softc *sc, bus_size_t off) function
172 return (RD4(ocotp_sc, off));
/freebsd-10.1-release/sys/dev/sdhci/
H A Dsdhci.c63 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) macro
125 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
129 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
131 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
137 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
139 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
143 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT));
156 if (!(RD4(slo
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/freebsd-10.1-release/sys/arm/ti/
H A Dti_sdhci.c138 RD4(struct ti_sdhci_softc *sc, bus_size_t off) function
156 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
179 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
199 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
208 val32 = RD4(sc, off);
242 val32 = RD4(sc, off & ~3);
269 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
292 val32 = RD4(sc, off & ~3);
/freebsd-10.1-release/sys/arm/xscale/ixp425/
H A Dixp425_wdog.c54 RD4(struct ixpwdog_softc *sc, bus_size_t off) function
/freebsd-10.1-release/sys/dev/cadence/
H A Dif_cgem.c138 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro
167 uint32_t low = RD4(sc, CGEM_SPEC_ADDR_LOW(i));
168 uint32_t high = RD4(sc, CGEM_SPEC_ADDR_HI(i)) & 0xffff;
242 net_cfg = RD4(sc, CGEM_NET_CFG);
718 net_cfg = RD4(sc, CGEM_NET_CFG);
770 istatus = RD4(sc, CGEM_INTR_STAT);
778 RD4(sc, CGEM_RX_STAT));
1019 RD4(sc, CGEM_DMA_CFG) |
1028 RD4(sc, CGEM_DMA_CFG) &
1038 RD4(s
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