| /freebsd-10.1-release/contrib/llvm/lib/MC/ |
| H A D | MCCodeGenInfo.cpp | 19 CodeGenOpt::Level OL) {
22 OptLevel = OL;
18 InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10.1-release/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcTargetMachine.cpp | 32 CodeGenOpt::Level OL,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
91 CodeGenOpt::Level OL)
92 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
103 CodeGenOpt::Level OL)
104 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
85 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
97 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| H A D | SparcTargetMachine.h | 41 CodeGenOpt::Level OL, bool is64bit);
76 CodeGenOpt::Level OL);
88 CodeGenOpt::Level OL);
|
| /freebsd-10.1-release/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430TargetMachine.cpp | 33 CodeGenOpt::Level OL)
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| H A D | MSP430TargetMachine.h | 44 CodeGenOpt::Level OL);
|
| /freebsd-10.1-release/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 69 CodeGenOpt::Level OL, bool is64bit)
70 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
83 CodeGenOpt::Level OL)
84 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
91 CodeGenOpt::Level OL)
92 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
66 NVPTXTargetMachine( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
80 NVPTXTargetMachine32( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
88 NVPTXTargetMachine64( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| H A D | NVPTXTargetMachine.h | 104 CodeGenOpt::Level OL);
113 CodeGenOpt::Level OL);
|
| /freebsd-10.1-release/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetMachine.cpp | 77 CodeGenOpt::Level OL,
79 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
98 CodeGenOpt::Level OL)
99 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
108 CodeGenOpt::Level OL)
109 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
73 PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
94 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
104 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| H A D | PPCTargetMachine.h | 44 CodeGenOpt::Level OL, bool is64Bit);
84 CodeGenOpt::Level OL);
95 CodeGenOpt::Level OL);
|
| /freebsd-10.1-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86TargetMachine.cpp | 37 CodeGenOpt::Level OL)
38 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
61 CodeGenOpt::Level OL)
62 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
82 CodeGenOpt::Level OL,
84 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
33 X86_32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
57 X86_64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
78 X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
|
| H A D | X86TargetMachine.h | 41 CodeGenOpt::Level OL,
90 CodeGenOpt::Level OL);
119 CodeGenOpt::Level OL);
|
| /freebsd-10.1-release/contrib/llvm/include/llvm/MC/ |
| H A D | MCCodeGenInfo.h | 38 CodeGenOpt::Level OL = CodeGenOpt::Default);
|
| /freebsd-10.1-release/contrib/llvm/lib/Target/CppBackend/ |
| H A D | CPPTargetMachine.h | 28 CodeGenOpt::Level OL)
25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /freebsd-10.1-release/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetMachine.cpp | 33 CodeGenOpt::Level OL)
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
29 AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| H A D | AArch64TargetMachine.h | 39 CodeGenOpt::Level OL);
|
| /freebsd-10.1-release/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCTargetDesc.cpp | 71 CodeGenOpt::Level OL) {
75 X->InitMCCodeGenInfo(Reloc::Static, CM, OL);
69 createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10.1-release/contrib/llvm/lib/Target/MSP430/MCTargetDesc/ |
| H A D | MSP430MCTargetDesc.cpp | 55 CodeGenOpt::Level OL) {
57 X->InitMCCodeGenInfo(RM, CM, OL);
53 createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10.1-release/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTargetMachine.cpp | 27 CodeGenOpt::Level OL)
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
22 SystemZTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /freebsd-10.1-release/contrib/llvm/lib/Target/XCore/ |
| H A D | XCoreTargetMachine.cpp | 27 CodeGenOpt::Level OL)
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| H A D | XCoreTargetMachine.h | 38 CodeGenOpt::Level OL);
|
| /freebsd-10.1-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMTargetMachine.h | 45 CodeGenOpt::Level OL);
80 CodeGenOpt::Level OL);
118 CodeGenOpt::Level OL);
|
| /freebsd-10.1-release/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsTargetMachine.h | 54 CodeGenOpt::Level OL,
109 CodeGenOpt::Level OL);
120 CodeGenOpt::Level OL);
|
| /freebsd-10.1-release/contrib/llvm/lib/Target/Sparc/MCTargetDesc/ |
| H A D | SparcMCTargetDesc.cpp | 87 CodeGenOpt::Level OL) {
98 X->InitMCCodeGenInfo(RM, CM, OL);
104 CodeGenOpt::Level OL) {
119 X->InitMCCodeGenInfo(RM, CM, OL);
85 createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
102 createSparcV9MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /freebsd-10.1-release/contrib/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| H A D | NVPTXMCTargetDesc.cpp | 55 StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) {
57 X->InitMCCodeGenInfo(RM, CM, OL);
54 createNVPTXMCCodeGenInfo( StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /freebsd-10.1-release/contrib/llvm/lib/Target/R600/MCTargetDesc/ |
| H A D | AMDGPUMCTargetDesc.cpp | 59 CodeGenOpt::Level OL) {
61 X->InitMCCodeGenInfo(RM, CM, OL);
57 createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|