Searched refs:AR_PHY_PLL_CTL_44 (Results 1 - 6 of 6) sorted by relevance

/freebsd-10.1-release/sys/dev/ath/ath_hal/ar5211/
H A Dar5211phy.h45 #define AR_PHY_PLL_CTL_44 0x19 /* 44 MHz for 11b channels and FPGA */ macro
H A Dar5211_attach.c256 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44);
H A Dar5211_reset.c606 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44);
/freebsd-10.1-release/sys/dev/ath/ath_hal/ar5212/
H A Dar5212phy.h142 #define AR_PHY_PLL_CTL_44 0xab /* 44 MHz for 11b, 11g */ macro
H A Dar5212_reset.c905 phyPLL = AR_PHY_PLL_CTL_44;
/freebsd-10.1-release/sys/dev/ath/ath_hal/ar5312/
H A Dar5312_reset.c679 phyPLL = AR_PHY_PLL_CTL_44;

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