1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2006 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17204644Srpaulo * $FreeBSD$ 18185377Ssam */ 19185377Ssam#ifndef _DEV_ATH_AR5211PHY_H 20185377Ssam#define _DEV_ATH_AR5211PHY_H 21185377Ssam 22185377Ssam/* 23185377Ssam * Definitions for the PHY on the Atheros AR5211/5311 chipset. 24185377Ssam */ 25185377Ssam 26185377Ssam/* PHY registers */ 27185377Ssam#define AR_PHY_BASE 0x9800 /* PHY registers base address */ 28185377Ssam#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 29185377Ssam 30185377Ssam#define AR_PHY_TURBO 0x9804 /* PHY frame control register */ 31185377Ssam#define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */ 32185377Ssam#define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */ 33185377Ssam 34185377Ssam#define AR_PHY_CHIP_ID 0x9818 /* PHY chip revision ID */ 35185377Ssam 36185377Ssam#define AR_PHY_ACTIVE 0x981C /* PHY activation register */ 37185377Ssam#define AR_PHY_ACTIVE_EN 0x00000001 /* Activate PHY chips */ 38185377Ssam#define AR_PHY_ACTIVE_DIS 0x00000000 /* Deactivate PHY chips */ 39185377Ssam 40185377Ssam#define AR_PHY_AGC_CONTROL 0x9860 /* PHY chip calibration and noise floor setting */ 41185377Ssam#define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* Perform PHY chip internal calibration */ 42185377Ssam#define AR_PHY_AGC_CONTROL_NF 0x00000002 /* Perform PHY chip noise-floor calculation */ 43185377Ssam 44185377Ssam#define AR_PHY_PLL_CTL 0x987c /* PLL control register */ 45185377Ssam#define AR_PHY_PLL_CTL_44 0x19 /* 44 MHz for 11b channels and FPGA */ 46185377Ssam#define AR_PHY_PLL_CTL_40 0x18 /* 40 MHz */ 47185377Ssam#define AR_PHY_PLL_CTL_20 0x13 /* 20 MHz half rate 11a for emulation */ 48185377Ssam 49185377Ssam 50185377Ssam#define AR_PHY_RX_DELAY 0x9914 /* PHY analog_power_on_time, in 100ns increments */ 51185377Ssam#define AR_PHY_RX_DELAY_M 0x00003FFF /* Mask for delay from active assertion (wake up) */ 52185377Ssam /* to enable_receiver */ 53185377Ssam 54185377Ssam#define AR_PHY_TIMING_CTRL4 0x9920 /* PHY */ 55185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_M 0x0000001F /* Mask for kcos_theta-1 for q correction */ 56185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_M 0x000007E0 /* Mask for sin_theta for i correction */ 57185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 /* Shift for sin_theta for i correction */ 58185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x00000800 /* enable IQ correction */ 59185377Ssam#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_M 0x0000F000 /* Mask for max number of samples (logarithmic) */ 60185377Ssam#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */ 61185377Ssam#define AR_PHY_TIMING_CTRL4_DO_IQCAL 0x00010000 /* perform IQ calibration */ 62185377Ssam 63185377Ssam#define AR_PHY_PAPD_PROBE 0x9930 64185377Ssam#define AR_PHY_PAPD_PROBE_POWERTX 0x00007E00 65185377Ssam#define AR_PHY_PAPD_PROBE_POWERTX_S 9 66185377Ssam#define AR_PHY_PAPD_PROBE_NEXT_TX 0x00008000 /* command to take next reading */ 67185377Ssam#define AR_PHY_PAPD_PROBE_GAINF 0xFE000000 68185377Ssam#define AR_PHY_PAPD_PROBE_GAINF_S 25 69185377Ssam 70185377Ssam#define AR_PHY_POWER_TX_RATE1 0x9934 71185377Ssam#define AR_PHY_POWER_TX_RATE2 0x9938 72185377Ssam#define AR_PHY_POWER_TX_RATE_MAX 0x993c 73185377Ssam 74185377Ssam#define AR_PHY_FRAME_CTL 0x9944 75185377Ssam#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038 76185377Ssam#define AR_PHY_FRAME_CTL_TX_CLIP_S 3 77185377Ssam#define AR_PHY_FRAME_CTL_ERR_SERV 0x20000000 78185377Ssam#define AR_PHY_FRAME_CTL_ERR_SERV_S 29 79185377Ssam 80185377Ssam#define AR_PHY_RADAR_0 0x9954 /* PHY radar detection settings */ 81185377Ssam#define AR_PHY_RADAR_0_ENA 0x00000001 /* Enable radar detection */ 82185377Ssam 83185377Ssam#define AR_PHY_IQCAL_RES_PWR_MEAS_I 0x9c10 /*PHY IQ calibration results - power measurement for I */ 84185377Ssam#define AR_PHY_IQCAL_RES_PWR_MEAS_Q 0x9c14 /*PHY IQ calibration results - power measurement for Q */ 85185377Ssam#define AR_PHY_IQCAL_RES_IQ_CORR_MEAS 0x9c18 /*PHY IQ calibration results - IQ correlation measurement */ 86185377Ssam#define AR_PHY_CURRENT_RSSI 0x9c1c /* rssi of current frame being received */ 87185377Ssam 88185377Ssam#define AR5211_PHY_MODE 0xA200 /* Mode register */ 89185377Ssam#define AR5211_PHY_MODE_OFDM 0x0 /* bit 0 = 0 for OFDM */ 90185377Ssam#define AR5211_PHY_MODE_CCK 0x1 /* bit 0 = 1 for CCK */ 91185377Ssam#define AR5211_PHY_MODE_RF5GHZ 0x0 /* bit 1 = 0 for 5 GHz */ 92185377Ssam#define AR5211_PHY_MODE_RF2GHZ 0x2 /* bit 1 = 1 for 2.4 GHz */ 93185377Ssam 94185377Ssam#endif /* _DEV_ATH_AR5211PHY_H */ 95