/freebsd-10.0-release/sys/arm/arm/ |
H A D | cpufunc_asm_arm8.S | 46 mcr p15, 0, r2, c15, c0, 0 /* Write clock register */ 53 mcr p15, 0, r1, c15, c0, 0 /* Write clock register */ 58 mcr p15, 0, r2, c15, c0, 0 /* Write clock register */ 77 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */ 80 mcr p15, 0, r0, c2, c0, 0 83 mcr p15, 0, r0, c8, c7, 0 86 mcr p15, 0, r0, c7, c7, 0 100 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ 105 mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */ 113 mcr p1 [all...] |
H A D | cpufunc_asm_arm11.S | 53 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 55 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 56 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 64 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 65 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 66 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 71 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 72 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 90 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 91 mcr p1 [all...] |
H A D | cpufunc_asm_armv4.S | 47 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ 52 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */ 57 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */ 62 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 70 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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H A D | cpufunc_asm_armv6.S | 53 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 54 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D cache */ 56 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 58 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 60 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 74 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 85 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 86 mcr p15, 0, r0, c7, c10, 0 /* Clean D cache */ 87 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 96 mcr p1 [all...] |
H A D | cpufunc_asm_arm11x6.S | 69 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */ 83 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 84 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 85 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 86 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 104 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \ 105 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */ 109 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \ 113 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */ 123 mcr p1 [all...] |
H A D | cpufunc_asm_fa526.S | 43 mcr p15, 0, r1, c7, c14, 0 /* clean and invalidate D$ */ 44 mcr p15, 0, r1, c7, c5, 0 /* invalidate I$ */ 45 mcr p15, 0, r1, c7, c5, 6 /* invalidate BTB */ 46 mcr p15, 0, r1, c7, c10, 4 /* drain write and fill buffer */ 48 mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */ 51 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLB */ 63 mcr p15, 0, r0, c8, c7, 1 /* flush Utlb single entry */ 71 mcr p15, 0, r0, c8, c5, 1 /* flush Itlb single entry */ 79 mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt*/ 85 mcr p1 [all...] |
H A D | cpufunc_asm_sa1.S | 67 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */ 68 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */ 71 mcr p15, 0, r0, c2, c0, 0 74 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */ 77 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */ 95 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 96 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */ 104 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */ 109 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */ 114 mcr p1 [all...] |
H A D | cpufunc_asm_arm10.S | 49 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 51 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 59 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 60 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 65 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 88 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ 89 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 93 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 104 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 113 mcr p1 [all...] |
H A D | cpufunc_asm_pj4b.S | 46 mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */ 50 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 51 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 62 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */ 63 mcr p15, 0, r0, c7, c10, 0 /* Clean (don't invalidate) DCache */ 64 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 73 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 86 mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4413 */ 88 mcr p15, 0, r0, c7, c6, 1 92 mcr p1 [all...] |
H A D | cpufunc_asm_arm7tdmi.S | 54 mcr p15, 0, r1, c2, c0, 0 70 mcr p15, 0, r0, c8, c7, 0 75 mcr p15, 0, r0, c8, c7, 1 85 mcr p15, 0, r0, c7, c7, 0
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H A D | cpufunc_asm_sa11x0.S | 89 mcr p15, 0, r0, c15, c2, 2 /* disable clock switching */ 91 mcr p15, 0, r0, c15, c8, 2 /* wait for interrupt */ 93 mcr p15, 0, r0, c15, c1, 2 /* re-enable clock switching */ 113 mcr p15, 0, r0, c2, c0, 0 116 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */ 125 mcr p15, 0, r0, c9, c0, 0 /* drain read buffer */
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H A D | cpufunc_asm_xscale.S | 148 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */ 149 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */ 156 mcr p15, 0, r0, c2, c0, 0 159 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */ 162 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */ 179 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 180 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 188 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */ 193 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */ 198 mcr p1 [all...] |
H A D | cpufunc_asm_armv5.S | 50 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 52 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 76 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ 77 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 81 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 92 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 101 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */ 105 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */ 108 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 126 mcr p1 [all...] |
H A D | cpufunc_asm_xscale_c3.S | 147 mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */ 159 mcr p15, 0, r3, c7, c14, 2 /* clean and invalidate */ 168 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 185 1: mcr p15, 0, r0, c7, c14, 1 /* clean/invalidate L1 D cache entry */ 187 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ 194 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 207 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ 208 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ 215 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 228 1: mcr p1 [all...] |
H A D | cpufunc_asm_armv5_ec.S | 60 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */ 63 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 65 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 67 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 87 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ 88 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 92 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 103 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 110 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 128 mcr p1 [all...] |
H A D | cpufunc_asm_ixp12x0.S | 55 mcr p15, 0, r0, c2, c0, 0 58 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */ 67 mcr p15, 0, r0, c9, c0, 0 /* drain read buffer */
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H A D | cpufunc_asm_armv7.S | 72 mcr p15, 0, r0, c2, c0, 0 /* Translation Table Base Register 0 (TTBR0) */ 74 mcr p15, 0, r0, c8, c3, 0 /* invalidate I+D TLBs Inner Shareable*/ 76 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 86 mcr p15, 0, r0, c8, c3, 0 /* flush I+D tlb */ 87 mcr p15, 0, r0, c7, c1, 6 /* flush BTB */ 89 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ 90 mcr p15, 0, r0, c7, c5, 6 /* flush BTB */ 101 mcr p15, 0, r0, c8, c3, 1 /* flush D tlb single entry Inner Shareable*/ 102 mcr p15, 0, r0, c7, c1, 6 /* flush BTB Inner Shareable */ 104 mcr p1 [all...] |
H A D | cpufunc_asm.S | 108 mcr p15, 0, r0, c1, c0, 0 114 mcr p15, 0, r0, c3, c0, 0 182 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 184 mcr p15, 0, r1, c9, c2, 0 /* Enable data cache lock mode */ 186 mcr p15, 0, r0, c7, c2, 5 /* Allocate the cache line */ 187 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 190 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 191 mcr p15, 0, r1, c9, c2, 0 /* Disable data cache lock mode */
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H A D | cpufunc_asm_arm9.S | 48 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 50 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 58 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 59 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 82 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ 83 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 97 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 106 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */ 127 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 144 mcr p1 [all...] |
H A D | cpufunc_asm_sheeva.S | 49 mcr p15, 0, r1, c7, c5, 0 /* Invalidate ICache */ 53 mcr p15, 1, r1, c15, c9, 0 /* Clean L2 */ 54 mcr p15, 1, r1, c15, c11, 0 /* Invalidate L2 */ 59 mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */ 61 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 63 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 92 mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */ 93 mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */ 105 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 135 mcr p1 [all...] |
H A D | locore.S | 140 mcr p15, 0, r2, c1, c0, 0 170 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 171 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 175 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ 180 mcr p15, 0, r0, c3, c0, 0 194 mcr p15, 0, r0, c1, c0, 0 320 mcr p15, 0, r0, c7, c7, 0 365 mcr p15, 0, r2, c1, c0, 0 381 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 382 mcr p1 [all...] |
/freebsd-10.0-release/sys/dev/uart/ |
H A D | uart_dev_ns8250.h | 39 uint8_t mcr; member in struct:ns8250_softc
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/freebsd-10.0-release/usr.sbin/bhyve/ |
H A D | uart_emul.c | 103 uint8_t mcr; /* Modem control register (R/W) */ member in struct:uart_softc 315 if ((sc->mcr & MCR_LOOPBACK) != 0) { 353 if (sc->mcr & MCR_LOOPBACK) { 397 sc->mcr = value & 0x1F; 400 if (sc->mcr & MCR_LOOPBACK) { 405 if (sc->mcr & MCR_RTS) 407 if (sc->mcr & MCR_DTR) 409 if (sc->mcr & MCR_OUT1) 411 if (sc->mcr & MCR_OUT2) 507 reg = sc->mcr; [all...] |
/freebsd-10.0-release/sys/dev/vte/ |
H A D | if_vte.c | 1232 uint16_t mcr; local 1237 mcr = CSR_READ_2(sc, VTE_MCR0); 1238 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 1240 mcr |= MCR0_FULL_DUPLEX; 1243 mcr |= MCR0_FC_ENB; 1251 mcr |= MCR0_FC_ENB; 1254 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1587 uint16_t mcr; local 1590 mcr = CSR_READ_2(sc, VTE_MCR1); 1591 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESE 1807 uint16_t mcr; local 1834 uint16_t mcr; local 1947 uint16_t mchash[4], mcr; local [all...] |
/freebsd-10.0-release/sys/dev/ubsec/ |
H A D | ubsec.c | 646 struct ubsec_mcr *mcr; local 655 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 656 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 1777 struct ubsec_mcr *mcr; local 1789 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1792 mcr->mcr_pkts = htole16(1); 1793 mcr->mcr_flags = 0; 1794 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1795 mcr->mcr_ipktbuf.pb_addr = mcr 2147 struct ubsec_mcr *mcr; local 2349 struct ubsec_mcr *mcr; local 2547 struct ubsec_mcr *mcr; local 2763 ubsec_dump_mcr(struct ubsec_mcr *mcr) argument [all...] |