arm/arm/cpufunc_asm_sheeva.S

49 	mcr	p15, 0, r1, c7, c5, 0	/* Invalidate ICache */
53 	mcr	p15, 1, r1, c15, c9, 0	/* Clean L2 */
54 	mcr	p15, 1, r1, c15, c11, 0	/* Invalidate L2 */
59 	mcr	p15, 0, r1, c7, c10, 4	/* drain the write buffer */
61 	mcr	p15, 0, r0, c2, c0, 0	/* load new TTB */
63 	mcr	p15, 0, r0, c8, c7, 0	/* invalidate I+D TLBs */
92 	mcr	p15, 5, r0, c15, c15, 0	/* Clean and inv zone start address */
93 	mcr	p15, 5, r2, c15, c15, 1	/* Clean and inv zone end address */
105 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
135 	mcr	p15, 5, r0, c15, c15, 0	/* Clean and inv zone start address */
136 	mcr	p15, 5, r2, c15, c15, 1	/* Clean and inv zone end address */
144 	mcr	p15, 0, r0, c7, c5, 1
157 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
187 	mcr	p15, 5, r0, c15, c14, 0	/* Inv zone start address */
188 	mcr	p15, 5, r2, c15, c14, 1	/* Inv zone end address */
200 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
230 	mcr	p15, 5, r0, c15, c13, 0	/* Clean zone start address */
231 	mcr	p15, 5, r2, c15, c13, 1	/* Clean zone end address */
243 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
273 	mcr	p15, 1, r0, c15, c9, 4	/* Clean L2 zone start address */
274 	mcr	p15, 1, r2, c15, c9, 5	/* Clean L2 zone end address */
275 	mcr	p15, 1, r0, c15, c11, 4	/* Inv L2 zone start address */
276 	mcr	p15, 1, r2, c15, c11, 5	/* Inv L2 zone end address */
288 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
318 	mcr	p15, 1, r0, c15, c11, 4	/* Inv L2 zone start address */
319 	mcr	p15, 1, r2, c15, c11, 5	/* Inv L2 zone end address */
331 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
361 	mcr	p15, 1, r0, c15, c9, 4	/* Clean L2 zone start address */
362 	mcr	p15, 1, r2, c15, c9, 5	/* Clean L2 zone end address */
374 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
386 	mcr	p15, 1, r0, c15, c9, 0	/* Clean L2 */
387 	mcr	p15, 1, r0, c15, c11, 0	/* Invalidate L2 */
391 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
416 	mcr	p15, 0, r0, c7, c10, 4	/* Drain write buffer */
417 	mcr	p15, 0, r0, c7, c0, 4	/* Wait for interrupt */