/freebsd-10.0-release/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/ |
H A D | tst.signedkeyspos.d | 98 @i64["cat", (long long)-2] = sum(-2); 99 @i64["bear", (long long)-2] = sum(-22); 100 @i64["dog", (long long)-2] = sum(-222); 101 @i64["cat", (long long)-1] = sum(-1); 102 @i64["bear", (long long)-1] = sum(-11); 103 @i64["dog", (long long)-1] = sum(-111); 104 @i64["cat", (long long)0] = sum(0); 105 @i64["bear", (long long)0] = sum(10); 106 @i64["dog", (long long)0] = sum(100); 107 @i64["ca [all...] |
H A D | tst.signedkeys.d | 113 @i64[(long long)-2] = sum(-2); 114 @i64[(long long)-1] = sum(-1); 115 @i64[(long long)0] = sum(0); 116 @i64[(long long)1] = sum(1); 117 @i64[(long long)2] = sum(2);
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/freebsd-10.0-release/crypto/heimdal/lib/roken/ |
H A D | gettimeofday.c | 52 ull -= 116444736000000000i64; 53 ull /= 10i64; /* ull is now in microseconds */ 55 tp->tv_usec = (ull % 1000000i64); 56 tp->tv_sec = (ull / 1000000i64);
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/freebsd-10.0-release/sys/boot/ficl/ |
H A D | math64.h | 58 void i64Push(FICL_STACK *pStack, DPINT i64); 75 #define i64Extend(i64) (i64).hi = ((i64).lo < 0) ? -1L : 0 76 #define m64CastIU(i64) (*(DPUNS *)(&(i64)))
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H A D | math64.c | 216 void i64Push(FICL_STACK *pStack, DPINT i64) argument 218 stackPushINT(pStack, i64.lo); 219 stackPushINT(pStack, i64.hi);
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/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonVarargsCallingConvention.h | 39 (MVT(MVT::i64).getSizeInBits() / 8))) { 63 if (LocVT == MVT::i64 || 119 if (LocVT == MVT::i64 ||
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H A D | HexagonISelLowering.cpp | 121 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 160 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 235 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 262 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 607 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 653 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) { 861 } else if (RegVT == MVT::i64) { 1050 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); 1087 setOperationAction(ISD::SDIV, MVT::i64, Expand); 1089 setOperationAction(ISD::SREM, MVT::i64, Expan [all...] |
H A D | HexagonCallingConvLower.cpp | 108 addLoc(CCValAssign::getReg(0, MVT::i64, Reg, MVT::i64,
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/freebsd-10.0-release/crypto/openssl/crypto/modes/ |
H A D | modes_lcl.h | 12 typedef __int64 i64; typedef 16 typedef long i64; typedef 20 typedef long long i64; typedef
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/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 79 /// i64. 81 return CurDAG->getTargetConstant(Imm, MVT::i64); 310 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { 356 // Don't even go down this path for i64, since different logic will be 514 } else if (LHS.getValueType() == MVT::i64) { 520 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, 524 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, 537 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS, 539 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor, 546 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LH [all...] |
H A D | PPCISelLowering.cpp | 103 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 108 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 125 setOperationAction(ISD::SREM, MVT::i64, Expand); 126 setOperationAction(ISD::UREM, MVT::i64, Expand); 131 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 132 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 135 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 136 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 194 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 195 setOperationAction(ISD::CTTZ , MVT::i64 , Expan [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 238 case MVT::i64: 267 case MVT::i64: 297 case MVT::i64: 320 case MVT::i64: 349 case MVT::i64: 372 case MVT::i64: 479 case MVT::i64: 533 case MVT::i64: 588 case MVT::i64: 635 case MVT::i64 [all...] |
/freebsd-10.0-release/crypto/openssl/crypto/sha/asm/ |
H A D | sha512-armv4.pl | 470 vadd.i64 $T1,$K,$h 476 vadd.i64 $T1,$t0 478 vadd.i64 $T1,$Ch 484 vadd.i64 $T1,@X[$i%16] 491 vadd.i64 $h,$T1 492 vadd.i64 $d,$T1 493 vadd.i64 $h,$Maj 519 vadd.i64 @X[$i%8],$s1 526 vadd.i64 @X[$i%8],$s0 530 vadd.i64 [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 311 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 }, 312 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 }, 313 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 }, 314 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 } 343 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 }, 344 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 }, 345 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 10 }, 346 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 10 } 360 // i16 -> i64 requires two dependent operations. 361 { ISD::SIGN_EXTEND, MVT::i64, MV [all...] |
/freebsd-10.0-release/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/typedef/ |
H A D | tst.TypedefDataAssign.d | 87 new_int64 i64;
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/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 64 UImm12 = CurDAG->getTargetConstant(CN->getZExtValue() / MemSize, MVT::i64); 234 MVT::i64, MVT::i32, MVT::Other, 235 CurDAG->getTargetConstant(0, MVT::i64), 294 assert((DestType == MVT::i64 || DestType == MVT::i32) 308 MemType = MVT::i64; 356 FixedPos = CurDAG->getTargetConstant(TestedBit, MVT::i64); 375 else if (VT == MVT::i64) 498 assert((Ty == MVT::i32 || Ty == MVT::i64) && "unexpected type");
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H A D | AArch64ISelLowering.cpp | 54 addRegisterClass(MVT::i64, &AArch64::GPR64RegClass); 74 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 79 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 80 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 85 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 90 setOperationAction(ISD::SELECT, MVT::i64, Custom); 95 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 102 setOperationAction(ISD::SETCC, MVT::i64, Custom); 108 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 115 setOperationAction(ISD::BlockAddress, MVT::i64, Custo [all...] |
/freebsd-10.0-release/contrib/libarchive/libarchive/ |
H A D | archive_private.h | 145 # define ARCHIVE_LITERAL_LL(x) x##i64
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/freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 105 AVT = MVT::i64; 151 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 152 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : 223 AVT = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
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/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 37 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass); 84 setOperationAction(ISD::MULHS, MVT::i64, Custom); 85 setOperationAction(ISD::MULHU, MVT::i64, Custom); 86 setOperationAction(ISD::MUL, MVT::i64, Custom); 89 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); 90 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); 94 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); 95 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); 117 case MVT::i64: 536 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, L [all...] |
H A D | MipsSEISelDAGToDAG.cpp | 349 Mips::ZERO_64, MVT::i64); 380 MVT::i64); 386 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd); 389 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, 390 CurDAG->getRegister(Mips::ZERO_64, MVT::i64), 396 MVT::i64); 397 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
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H A D | MipsISelLowering.cpp | 260 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 261 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 262 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 263 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 264 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 265 setOperationAction(ISD::SELECT, MVT::i64, Custom); 266 setOperationAction(ISD::LOAD, MVT::i64, Custom); 267 setOperationAction(ISD::STORE, MVT::i64, Custom); 278 setOperationAction(ISD::ADD, MVT::i64, Custom); 284 setOperationAction(ISD::SDIV, MVT::i64, Expan [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/R600/ |
H A D | AMDILISelLowering.cpp | 49 (int)MVT::i64, 66 (int)MVT::i64 112 if (VT != MVT::i64 && VT != MVT::v2i64) { 162 setOperationAction(ISD::MULHU, MVT::i64, Expand); 164 setOperationAction(ISD::MULHS, MVT::i64, Expand); 168 setOperationAction(ISD::Constant , MVT::i64 , Legal); 299 if (OVT.getScalarType() == MVT::i64) { 316 if (OVT.getScalarType() == MVT::i64) { 369 return EVT(MVT::i64); 371 return EVT(MVT::getVectorVT(MVT::i64, vEl [all...] |
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 419 if (RetVT == MVT::i64) 430 if (RetVT == MVT::i64) 437 if (RetVT == MVT::i64) 444 if (RetVT == MVT::i64) 451 if (RetVT == MVT::i64) 469 if (RetVT == MVT::i64) 480 if (RetVT == MVT::i64) 487 if (RetVT == MVT::i64) 494 if (RetVT == MVT::i64) 501 if (RetVT == MVT::i64) [all...] |
/freebsd-10.0-release/sys/contrib/octeon-sdk/ |
H A D | cvmx-fau.h | 256 uint64_t i64; member in union:__anon6870 259 result.i64 = cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value));
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