Lines Matching refs:i64
103 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
108 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
125 setOperationAction(ISD::SREM, MVT::i64, Expand);
126 setOperationAction(ISD::UREM, MVT::i64, Expand);
131 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
132 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
135 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
136 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
194 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
195 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
196 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
197 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
201 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
204 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
209 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
213 setOperationAction(ISD::SELECT, MVT::i64, Expand);
238 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
244 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
245 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
265 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
266 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
267 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
268 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
269 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
285 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
287 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
289 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
291 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
296 setOperationAction(ISD::VAARG, MVT::i64, Custom);
307 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
327 // They also have instructions for converting between i64 and fp.
328 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
329 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
330 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
331 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
332 // This is just the low 32 bits of a (signed) fp->i64 conversion.
333 // We cannot do this with Promote because i64 is not a legal type.
346 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
347 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
348 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
349 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
359 // 64-bit PowerPC implementations can support i64 types directly
360 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
362 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
364 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
365 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
366 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
368 // 32-bit PowerPC wants to expand i64 shifts itself.
508 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
513 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
514 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
1292 if (VT != MVT::i64) {
1308 // sext i32 to i64 when addr mode is r+i.
1309 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1383 return DAG.getNode(PPCISD::TOC_ENTRY, CP->getDebugLoc(), MVT::i64, GA,
1384 DAG.getRegister(PPC::X2, MVT::i64));
1404 return DAG.getNode(PPCISD::TOC_ENTRY, JT->getDebugLoc(), MVT::i64, GA,
1405 DAG.getRegister(PPC::X2, MVT::i64));
1445 is64bit ? MVT::i64 : MVT::i32);
1455 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1465 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1476 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1488 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1499 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1525 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1526 DAG.getRegister(PPC::X2, MVT::i64));
1608 if (VT == MVT::i64) {
1667 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1670 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1712 bool isPPC64 = (PtrVT == MVT::i64);
1725 isPPC64 ? MVT::i64 : MVT::i32);
2168 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2169 // value to MVT::i64 and then truncate to the correct register size.
2175 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2178 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2377 case MVT::i64:
2380 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2383 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2384 // value to MVT::i64 and then truncate to the correct register size.
2514 bool isPPC64 = PtrVT == MVT::i64;
2577 case MVT::i64: // PPC64
2580 // Does MVT::i64 apply?
2712 case MVT::i64: // PPC64
2715 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2718 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2719 // value to MVT::i64 and then truncate to the correct register size.
3037 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3068 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3089 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3137 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3279 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3289 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3830 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3873 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3986 case MVT::i64:
4111 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4154 bool isPPC64 = PtrVT == MVT::i64;
4203 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4254 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4316 case MVT::i64:
4786 case MVT::i64:
4788 "i64 FP_TO_UINT is supported only with FPCVT");
4848 if (Op.getOperand(0).getValueType() == MVT::i64) {
4870 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4871 SINT, DAG.getConstant(2047, MVT::i64));
4872 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4873 Round, DAG.getConstant(2047, MVT::i64));
4874 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4875 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4876 Round, DAG.getConstant(-2048, MVT::i64));
4886 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4888 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4889 Cond, DAG.getConstant(1, MVT::i64));
4891 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4893 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4941 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5796 if (VT == MVT::i64) {
6050 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6170 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6174 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6177 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6178 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6191 if (PVT == MVT::i64) {
6203 if (PVT == MVT::i64) {
6215 if (PVT == MVT::i64) {
6230 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6240 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6241 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6923 // type must be i64.
6924 if (N->getOperand(0).getValueType() == MVT::i64 &&
6985 N->getOperand(1).getValueType() == MVT::i64))) {
7009 N->getValueType(0) == MVT::i64))) {
7020 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
7021 MVT::i64 : MVT::i32, MVT::Other),
7279 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7283 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7289 if (VT == MVT::f64 || VT == MVT::i64)
7442 isPPC64? MVT::i64 : MVT::i32);
7461 bool isPPC64 = PtrVT == MVT::i64;
7508 return MVT::i64;