Searched refs:getSubReg (Results 1 - 25 of 52) sorted by relevance

123

/freebsd-10.0-release/contrib/llvm/lib/MC/
H A DMCRegisterInfo.cpp21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { function in class:MCRegisterInfo
/freebsd-10.0-release/contrib/llvm/lib/Target/R600/
H A DR600ExpandSpecialInstrs.cpp174 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg);
235 Src0 = TRI.getSubReg(Src0, SubRegIndex);
236 Src1 = TRI.getSubReg(Src1, SubRegIndex);
241 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
242 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
250 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
H A DSIInstrInfo.cpp161 get(Opcode), RI.getSubReg(DestReg, SubIdx));
163 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp183 if (RCI.getSubReg() == Idx)
222 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
231 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
241 *BestPreA = IA.getSubReg();
242 *BestPreB = IB.getSubReg();
H A DCalcSpillWeights.cpp64 sub = mi->getOperand(0).getSubReg();
66 hsub = mi->getOperand(1).getSubReg();
68 sub = mi->getOperand(1).getSubReg();
70 hsub = mi->getOperand(0).getSubReg();
H A DOptimizePHIs.cpp106 !SrcMI->getOperand(0).getSubReg() &&
107 !SrcMI->getOperand(1).getSubReg() &&
H A DTargetInstrInfo.cpp138 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
139 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
140 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
316 if (FoldOp.getSubReg() || LiveOp.getSubReg())
451 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
H A DVirtRegMap.cpp293 if (MO.getSubReg()) {
315 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
H A DExpandPostRAPseudos.cpp87 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
91 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
H A DRegAllocFast.cpp669 if (!MO.getSubReg()) {
675 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
706 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
744 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
895 CopyDstSub = MI->getOperand(0).getSubReg();
896 CopySrcSub = MI->getOperand(1).getSubReg();
928 if (MO.getSubReg() && MI->readsVirtualRegister(Reg))
H A DMachineInstr.cpp72 if (SubIdx && getSubReg())
73 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
81 if (getSubReg()) {
82 Reg = TRI.getSubReg(Reg, getSubReg());
83 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
178 getSubReg() == Other.getSubReg();
217 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
267 OS << PrintReg(getReg(), TRI, getSubReg());
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H A DRegisterCoalescer.cpp220 DstSub = MI->getOperand(0).getSubReg();
222 SrcSub = MI->getOperand(1).getSubReg();
225 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
228 SrcSub = MI->getOperand(2).getSubReg();
276 Dst = TRI.getSubReg(Dst, DstSub);
371 Dst = TRI.getSubReg(Dst, DstSub);
376 return TRI.getSubReg(DstReg, SrcSub) == Dst;
697 UseMI->getOperand(0).getSubReg())
763 if (DstOperand.getSubReg() && !DstOperand.isUndef())
1370 TRI->composeSubRegIndices(SubIdx, MO->getSubReg()));
[all...]
H A DPeepholeOptimizer.cpp206 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
429 if (!MI->getOperand(0).getSubReg() &&
/freebsd-10.0-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp43 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_high));
44 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_low));
257 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_high),
258 RI.getSubReg(SrcReg, SystemZ::subreg_high), KillSrc);
259 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_low),
260 RI.getSubReg(SrcReg, SystemZ::subreg_low), KillSrc);
/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp159 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
160 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
184 unsigned Lo = RegInfo.getSubReg(Src, Mips::sub_lo);
185 unsigned Hi = RegInfo.getSubReg(Src, Mips::sub_hi);
217 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
218 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
219 unsigned SrcLo = RegInfo.getSubReg(Src, Mips::sub_lo);
220 unsigned SrcHi = RegInfo.getSubReg(Src, Mips::sub_hi);
303 MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven));
304 MachineLocation SrcML1(RegInfo->getSubReg(Re
[all...]
H A DMipsSEInstrInfo.cpp375 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
390 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven))
392 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd))
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp354 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
355 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
356 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
357 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
359 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
360 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
361 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
362 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
365 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
366 D1 = TRI->getSubReg(Re
[all...]
H A DARMMCInstLower.cpp74 assert(!MO.getSubReg() && "Subregs should be eliminated!");
H A DThumb2ITBlockPass.cpp113 assert(MI->getOperand(0).getSubReg() == 0 &&
114 MI->getOperand(1).getSubReg() == 0 &&
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp259 unsigned getSubReg() const { function in class:__anon2395::CountValue
761 SR = Start->getSubReg();
764 SR = End->getSubReg();
779 DistSR = End->getSubReg();
789 SubIB.addReg(End->getReg(), 0, End->getSubReg())
790 .addReg(Start->getReg(), 0, Start->getSubReg());
793 .addReg(Start->getReg(), 0, Start->getSubReg());
795 SubIB.addReg(End->getReg(), 0, End->getSubReg())
1084 .addReg(TripCount->getReg(), 0, TripCount->getSubReg());
/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/
H A DMachineInstr.h666 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
678 getOperand(0).getSubReg() == getOperand(1).getSubReg();
H A DMachineOperand.h264 unsigned getSubReg() const { function in class:llvm::MachineOperand
328 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64MCInstLower.cpp106 assert(!MO.getSubReg() && "Subregs should be eliminated!");
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp728 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
730 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
1273 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1274 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1286 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1287 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1337 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1338 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1382 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1383 unsigned Reg1 = MRI.getSubReg(Re
[all...]
/freebsd-10.0-release/contrib/llvm/include/llvm/MC/
H A DMCRegisterInfo.h323 unsigned getSubReg(unsigned Reg, unsigned Idx) const;

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