/freebsd-10.0-release/contrib/llvm/include/llvm/MC/ |
H A D | MCInstrAnalysis.h | 32 return Info->get(Inst.getOpcode()).isBranch(); 36 return Info->get(Inst.getOpcode()).isConditionalBranch(); 40 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); 44 return Info->get(Inst.getOpcode()).isIndirectBranch(); 48 return Info->get(Inst.getOpcode()).isCall(); 52 return Info->get(Inst.getOpcode()).isReturn();
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/freebsd-10.0-release/contrib/llvm/lib/MC/ |
H A D | MCInstrAnalysis.cpp | 16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
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H A D | MCInst.cpp | 43 OS << "<MCInst " << getOpcode(); 54 OS << "<MCInst #" << getOpcode(); 58 OS << ' ' << Printer->getOpcodeName(getOpcode());
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/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCBranchSelector.cpp | 116 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm()) 118 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ || 119 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) && 158 if (I->getOpcode() == PPC::BCC) { 169 } else if (I->getOpcode() == PPC::BDNZ) { 171 } else if (I->getOpcode() == PPC::BDNZ8) { 173 } else if (I->getOpcode() == PPC::BDZ) { 175 } else if (I->getOpcode() [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonNewValueJump.cpp | 130 if (II->getOpcode() == TargetOpcode::KILL) 180 if (MII->getOpcode() == Hexagon::CALLv3) 194 if (MII->getOpcode() == TargetOpcode::KILL || 195 MII->getOpcode() == TargetOpcode::PHI || 196 MII->getOpcode() == TargetOpcode::COPY) 203 if (MII->getOpcode() == Hexagon::TFR_condset_rr || 204 MII->getOpcode() == Hexagon::TFR_condset_ii || 205 MII->getOpcode() == Hexagon::TFR_condset_ri || 206 MII->getOpcode() == Hexagon::TFR_condset_ir || 207 MII->getOpcode() [all...] |
H A D | HexagonRegisterInfo.cpp | 146 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) && 154 if (!TII.isValidOffset(MI.getOpcode(), Offset)) { 163 if ( (MI.getOpcode() == Hexagon::LDriw) || 164 (MI.getOpcode() == Hexagon::LDrid) || 165 (MI.getOpcode() == Hexagon::LDrih) || 166 (MI.getOpcode() == Hexagon::LDriuh) || 167 (MI.getOpcode() == Hexagon::LDrib) || 168 (MI.getOpcode() == Hexagon::LDriub) || 169 (MI.getOpcode() == Hexagon::LDriw_f) || 170 (MI.getOpcode() [all...] |
H A D | HexagonSplitTFRCondSets.cpp | 93 switch(MI->getOpcode()) { 101 if (MI->getOpcode() == Hexagon::TFR_condset_rr || 102 MI->getOpcode() == Hexagon::TFR_condset_rr_f) { 106 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) { 137 if (MI->getOpcode() == Hexagon::TFR_condset_ri ) { 142 } else if (MI->getOpcode() == Hexagon::TFR_condset_ri_f ) { 158 if (MI->getOpcode() == Hexagon::TFR_condset_ir ) { 163 } else if (MI->getOpcode() == Hexagon::TFR_condset_ir_f ) { 186 if (MI->getOpcode() == Hexagon::TFR_condset_ii ) { 195 } else if (MI->getOpcode() [all...] |
H A D | HexagonCFGOptimizer.cpp | 76 switch(MI->getOpcode()) { 113 int Opc = MI->getOpcode(); 165 if ((MI->getOpcode() == Hexagon::JMP_t) || 166 (MI->getOpcode() == Hexagon::JMP_f)) { 178 IsUnconditionalJump(LayoutSucc->front().getOpcode())) { 185 IsUnconditionalJump(JumpAroundTarget->back().getOpcode()) &&
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/freebsd-10.0-release/contrib/llvm/lib/Target/R600/ |
H A D | R600EmitClauseMarkers.cpp | 35 switch (MI->getOpcode()) { 49 TII->isCubeOp(MI->getOpcode()) || 50 TII->isReductionOp(MI->getOpcode())) 64 if (TII->isALUInstr(MI->getOpcode())) 66 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode())) 68 switch (MI->getOpcode()) { 83 switch (MI->getOpcode()) { 102 if (!TII->isALUInstr(MI->getOpcode())) 105 int SrcIdx = TII->getOperandIdx(MI->getOpcode(), OpTable[j][0]); 110 TII->getOperandIdx(MI->getOpcode(), OpTabl [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 80 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 81 Addr.getOpcode() == ISD::TargetGlobalAddress) 84 if (Addr.getOpcode() == ISD::ADD) { 99 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 104 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 116 if (Addr.getOpcode() == ISD::FrameIndex) return false; 117 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 118 Addr.getOpcode() == ISD::TargetGlobalAddress) 121 if (Addr.getOpcode() == ISD::ADD) { 125 if (Addr.getOperand(0).getOpcode() [all...] |
H A D | FPMover.cpp | 90 if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD || 91 MI->getOpcode() == SP::FpNEGD) { 95 if (DestDReg == SrcDReg && MI->getOpcode() == SP::FpMOVD) { 106 if (MI->getOpcode() == SP::FpMOVD) 108 else if (MI->getOpcode() == SP::FpNEGD) 110 else if (MI->getOpcode() == SP::FpABSD)
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/freebsd-10.0-release/contrib/llvm/include/llvm/IR/ |
H A D | Operator.h | 49 /// getOpcode - Return the opcode for this Instruction or ConstantExpr. 51 unsigned getOpcode() const { function in class:llvm::Operator 53 return I->getOpcode(); 54 return cast<ConstantExpr>(this)->getOpcode(); 57 /// getOpcode - If V is an Instruction or ConstantExpr, return its 60 static unsigned getOpcode(const Value *V) { function in class:llvm::Operator 62 return I->getOpcode(); 64 return CE->getOpcode(); 112 return I->getOpcode() == Instruction::Add || 113 I->getOpcode() [all...] |
H A D | Instruction.h | 82 /// getOpcode() returns a member of one of the enums like Instruction::Add. 83 unsigned getOpcode() const { return getValueID() - InstructionVal; } function in class:llvm::Instruction 85 const char *getOpcodeName() const { return getOpcodeName(getOpcode()); } 86 bool isTerminator() const { return isTerminator(getOpcode()); } 87 bool isBinaryOp() const { return isBinaryOp(getOpcode()); } 88 bool isShift() { return isShift(getOpcode()); } 89 bool isCast() const { return isCast(getOpcode()); } 109 return getOpcode() == Shl || getOpcode() == LShr; 114 return getOpcode() [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/MBlaze/ |
H A D | MBlazeISelDAGToDAG.cpp | 101 unsigned Opc = N->getOpcode(); 122 if (N.getOpcode() == ISD::FrameIndex) return false; 123 if (N.getOpcode() == ISD::TargetExternalSymbol || 124 N.getOpcode() == ISD::TargetGlobalAddress) 128 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) { 132 if (N.getOperand(0).getOpcode() == ISD::TargetJumpTable || 133 N.getOperand(1).getOpcode() == ISD::TargetJumpTable) 153 if (N.getOpcode() == ISD::ADD || N.getOpcode() [all...] |
H A D | MBlazeInstrInfo.cpp | 45 if (MI->getOpcode() == MBlaze::LWI) { 64 if (MI->getOpcode() == MBlaze::SWI) { 137 unsigned LastOpc = LastInst->getOpcode(); 146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); 162 if (MBlaze::isCondBranchOpcode(SecondLastInst->getOpcode()) && 163 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) { 165 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); 173 if (MBlaze::isUncondBranchOpcode(SecondLastInst->getOpcode()) && 174 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) { 223 if (!MBlaze::isUncondBranchOpcode(I->getOpcode()) [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 92 switch (MI.getOpcode()) { 136 if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS) 183 if (LastInst->getOpcode() == NVPTX::GOTO) { 186 } else if (LastInst->getOpcode() == NVPTX::CBranch) { 204 if (SecondLastInst->getOpcode() == NVPTX::CBranch && 205 LastInst->getOpcode() == NVPTX::GOTO) { 214 if (SecondLastInst->getOpcode() == NVPTX::GOTO && 215 LastInst->getOpcode() == NVPTX::GOTO) { 232 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() ! [all...] |
H A D | NVPTXutil.cpp | 22 if ((MI->getOpcode() != NVPTX::LD_i32_avar) && 23 (MI->getOpcode() != NVPTX::LD_i64_avar))
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/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGNodes.h | 145 inline unsigned getOpcode() const; 358 /// getOpcode - Return the SelectionDAG opcode value for this node. For 362 unsigned getOpcode() const { return (unsigned short)NodeType; } function in class:llvm::SDNode 776 inline unsigned SDValue::getOpcode() const { 777 return Node->getOpcode(); 977 return getOperand(getOpcode() == ISD::STORE ? 2 : 1); 984 return N->getOpcode() == ISD::LOAD || 985 N->getOpcode() == ISD::STORE || 986 N->getOpcode() == ISD::PREFETCH || 987 N->getOpcode() [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Analysis/ |
H A D | CostModel.cpp | 112 switch (I->getOpcode()) { 121 return TTI->getCFInstrCost(I->getOpcode()); 145 return TTI->getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, 151 return TTI->getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy); 156 return TTI->getCmpSelInstrCost(I->getOpcode(), ValTy); 161 return TTI->getMemoryOpCost(I->getOpcode(), ValTy, 167 return TTI->getMemoryOpCost(I->getOpcode(), I->getType(), 184 return TTI->getCastInstrCost(I->getOpcode(), I->getType(), SrcTy); 192 return TTI->getVectorInstrCost(I->getOpcode(), 201 return TTI->getVectorInstrCost(I->getOpcode(), [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineShifts.cpp | 106 switch (I->getOpcode()) { 201 switch (I->getOpcode()) { 314 bool isLeftShift = I.getOpcode() == Instruction::Shl; 319 if (I.getOpcode() != Instruction::AShr && 337 if (I.getOpcode() != Instruction::AShr) 346 if (BO->getOpcode() == Instruction::Mul && isLeftShift) 372 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName()); 386 if (I.getOpcode() == Instruction::Shl) 389 assert(I.getOpcode() == Instruction::LShr && "Unknown logical shift"); 408 switch (Op0BO->getOpcode()) { [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 58 int Opcode = MI->getOpcode(); 80 int Opcode = MI->getOpcode(); 209 if (IsBRU(LastInst->getOpcode())) { 214 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 235 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 241 && IsBRU(LastInst->getOpcode())) { 253 if (IsBRU(SecondLastInst->getOpcode()) && 254 IsBRU(LastInst->getOpcode())) { 263 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) { [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 26 unsigned Opcode = MCID.getOpcode(); 59 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && 60 (TII.canCauseFpMLxStall(MI->getOpcode()) ||
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/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsDirectObjLower.cpp | 36 switch (Inst.getOpcode()) { 54 int Opcode = InstIn.getOpcode();
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/freebsd-10.0-release/contrib/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | R600MCCodeEmitter.cpp | 107 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 108 if (MI.getOpcode() == AMDGPU::RETURN || 109 MI.getOpcode() == AMDGPU::FETCH_CLAUSE || 110 MI.getOpcode() == AMDGPU::ALU_CLAUSE || 111 MI.getOpcode() == AMDGPU::BUNDLE || 112 MI.getOpcode() == AMDGPU::KILL) { 123 unsigned Opcode = MI.getOpcode(); 221 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) {
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/freebsd-10.0-release/contrib/llvm/tools/clang/lib/StaticAnalyzer/Checkers/ |
H A D | PointerArithChecker.cpp | 36 if (B->getOpcode() != BO_Sub && B->getOpcode() != BO_Add)
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