Searched refs:getInstr (Results 1 - 16 of 16) sorted by relevance
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 38 MachineInstr *MI = SU->getInstr(); 80 MachineInstr *MI = SU->getInstr();
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/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonMachineScheduler.cpp | 30 if (SUnits[su].getInstr()->isCall()) 33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall) 44 if (!SU || !SU->getInstr()) 49 switch (SU->getInstr()->getOpcode()) { 51 if (!ResourcesModel->canReserveResources(SU->getInstr())) 101 switch (SU->getInstr()->getOpcode()) { 103 ResourcesModel->reserveResources(SU->getInstr()); 124 DEBUG(Packet[i]->getInstr()->dump()); 240 assert(SU->getInstr() && "Scheduled SUnit must have instr"); 272 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); [all...] |
H A D | HexagonVLIWPacketizer.cpp | 2280 if (PacketSU->getInstr()->getDesc().mayStore() || 2283 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME || 2284 PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME) 2380 MachineInstr* TempMI = TempSU->getInstr(); 2394 TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(), 2447 MachineInstr *PacketMI = PacketSU->getInstr(); 2687 MachineInstr *I = SUI->getInstr(); 2688 MachineInstr *J = SUJ->getInstr(); 2799 if (PacketSU->getInstr()->getDesc().isCall()) { 2811 if (PacketSU->getInstr() [all...] |
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/ |
H A D | ScheduleDAGInstrs.cpp | 242 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); 269 RegUse = UseSU->getInstr(); 271 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, 275 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, 288 const MachineInstr *MI = SU->getInstr(); 308 !DefSU->getInstr()->registerDefIsDead(*Alias))) { 314 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()); 369 const MachineInstr *MI = SU->getInstr(); 393 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()); 409 MachineInstr *MI = SU->getInstr(); [all...] |
H A D | SlotIndexes.cpp | 184 MachineInstr *SlotMI = ListI->getInstr(); 222 if (itr->getInstr() != 0) { 223 dbgs() << *itr->getInstr();
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H A D | MachineScheduler.cpp | 671 MachineInstr *MI = SU->getInstr(); 811 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI)) 826 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength) 857 if (!SU->getInstr()->mayLoad()) 901 MachineInstr *Branch = DAG->ExitSU.getInstr(); 907 if (!TII->shouldScheduleAdjacent(SU->getInstr(), Branch)) 970 MachineInstr *Copy = CopySU->getInstr(); 1096 if (!SU->getInstr()->isCopy()) 1407 RemainingMicroOps += SchedModel->getNumMicroOps(I->getInstr(), S [all...] |
H A D | DFAPacketizer.cpp | 170 MIToSUnit[SU->getInstr()] = SU;
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H A D | CriticalAntiDepBreaker.cpp | 425 MISUnitMap[SU->getInstr()] = SU; 446 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr(); 551 CriticalPathMI = CriticalPathSU->getInstr();
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H A D | AggressiveAntiDepBreaker.cpp | 720 MISUnitMap.insert(std::pair<MachineInstr *, const SUnit *>(SU->getInstr(), 739 CriticalPathMI = CriticalPathSU->getInstr(); 784 CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : 0;
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H A D | PostRASchedulerList.cpp | 755 BB->splice(RegionEnd, BB, SU->getInstr());
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/freebsd-10.0-release/contrib/llvm/lib/Target/R600/ |
H A D | R600MachineScheduler.cpp | 143 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), 144 E = SU->getInstr()->operands_end(); It != E; ++It) { 186 MachineInstr *MI = SU->getInstr(); 247 int Opcode = SU->getInstr()->getOpcode(); 296 InstructionsGroupCandidate.push_back(SU->getInstr()); 362 AssignSlot(UnslotedSU->getInstr(), Slot); 371 AssignSlot(UnslotedSU->getInstr(), Slot); 404 InstructionsGroupCandidate.push_back(SU->getInstr());
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H A D | R600Packetizer.cpp | 174 MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
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/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.cpp | 140 MachineInstr *MI = SU->getInstr(); 198 MachineInstr *MI = SU->getInstr();
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/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | SlotIndexes.h | 46 MachineInstr* getInstr() const { return mi; } function in class:llvm::IndexListEntry 417 return index.isValid() ? index.listEntry()->getInstr() : 0; 426 if (I->getInstr()) 609 assert(miEntry->getInstr() == mi && "Instruction indexes broken."); 624 assert(miEntry->getInstr() == mi &&
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H A D | ScheduleDAGInstrs.h | 162 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
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H A D | ScheduleDAG.h | 403 /// getInstr - Return the representative MachineInstr for this SUnit. 405 MachineInstr *getInstr() const { function in class:llvm::SUnit 584 if (SU->isInstr()) return &SU->getInstr()->getDesc();
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