Searched refs:clk (Results 1 - 25 of 50) sorted by relevance

12

/freebsd-10.0-release/contrib/ntp/kernel/
H A Dtty_clk.c5 #include "clk.h"
72 #define clk_bflush(clk) (ndflush(&((clk)->clkbuf), (clk)->clk_cc))
81 register struct clkdata *clk; local
90 for (clk = clk_data; clk < &clk_data[NCLK]; clk++)
91 if (!clk->inuse)
93 if (clk >
110 register struct clkdata *clk; local
132 register struct clkdata *clk; local
157 register struct clkdata *clk; local
304 register struct clkdata *clk; local
[all...]
/freebsd-10.0-release/sys/arm/at91/
H A Dat91sam9g20.c128 struct at91_pmc_clock *clk; local
131 clk = at91_pmc_clock_ref("udpck");
132 clk->pmc_mask = PMC_SCER_UDP_SAM9;
133 at91_pmc_clock_deref(clk);
136 clk = at91_pmc_clock_ref("uhpck");
137 clk->pmc_mask = PMC_SCER_UHP_SAM9;
138 at91_pmc_clock_deref(clk);
141 clk = at91_pmc_clock_ref("plla");
142 clk->pll_min_in = SAM9G20_PLL_A_MIN_IN_FREQ; /* 2 MHz */
143 clk
[all...]
H A Dat91sam9x5.c131 struct at91_pmc_clock *clk; local
134 clk = at91_pmc_clock_ref("udpck");
135 clk->pmc_mask = PMC_SCER_UDP_SAM9;
136 at91_pmc_clock_deref(clk);
139 clk = at91_pmc_clock_ref("uhpck");
140 clk->pmc_mask = PMC_SCER_UHP_SAM9;
141 at91_pmc_clock_deref(clk);
144 clk = at91_pmc_clock_ref("plla");
145 clk->pll_min_in = SAM9X25_PLL_A_MIN_IN_FREQ; /* 2 MHz */
146 clk
[all...]
H A Dat91sam9260.c154 struct at91_pmc_clock *clk; local
157 clk = at91_pmc_clock_ref("udpck");
158 clk->pmc_mask = PMC_SCER_UDP_SAM9;
159 at91_pmc_clock_deref(clk);
162 clk = at91_pmc_clock_ref("uhpck");
163 clk->pmc_mask = PMC_SCER_UHP_SAM9;
164 at91_pmc_clock_deref(clk);
167 clk = at91_pmc_clock_ref("plla");
168 clk->pll_min_in = SAM9260_PLL_A_MIN_IN_FREQ; /* 1 MHz */
169 clk
[all...]
H A Dat91rm9200.c154 struct at91_pmc_clock *clk; local
157 clk = at91_pmc_clock_ref("udpck");
158 clk->pmc_mask = PMC_SCER_UDP;
159 at91_pmc_clock_deref(clk);
162 clk = at91_pmc_clock_ref("uhpck");
163 clk->pmc_mask = PMC_SCER_UHP;
164 at91_pmc_clock_deref(clk);
167 clk = at91_pmc_clock_ref("plla");
168 clk->pll_min_in = RM9200_PLL_A_MIN_IN_FREQ; /* 1 MHz */
169 clk
[all...]
H A Dat91sam9g45.c131 struct at91_pmc_clock *clk; local
134 clk = at91_pmc_clock_ref("uhpck");
135 clk->pmc_mask = PMC_SCER_UHP_SAM9;
136 at91_pmc_clock_deref(clk);
139 clk = at91_pmc_clock_ref("plla");
140 clk->pll_min_in = SAM9G45_PLL_A_MIN_IN_FREQ; /* 2 MHz */
141 clk->pll_max_in = SAM9G45_PLL_A_MAX_IN_FREQ; /* 32 MHz */
142 clk->pll_min_out = SAM9G45_PLL_A_MIN_OUT_FREQ; /* 400 MHz */
143 clk->pll_max_out = SAM9G45_PLL_A_MAX_OUT_FREQ; /* 800 MHz */
144 clk
[all...]
H A Dat91_pmc.c225 at91_pmc_set_pllb_mode(struct at91_pmc_clock *clk, int on) argument
245 at91_pmc_set_upll_mode(struct at91_pmc_clock *clk, int on) argument
265 at91_pmc_set_sys_mode(struct at91_pmc_clock *clk, int on) argument
269 WR4(sc, on ? PMC_SCER : PMC_SCDR, clk->pmc_mask);
271 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) != clk->pmc_mask)
274 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) == clk->pmc_mask)
279 at91_pmc_set_periph_mode(struct at91_pmc_clock *clk, int on) argument
283 WR4(sc, on ? PMC_PCER : PMC_PCDR, clk
296 struct at91_pmc_clock *clk; local
336 struct at91_pmc_clock *clk, *alias_clk; local
365 at91_pmc_clock_deref(struct at91_pmc_clock *clk) argument
372 at91_pmc_clock_enable(struct at91_pmc_clock *clk) argument
385 at91_pmc_clock_disable(struct at91_pmc_clock *clk) argument
398 at91_pmc_pll_rate(struct at91_pmc_clock *clk, uint32_t reg) argument
422 at91_pmc_pll_calc(struct at91_pmc_clock *clk, uint32_t out_freq) argument
[all...]
H A Dat91_twi.c256 int clk; local
269 clk = TWI_SLOW_CLOCK;
273 clk = TWI_FAST_CLOCK;
279 clk = TWI_FASTEST_CLOCK;
282 sc->cwgr = TWI_CWGR_CKDIV(1) | TWI_CWGR_CHDIV(TWI_CWGR_DIV(clk)) |
283 TWI_CWGR_CLDIV(TWI_CWGR_DIV(clk));
H A Dif_macbvar.h130 struct at91_pmc_clock *clk; member in struct:macb_softc
/freebsd-10.0-release/contrib/ntp/libntp/
H A Dclocktypes.c111 register struct clktype *clk; local
113 for (clk = clktypes; clk->code != -1; clk++) {
114 if (num == clk->code)
115 return (clk->abbrev);
/freebsd-10.0-release/sys/arm/ti/
H A Dti_prcm.c74 * @clk: the ID of the clock device to get
86 ti_prcm_clk_dev(clk_ident_t clk) argument
96 if (clk_dev->id == clk) {
103 printf("ti_prcm: Failed to find clock device (%d)\n", clk);
109 * @clk: identifier for the module to enable, see ti_prcm.h for a list
126 ti_prcm_clk_valid(clk_ident_t clk) argument
130 if (ti_prcm_clk_dev(clk) == NULL)
139 * @clk: identifier for the module to enable, see ti_prcm.h for a list
156 ti_prcm_clk_enable(clk_ident_t clk) argument
165 clk_dev = ti_prcm_clk_dev(clk);
200 ti_prcm_clk_disable(clk_ident_t clk) argument
243 ti_prcm_clk_set_source(clk_ident_t clk, clk_src_t clksrc) argument
287 ti_prcm_clk_get_source_freq(clk_ident_t clk, unsigned int *freq) argument
[all...]
H A Dti_prcm.h197 int ti_prcm_clk_valid(clk_ident_t clk);
198 int ti_prcm_clk_enable(clk_ident_t clk);
199 int ti_prcm_clk_disable(clk_ident_t clk);
200 int ti_prcm_clk_accessible(clk_ident_t clk);
201 int ti_prcm_clk_disable_autoidle(clk_ident_t clk);
202 int ti_prcm_clk_set_source(clk_ident_t clk, clk_src_t clksrc);
203 int ti_prcm_clk_get_source_freq(clk_ident_t clk, unsigned int *freq);
H A Dti_i2c.c825 clk_ident_t clk; local
832 clk = I2C0_CLK + sc->device_id;
833 err = ti_prcm_clk_enable(clk);
974 clk_ident_t clk; local
1002 clk = I2C0_CLK + sc->device_id;
1003 ti_prcm_clk_disable(clk);
H A Dti_sdhci.c322 clk_ident_t clk; local
326 clk = MMC0_CLK + sc->mmchs_device_id;
327 if (ti_prcm_clk_enable(clk) != 0) {
333 if (ti_prcm_clk_get_source_freq(clk, &sc->baseclk_hz) != 0) {
/freebsd-10.0-release/sys/arm/ti/twl/
H A Dtwl_clks.c93 * Register offsets within a clk regulator register set
165 * @clk: the clock device we're reading from / writing to
173 twl_clks_read_1(struct twl_clks_softc *sc, struct twl_clk_entry *clk, argument
176 return (twl_read(sc->sc_pdev, clk->sub_dev, clk->reg_off + off, val, 1));
180 twl_clks_write_1(struct twl_clks_softc *sc, struct twl_clk_entry *clk, argument
183 return (twl_write(sc->sc_pdev, clk->sub_dev, clk->reg_off + off, &val, 1));
203 struct twl_clk_entry *clk; local
210 LIST_FOREACH(clk,
278 twl_clks_set_state(struct twl_clks_softc *sc, struct twl_clk_entry *clk, int enable) argument
362 struct twl_clk_entry *clk; local
393 struct twl_clk_entry *clk; local
638 struct twl_clk_entry *clk; local
[all...]
/freebsd-10.0-release/sys/kern/
H A Dkern_ffclock.c174 int clk, error; local
181 for (clk = 0; clk < NUM_SYSCLOCKS; clk++) {
182 sbuf_cat(s, sysclocks[clk]);
183 if (clk + 1 < NUM_SYSCLOCKS)
206 int clk, error; local
216 for (clk = 0; clk < NUM_SYSCLOCKS; clk
[all...]
/freebsd-10.0-release/sbin/routed/
H A Dmain.c73 struct timeval clk; variable in typeref:struct:timeval
126 gettimeofday(&clk, 0);
127 prev_clk = clk;
128 epoch = clk;
305 srandom((int)(clk.tv_sec ^ clk.tv_usec ^ mypid));
365 prev_clk = clk;
366 gettimeofday(&clk, 0);
367 if (prev_clk.tv_sec == clk.tv_sec
368 && prev_clk.tv_usec == clk
[all...]
/freebsd-10.0-release/sbin/sconfig/
H A Dsconfig.c584 int loop, dpll, nrzi, invclk, clk, higain, phony, use16, crc4; local
606 clk_valid = ioctl (fd, SERIAL_GETCLK, &clk) >= 0;
679 switch (clk) {
686 default: printf (" syn=%d", clk); break;
734 int higain, clk, keepalive, debug, port, dlci, invrclk, invtclk; local
868 clk = E1CLK_INTERNAL;
869 ioctl (fd, SERIAL_SETCLK, &clk);
871 clk = E1CLK_RECEIVE;
872 ioctl (fd, SERIAL_SETCLK, &clk);
874 clk
[all...]
/freebsd-10.0-release/sys/dev/cxgb/common/
H A Dcxgb_vsc7323.c197 int mode, clk, r; local
201 mode = clk = 1;
203 mode = 1, clk = 2;
205 mode = clk = 3;
212 0x91 | (clk << 1))) ||
214 0x90 | (clk << 1))) ||
/freebsd-10.0-release/sys/arm/freescale/imx/
H A Dimx51_ccm.c189 imx51_get_clock(enum imx51_clock clk) argument
204 switch (clk) {
208 return ccm_softc->pll_freq[clk-IMX51CLK_PLL1];
236 return 0; /* XXX PLL2 bypass clk */
241 return 0; /* XXX PLL3 bypass clk */
364 "clock %d: not supported yet\n", clk);
H A Dimx51_ccmreg.h149 #define CCMR_CCGR_MODULE(clk) ((clk) / CCMR_CCGR_NSOURCE)
/freebsd-10.0-release/sys/dev/usb/serial/
H A Dumcs.c693 uint8_t clk; local
696 if (umcs7840_calc_baudrate(t->c_ospeed, &divisor, &clk) || !divisor)
1037 uint8_t clk; local
1040 if (umcs7840_calc_baudrate(rate, &divisor, &clk)) {
1044 if (divisor == 0 || (clk & MCS7840_DEV_SPx_CLOCK_MASK) != clk) {
1048 DPRINTF("Port %d set speed: %d (%02x / %d)\n", portno, rate, clk, divisor);
1055 data |= clk;
1086 umcs7840_calc_baudrate(uint32_t rate, uint16_t *divisor, uint8_t *clk) argument
1097 *clk
[all...]
/freebsd-10.0-release/sys/mips/atheros/
H A Duart_dev_ar933x.c110 ar933x_uart_get_baud(unsigned int clk, unsigned int scale, argument
117 t = clk;
134 uint32_t clk; local
137 clk = bas->rclk;
148 tstep = tstep / clk;
153 diff = abs(ar933x_uart_get_baud(clk, tscale, tstep) - baud);
/freebsd-10.0-release/sys/dev/cx/
H A Dcxddk.h259 unsigned clk : 3; /* receive clock source */ member in struct:__anon7813
272 unsigned clk : 3; /* transmit clock source */ member in struct:__anon7814
406 void cx_clock (long hz, long ba, int *clk, int *div);
H A Dcxddk.c250 return (c->opt.tcor.clk == CLK_EXT) ? 0 : c->txbaud;
280 c->opt.rcor.clk = clock;
285 c->opt.rcor.clk = CLK_EXT;
292 c->opt.tcor.clk = clock;
302 c->opt.tcor.clk = CLK_EXT;
306 c->opt.rcor.clk = CLK_EXT;
759 c->opt.rcor.clk = clock;
765 c->opt.tcor.clk = clock;

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