| /freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 263 MBB.addLiveIn(SuperReg);
271 MBB.addLiveIn(Reg);
317 MBB.addLiveIn(SuperReg);
324 MBB.addLiveIn(Reg);
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| H A D | HexagonCFGOptimizer.cpp | 223 LayoutSucc->addLiveIn(NewLiveIn[i]);
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| /freebsd-10.0-release/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 130 MF.getRegInfo().addLiveIn(Mips::T9_64);
131 MBB.addLiveIn(Mips::T9_64);
158 MF.getRegInfo().addLiveIn(Mips::T9);
159 MBB.addLiveIn(Mips::T9);
193 MF.getRegInfo().addLiveIn(Mips::V0);
194 MBB.addLiveIn(Mips::V0);
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| H A D | Mips16FrameLowering.cpp | 122 EntryBlock->addLiveIn(Reg);
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| H A D | MipsSEFrameLowering.cpp | 327 MBB.addLiveIn(ehDataReg(I));
431 EntryBlock->addLiveIn(Reg);
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| /freebsd-10.0-release/contrib/llvm/lib/Target/XCore/ |
| H A D | XCoreFrameLowering.cpp | 126 MBB.addLiveIn(XCore::LR);
154 MBB.addLiveIn(XCore::LR);
171 MBB.addLiveIn(XCore::R10);
289 MBB.addLiveIn(it->getReg());
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| /freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430FrameLowering.cpp | 76 I->addLiveIn(MSP430::FPW);
198 MBB.addLiveIn(Reg);
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| /freebsd-10.0-release/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZFrameLowering.cpp | 111 MBB.addLiveIn(GPR64);
199 MBB.addLiveIn(Reg);
365 I->addLiveIn(SystemZ::R11D);
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| /freebsd-10.0-release/contrib/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 377 EntryMBB->addLiveIn(LiveIns[i].first);
381 EntryMBB->addLiveIn(LiveIns[i].first);
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| H A D | VirtRegMap.cpp | 257 LiveIn[i]->addLiveIn(PhysReg);
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| H A D | MachineBasicBlock.cpp | 346 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) { function in class:MachineBasicBlock
373 addLiveIn(PhysReg);
812 NMBB->addLiveIn(*I);
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| H A D | MachineFunction.cpp | 415 /// addLiveIn - Add the specified physical register as a live-in value and
417 unsigned MachineFunction::addLiveIn(unsigned PReg, function in class:MachineFunction
426 MRI.addLiveIn(PReg, VReg);
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| H A D | PrologEpilogInserter.cpp | 301 EntryBlock->addLiveIn(CSI[i].getReg());
376 MBB->addLiveIn(blockCSI[i].getReg());
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| H A D | BranchFolding.cpp | 387 NewMBB->addLiveIn(i);
1718 TBB->addLiveIn(Def);
1719 FBB->addLiveIn(Def);
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| /freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/ |
| H A D | MachineBasicBlock.h | 295 /// addLiveIn - Add the specified register as a live in. Note that it
297 void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); } function in class:llvm::MachineBasicBlock
302 unsigned addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC);
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| H A D | MachineFunction.h | 308 /// addLiveIn - Add the specified physical register as a live-in value and
310 unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
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| H A D | MachineRegisterInfo.h | 476 /// addLiveIn - Add the specified register as a live-in. Note that it
478 void addLiveIn(unsigned Reg, unsigned vreg = 0) { function in class:llvm::MachineRegisterInfo
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| /freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 805 I->addLiveIn(FramePtr);
1263 MBB.addLiveIn(Reg);
1283 MBB.addLiveIn(Reg);
1458 allocMBB->addLiveIn(*i);
1459 checkMBB->addLiveIn(*i);
1463 allocMBB->addLiveIn(X86::R10);
1700 stackCheckMBB->addLiveIn(*I);
1701 incStackMBB->addLiveIn(*I);
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| /freebsd-10.0-release/contrib/llvm/lib/Target/MBlaze/ |
| H A D | MBlazeInstrInfo.cpp | 293 RegInfo.addLiveIn(MBlaze::R20);
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| /freebsd-10.0-release/contrib/llvm/lib/Target/R600/ |
| H A D | AMDGPUIndirectAddressing.cpp | 135 (*Succ)->addLiveIn(Key->second);
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| H A D | SIISelLowering.cpp | 174 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
181 Reg = MF.addLiveIn(Reg, RC);
195 Reg = MF.addLiveIn(Reg, RC);
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| /freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 614 MBB.addLiveIn(Reg);
806 MBB.addLiveIn(SupReg);
824 MBB.addLiveIn(SupReg);
836 MBB.addLiveIn(SupReg);
845 MBB.addLiveIn(NextReg);
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| H A D | Thumb1FrameLowering.cpp | 359 MBB.addLiveIn(Reg);
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| /freebsd-10.0-release/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 368 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
383 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
394 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
506 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
556 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
627 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
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| /freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 2037 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2129 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2148 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2317 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2356 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2379 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2406 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2408 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2426 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2481 unsigned VReg = MF.addLiveIn(GP
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