Searched refs:Regs (Results 1 - 22 of 22) sorted by relevance

/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.h111 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { argument
113 if (!isAllocated(Regs[i]))
138 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { argument
139 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
144 unsigned Reg = Regs[FirstUnalloc];
150 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, argument
152 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
157 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/
H A DRegisterScavenging.h180 void setUsed(BitVector &Regs) { argument
181 RegsAvailable.reset(Regs);
183 void setUnused(BitVector &Regs) { argument
184 RegsAvailable |= Regs;
H A DCallingConvLower.h281 unsigned getFirstUnallocated(const uint16_t *Regs, unsigned NumRegs) const { argument
283 if (!isAllocated(Regs[i]))
308 unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) { argument
309 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
314 unsigned Reg = Regs[FirstUnalloc];
320 unsigned AllocateReg(const uint16_t *Regs, const uint16_t *ShadowRegs, argument
322 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
327 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
H A DRegisterPressure.h211 void addLiveRegs(ArrayRef<unsigned> Regs);
312 void increaseRegPressure(ArrayRef<unsigned> Regs);
313 void decreaseRegPressure(ArrayRef<unsigned> Regs);
/freebsd-10.0-release/contrib/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp57 const std::vector<CodeGenRegister*> &Regs, bool isCtor);
59 const std::vector<CodeGenRegister*> &Regs,
173 const CodeGenRegister::Set &Regs = RC.getMembers(); local
174 if (Regs.empty())
179 OS << " {" << (*Regs.begin())->getWeight(RegBank)
311 const std::vector<CodeGenRegister*> &Regs,
319 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
320 Record *Reg = Regs[i]->TheDef;
338 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
386 for (unsigned i = 0, e = Regs
310 EmitRegMappingTables(raw_ostream &OS, const std::vector<CodeGenRegister*> &Regs, bool isCtor) argument
436 EmitRegMapping(raw_ostream &OS, const std::vector<CodeGenRegister*> &Regs, bool isCtor) argument
704 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); local
1208 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); local
1295 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); local
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H A DCodeGenRegisters.cpp153 RegUnitIterator(const CodeGenRegister::Set &Regs): argument
154 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() {
981 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); local
982 std::sort(Regs.begin(), Regs.end(), LessRecord());
983 Registers.reserve(Regs.size());
985 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
986 getReg(Regs[i]);
1241 CodeGenRegister::Set Regs; member in struct:__anon3651::UberRegSet
1272 const CodeGenRegister::Set &Regs = RegClass->getMembers(); local
1874 computeCoveredRegisters(ArrayRef<Record*> Regs) argument
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H A DCodeGenTarget.cpp217 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); local
218 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
219 if (I == Regs.end())
H A DCodeGenRegisters.h644 // Compute the set of registers completely covered by the registers in Regs.
645 // The returned BitVector will have a bit set for each register in Regs,
647 // registers in Regs.
651 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
H A DAsmMatcherEmitter.cpp2135 const std::vector<CodeGenRegister*> &Regs =
2137 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2138 const CodeGenRegister *Reg = Regs[i];
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/
H A DRegisterPressure.cpp109 void RegPressureTracker::increaseRegPressure(ArrayRef<unsigned> Regs) { argument
110 for (unsigned I = 0, E = Regs.size(); I != E; ++I) {
111 if (TargetRegisterInfo::isVirtualRegister(Regs[I])) {
112 const TargetRegisterClass *RC = MRI->getRegClass(Regs[I]);
119 TRI->getRegUnitPressureSets(Regs[I]),
120 TRI->getRegUnitWeight(Regs[I]));
126 void RegPressureTracker::decreaseRegPressure(ArrayRef<unsigned> Regs) { argument
127 for (unsigned I = 0, E = Regs.size(); I != E; ++I) {
128 if (TargetRegisterInfo::isVirtualRegister(Regs[I])) {
129 const TargetRegisterClass *RC = MRI->getRegClass(Regs[
308 containsReg(ArrayRef<unsigned> Regs, unsigned Reg) argument
341 pushRegUnits(unsigned Reg, SmallVectorImpl<unsigned> &Regs) argument
371 addLiveRegs(ArrayRef<unsigned> Regs) argument
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H A DExecutionDepsFix.cpp575 SmallVector<LiveReg, 4> Regs; local
586 for (SmallVector<LiveReg, 4>::iterator i = Regs.begin(), e = Regs.end();
590 Regs.insert(i, LR);
594 Regs.push_back(LR);
600 while (!Regs.empty()) {
602 dv = Regs.pop_back_val().Value;
609 DomainValue *Latest = Regs.pop_back_val().Value;
H A DAggressiveAntiDepBreaker.h97 std::vector<unsigned> &Regs,
H A DAggressiveAntiDepBreaker.cpp70 std::vector<unsigned> &Regs,
75 Regs.push_back(Reg);
537 std::vector<unsigned> Regs;
538 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
539 assert(Regs.size() > 0 && "Empty register group!");
540 if (Regs.size() == 0)
550 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
551 unsigned Reg = Regs[i];
570 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
571 unsigned Reg = Regs[
68 GetGroupRegs( unsigned Group, std::vector<unsigned> &Regs, std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs) argument
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/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp590 SmallVector<std::pair<unsigned,bool>, 4> Regs; local
622 Regs.push_back(std::make_pair(Reg, isKill));
625 if (Regs.empty())
627 if (Regs.size() > 1 || StrOpc== 0) {
631 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
632 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
633 } else if (Regs.size() == 1) {
636 .addReg(Regs[0].first, getKillRegState(Regs[
660 SmallVector<unsigned, 4> Regs; local
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H A DARMLoadStoreOptimizer.cpp97 ArrayRef<std::pair<unsigned, bool> > Regs,
279 /// registers in Regs as the register operands that would be loaded / stored.
287 ArrayRef<std::pair<unsigned, bool> > Regs,
290 unsigned NumRegs = Regs.size();
320 NewBase = Regs[NumRegs-1].first;
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
354 | getKillRegState(Regs[i].second));
393 SmallVector<std::pair<unsigned, bool>, 8> Regs; local
400 Regs.push_back(std::make_pair(Reg, isKill));
416 Pred, PredReg, Scratch, dl, Regs, ImpDef
282 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument
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H A DThumb2SizeReduction.cpp214 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
215 if (*Regs == ARM::CPSR)
/freebsd-10.0-release/contrib/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp309 parseRegister(Register &Reg, char Prefix, const unsigned *Regs,
314 char Prefix, const unsigned *Regs,
320 const unsigned *Regs, SystemZOperand::RegisterKind RegKind,
443 // Regs maps asm register numbers to LLVM register numbers, with zero
448 const unsigned *Regs, bool IsAddress) {
451 if (Reg.Prefix != Prefix || Reg.Number > 15 || Regs[Reg.Number] == 0) {
459 Reg.Number = Regs[Reg.Number];
464 // 'f' for FPRs, etc. Regs maps asm register numbers to LLVM register numbers,
466 // register represented by Regs and IsAddress says whether the register is
470 char Prefix, const unsigned *Regs,
447 parseRegister(Register &Reg, char Prefix, const unsigned *Regs, bool IsAddress) argument
469 parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands, char Prefix, const unsigned *Regs, SystemZOperand::RegisterKind Kind, bool IsAddress) argument
486 parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands, const unsigned *Regs, SystemZOperand::RegisterKind RegKind, bool HasIndex) argument
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/freebsd-10.0-release/contrib/llvm/lib/Target/R600/
H A DSIISelLowering.cpp191 SmallVector<SDValue, 4> Regs; local
192 Regs.push_back(Val);
196 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
202 Regs.push_back(DAG.getUNDEF(VT));
205 Regs.data(), Regs.size()));
H A DR600InstrInfo.cpp612 std::vector<unsigned> Regs; local
618 return Regs;
623 Regs.push_back(SuperReg);
626 Regs.push_back(Reg);
629 return Regs;
/freebsd-10.0-release/contrib/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp814 SmallPtrSet<const SCEV *, 16> &Regs,
826 SmallPtrSet<const SCEV *, 16> &Regs,
830 SmallPtrSet<const SCEV *, 16> &Regs,
840 SmallPtrSet<const SCEV *, 16> &Regs,
862 if (!Regs.count(AR->getOperand(1))) {
863 RateRegister(AR->getOperand(1), Regs, L, SE, DT);
888 SmallPtrSet<const SCEV *, 16> &Regs,
896 if (Regs.insert(Reg)) {
897 RateRegister(Reg, Regs, L, SE, DT);
904 SmallPtrSet<const SCEV *, 16> &Regs,
839 RateRegister(const SCEV *Reg, SmallPtrSet<const SCEV *, 16> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT) argument
887 RatePrimaryRegister(const SCEV *Reg, SmallPtrSet<const SCEV *, 16> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT, SmallPtrSet<const SCEV *, 16> *LoserRegs) argument
903 RateFormula(const Formula &F, SmallPtrSet<const SCEV *, 16> &Regs, const DenseSet<const SCEV *> &VisitedRegs, const Loop *L, const SmallVectorImpl<int64_t> &Offsets, ScalarEvolution &SE, DominatorTree &DT, SmallPtrSet<const SCEV *, 16> *LoserRegs) argument
1160 SmallPtrSet<const SCEV *, 4> Regs; member in class:__anon2649::LSRUse
3663 SmallPtrSet<const SCEV *, 16> Regs; local
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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp598 /// Regs - This list holds the registers assigned to the values.
602 SmallVector<unsigned, 4> Regs; member in struct:__anon2224::RegsForValue
608 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
619 Regs.push_back(Reg + i);
639 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Par
5741 SmallVector<unsigned, 4> Regs; local
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/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2231 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, argument
2235 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2238 contains(Regs.front().first))
2243 I = Regs.begin(), E = Regs.end(); I != E; ++I)

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