Searched refs:Reg (Results 1 - 25 of 243) sorted by relevance

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/freebsd-10.0-release/contrib/llvm/lib/Target/Sparc/
H A DSparcMachineFunctionInfo.h38 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
44 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp41 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument
43 VRegInfo[Reg].first = RC;
47 MachineRegisterInfo::constrainRegClass(unsigned Reg, argument
50 const TargetRegisterClass *OldRC = getRegClass(Reg);
58 setRegClass(Reg, NewRC);
63 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { argument
65 const TargetRegisterClass *OldRC = getRegClass(Reg);
73 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
87 setRegClass(Reg, NewRC);
101 unsigned Reg local
112 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
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H A DMachineInstrBundle.cpp133 unsigned Reg = MO.getReg(); local
134 if (!Reg)
136 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
137 if (LocalDefSet.count(Reg)) {
141 KilledDefSet.insert(Reg);
143 if (ExternUseSet.insert(Reg)) {
144 ExternUses.push_back(Reg);
146 UndefUseSet.insert(Reg);
150 KilledUseSet.insert(Reg);
156 unsigned Reg local
187 unsigned Reg = LocalDefs[i]; local
197 unsigned Reg = ExternUses[i]; local
252 analyzeVirtReg(unsigned Reg, SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) argument
281 analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI) argument
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H A DAggressiveAntiDepBreaker.cpp60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { argument
61 unsigned Node = GroupNodeIndices[Reg];
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
75 Regs.push_back(Reg);
82 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) argument
106 IsLive(unsigned Reg) argument
160 unsigned Reg = *AI; local
173 unsigned Reg = *I; local
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H A DCriticalAntiDepBreaker.cpp66 unsigned Reg = *AI; local
67 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
68 KillIndices[Reg] = BBSize;
69 DefIndices[Reg] = ~0u;
81 unsigned Reg = *AI; local
82 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
83 KillIndices[Reg] = BBSize;
84 DefIndices[Reg] = ~0u;
100 for (unsigned Reg = 0; Reg !
172 unsigned Reg = MO.getReg(); local
235 unsigned Reg = MO.getReg(); local
266 unsigned Reg = MO.getReg(); local
579 unsigned Reg = MO.getReg(); local
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H A DDeadMachineInstructionElim.cpp69 unsigned Reg = MO.getReg(); local
70 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
72 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
75 if (!MRI->use_nodbg_empty(Reg))
127 unsigned Reg = MO.getReg(); local
128 if (!TargetRegisterInfo::isVirtualRegister(Reg))
131 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
155 unsigned Reg = MO.getReg(); local
156 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
174 unsigned Reg = MO.getReg(); local
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H A DLiveVariables.cpp182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { argument
183 VarInfo &VRInfo = getVarInfo(Reg);
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, argument
197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
219 if (TRI->isSubRegister(Reg, DefReg)) {
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { argument
232 MachineInstr *LastDef = PhysRegDef[Reg];
234 if (!LastDef && !PhysRegUse[Reg]) {
242 // All of the sub-registers must have been defined before the use of Reg!
244 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefReg
281 FindLastRefOrPartRef(unsigned Reg) argument
311 HandlePhysRegKill(unsigned Reg, MachineInstr *MI) argument
443 HandlePhysRegDef(unsigned Reg, MachineInstr *MI, SmallVector<unsigned, 4> &Defs) argument
489 unsigned Reg = Defs.back(); local
652 const unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
677 replaceKillInstruction(unsigned Reg, MachineInstr *OldMI, MachineInstr *NewMI) argument
690 unsigned Reg = MO.getReg(); local
715 isLiveIn(const MachineBasicBlock &MBB, unsigned Reg, MachineRegisterInfo &MRI) argument
733 isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) argument
814 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
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H A DAllocationOrder.h52 unsigned Reg = Order[Pos++]; local
53 if (!isHint(Reg))
54 return Reg;
H A DRegisterPressure.cpp49 void RegisterPressure::increase(unsigned Reg, const TargetRegisterInfo *TRI, argument
51 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
52 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
59 TRI->getRegUnitPressureSets(Reg),
60 TRI->getRegUnitWeight(Reg));
65 void RegisterPressure::decrease(unsigned Reg, const TargetRegisterInfo *TRI, argument
67 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
68 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
73 decreaseSetPressure(MaxSetPressure, TRI->getRegUnitPressureSets(Reg),
74 TRI->getRegUnitWeight(Reg));
308 containsReg(ArrayRef<unsigned> Regs, unsigned Reg) argument
341 pushRegUnits(unsigned Reg, SmallVectorImpl<unsigned> &Regs) argument
379 discoverLiveIn(unsigned Reg) argument
390 discoverLiveOut(unsigned Reg) argument
441 unsigned Reg = RegOpers.Defs[i]; local
450 unsigned Reg = RegOpers.Uses[i]; local
491 unsigned Reg = RegOpers.Uses[i]; local
516 unsigned Reg = RegOpers.Defs[i]; local
627 unsigned Reg = RegOpers.Defs[i]; local
633 unsigned Reg = RegOpers.Uses[i]; local
674 findUseBetween(unsigned Reg, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo *MRI, const LiveIntervals *LIS) argument
711 unsigned Reg = RegOpers.Uses[i]; local
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H A DRegisterScavenging.cpp33 void RegScavenger::setUsed(unsigned Reg) { argument
34 RegsAvailable.reset(Reg);
36 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
40 bool RegScavenger::isAliasUsed(unsigned Reg) const {
41 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
42 if (isUsed(*AI, *AI == Reg))
50 I->Reg = 0;
107 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) { argument
108 BV.set(Reg);
109 for (MCSubRegIterator SubRegs(Reg, TR
133 unsigned Reg = MO.getReg(); local
205 unsigned Reg = MO.getReg(); local
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/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.h74 bool isAllocated(unsigned Reg) const {
75 return UsedRegs[Reg/32] & (1 << (Reg&31));
121 unsigned AllocateReg(unsigned Reg) { argument
122 if (isAllocated(Reg)) return 0;
123 MarkAllocated(Reg);
124 return Reg;
128 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { argument
129 if (isAllocated(Reg)) return 0;
130 MarkAllocated(Reg);
144 unsigned Reg = Regs[FirstUnalloc]; local
157 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; local
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/freebsd-10.0-release/contrib/llvm/lib/MC/
H A DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument
20 for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { argument
31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
/freebsd-10.0-release/sys/contrib/dev/acpica/components/hardware/
H A Dhwregs.c77 * PARAMETERS: Reg - GAS register structure
91 ACPI_GENERIC_ADDRESS *Reg,
98 if (!Reg)
108 ACPI_MOVE_64_TO_64 (Address, &Reg->Address);
116 if ((Reg->SpaceId != ACPI_ADR_SPACE_SYSTEM_MEMORY) &&
117 (Reg->SpaceId != ACPI_ADR_SPACE_SYSTEM_IO))
120 "Unsupported address space: 0x%X", Reg->SpaceId));
126 if ((Reg->BitWidth != 8) &&
127 (Reg->BitWidth != 16) &&
128 (Reg
90 AcpiHwValidateRegister( ACPI_GENERIC_ADDRESS *Reg, UINT8 MaxBitWidth, UINT64 *Address) argument
170 AcpiHwRead( UINT32 *Value, ACPI_GENERIC_ADDRESS *Reg) argument
236 AcpiHwWrite( UINT32 Value, ACPI_GENERIC_ADDRESS *Reg) argument
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H A Dhwxface.c115 * Reg - GAS register structure
132 ACPI_GENERIC_ADDRESS *Reg)
151 Status = AcpiHwValidateRegister (Reg, 64, &Address);
161 if (Reg->SpaceId == ACPI_ADR_SPACE_SYSTEM_MEMORY)
164 Address, ReturnValue, Reg->BitWidth);
175 Width = Reg->BitWidth;
188 if (Reg->BitWidth == 64)
207 ACPI_FORMAT_UINT64 (*ReturnValue), Reg->BitWidth,
209 AcpiUtGetRegionName (Reg->SpaceId)));
222 * Reg
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/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/
H A DRegisterPressure.h42 /// \param Reg is either a virtual register number or register unit number.
43 void increase(unsigned Reg, const TargetRegisterInfo *TRI,
49 /// \param Reg is either a virtual register number or register unit number.
50 void decrease(unsigned Reg, const TargetRegisterInfo *TRI,
134 bool contains(unsigned Reg) { argument
135 if (TargetRegisterInfo::isVirtualRegister(Reg))
136 return VirtRegs.count(Reg);
137 return PhysRegs.count(Reg);
140 bool insert(unsigned Reg) { argument
141 if (TargetRegisterInfo::isVirtualRegister(Reg))
146 erase(unsigned Reg) argument
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H A DLiveVariables.h106 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
107 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
110 unsigned Reg,
150 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
165 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
170 MachineInstr *FindLastPartialDef(unsigned Reg,
281 isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) argument
299 isPHIJoin(unsigned Reg) argument
302 setPHIJoin(unsigned Reg) argument
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H A DRegisterScavenging.h45 ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(NULL) {}
52 unsigned Reg; member in struct:llvm::RegScavenger::ScavengedInfo
162 void setUsed(unsigned Reg);
165 bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
171 bool isUsed(unsigned Reg, bool CheckReserved = true) const { argument
172 return !RegsAvailable.test(Reg) || (CheckReserved && isReserved(Reg));
175 /// isAliasUsed - Is Reg or an alias currently in use?
176 bool isAliasUsed(unsigned Reg) cons
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H A DMachineRegisterInfo.h77 return MO->Contents.Reg.Next;
160 /// Verify the sanity of the use list for Reg.
161 void verifyUseList(unsigned Reg) const;
196 /// Reg are Debug instructions.
275 MachineInstr *getVRegDef(unsigned Reg) const;
280 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
286 void clearKillFlags(unsigned Reg) const;
303 const TargetRegisterClass *getRegClass(unsigned Reg) const {
304 return VRegInfo[Reg].first;
309 void setRegClass(unsigned Reg, cons
346 setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) argument
394 setPhysRegUsed(unsigned Reg) argument
407 setPhysRegUnused(unsigned Reg) argument
478 addLiveIn(unsigned Reg, unsigned vreg = 0) argument
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H A DCallingConvLower.h239 bool isAllocated(unsigned Reg) const {
240 return UsedRegs[Reg/32] & (1 << (Reg&31));
291 unsigned AllocateReg(unsigned Reg) { argument
292 if (isAllocated(Reg)) return 0;
293 MarkAllocated(Reg);
294 return Reg;
298 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { argument
299 if (isAllocated(Reg)) return 0;
300 MarkAllocated(Reg);
314 unsigned Reg = Regs[FirstUnalloc]; local
327 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; local
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H A DLiveIntervalAnalysis.h104 LiveInterval &getInterval(unsigned Reg) { argument
105 LiveInterval *LI = VirtRegIntervals[Reg];
110 const LiveInterval &getInterval(unsigned Reg) const {
111 return const_cast<LiveIntervals*>(this)->getInterval(Reg);
114 bool hasInterval(unsigned Reg) const {
115 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
119 LiveInterval &getOrCreateInterval(unsigned Reg) { argument
120 if (!hasInterval(Reg)) {
121 VirtRegIntervals.grow(Reg);
128 removeInterval(unsigned Reg) argument
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/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/
H A DMipsMachineFunction.h69 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
92 int getEhDataRegFI(unsigned Reg) const { return EhDataRegFI[Reg]; }
/freebsd-10.0-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZMachineFunctionInfo.h41 void setLowSavedGPR(unsigned Reg) { LowSavedGPR = Reg; } argument
46 void setHighSavedGPR(unsigned Reg) { HighSavedGPR = Reg; } argument
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp65 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
89 unsigned Reg = MI->getOperand(1).getReg(); local
90 if (TargetRegisterInfo::isPhysicalRegister(Reg))
94 MachineInstr *DefMI = MRI->getVRegDef(Reg);
99 Reg = DefMI->getOperand(1).getReg();
100 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
101 DefMI = MRI->getVRegDef(Reg);
105 Reg = DefMI->getOperand(2).getReg();
106 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
107 DefMI = MRI->getVRegDef(Reg);
117 unsigned Reg = MI->getOperand(0).getReg(); local
143 unsigned Reg = MI->getOperand(1).getReg(); local
184 hasRAWHazard(unsigned Reg, MachineInstr *MI) const argument
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/freebsd-10.0-release/contrib/llvm/include/llvm/MC/
H A DMCRegisterInfo.h71 bool contains(unsigned Reg) const {
72 unsigned InByte = Reg % 8;
73 unsigned Byte = Reg / 8;
323 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
326 /// Reg so its sub-register of index SubIdx is Reg.
327 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
423 /// MCSubRegIterator enumerates all sub-registers of Reg.
426 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
427 init(Reg, MCR
445 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, bool IncludeSelf) argument
481 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) argument
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/freebsd-10.0-release/contrib/llvm/lib/Target/R600/
H A DAMDGPUIndirectAddressing.cpp37 bool regHasExplicitDef(MachineRegisterInfo &MRI, unsigned Reg) const;
166 unsigned Reg = *LJ; local
167 if (RegisterAddressMap.find(Reg) == RegisterAddressMap.end()) {
171 if (RegisterAddressMap[Reg] == Address) {
172 PhiRegisters.push_back(Reg);
194 unsigned Reg = *RI; local
195 MachineInstr *DefInst = MRI.getVRegDef(Reg);
198 Phi.addReg(Reg);
200 MBB.removeLiveIn(Reg);
223 unsigned Reg local
252 unsigned Reg = LiveAddressRegisterMap[Address]; local
288 unsigned Reg = LiveAddressRegisterMap[Addr]; local
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