/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 36 if (getOpcode() < ISD::BUILTIN_OP_END) 54 case ISD::DELETED_NODE: return "<<Deleted Node!>>"; 56 case ISD::PREFETCH: return "Prefetch"; 57 case ISD::ATOMIC_FENCE: return "AtomicFence"; 58 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 59 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 60 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 61 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 62 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; 63 case ISD [all...] |
H A D | LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition 16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the 18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC; 22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR, 154 if (Op.getOpcode() == ISD::LOAD) { 156 ISD::LoadExtType ExtType = LD->getExtensionType(); 157 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) { 163 } else if (Op.getOpcode() == ISD::STORE) { 193 case ISD::ADD: 194 case ISD [all...] |
H A D | LegalizeIntegerTypes.cpp | 50 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; 51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; 54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 57 case ISD::CONVERT_RNDSAT: 59 case ISD::CTLZ_ZERO_UNDEF: 60 case ISD [all...] |
H A D | LegalizeVectorTypes.cpp | 49 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; 50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 51 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; 52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; 53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; 55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; 56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 58 case ISD [all...] |
H A D | LegalizeDAG.cpp | 273 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 286 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, 303 assert(ST->getAddressingMode() == ISD::UNINDEXED && 318 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); 359 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 361 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 371 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 383 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 400 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 407 Ptr = DAG.getNode(ISD [all...] |
H A D | TargetLowering.cpp | 104 ISD::CondCode &CCCode, 112 case ISD::SETEQ: 113 case ISD::SETOEQ: 117 case ISD::SETNE: 118 case ISD::SETUNE: 122 case ISD::SETGE: 123 case ISD::SETOGE: 127 case ISD::SETLT: 128 case ISD::SETOLT: 132 case ISD [all...] |
H A D | DAGCombiner.cpp | 159 ISD::NodeType ExtType); 257 SDValue N3, ISD::CondCode CC, 259 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 402 if (Op.getOpcode() == ISD::FNEG) return 2; 412 case ISD::ConstantFP: 416 case ISD::FADD: 422 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 432 case ISD::FSUB: 439 case ISD::FMUL: 440 case ISD [all...] |
H A D | SelectionDAG.cpp | 93 // ISD Namespace 98 bool ISD::isBuildVectorAllOnes(const SDNode *N) { 100 if (N->getOpcode() == ISD::BITCAST) 103 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 108 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 138 N->getOperand(i).getOpcode() != ISD::UNDEF) 146 bool ISD::isBuildVectorAllZeros(const SDNode *N) { 148 if (N->getOpcode() == ISD::BITCAST) 151 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 156 while (i != e && N->getOperand(i).getOpcode() == ISD [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 173 int ISD = TLI->InstructionOpcodeToISD(Opcode); local 174 assert(ISD && "Invalid opcode"); 179 { ISD::SHL, MVT::v4i32, 1 }, 180 { ISD::SRL, MVT::v4i32, 1 }, 181 { ISD::SRA, MVT::v4i32, 1 }, 182 { ISD::SHL, MVT::v8i32, 1 }, 183 { ISD::SRL, MVT::v8i32, 1 }, 184 { ISD::SRA, MVT::v8i32, 1 }, 185 { ISD::SHL, MVT::v2i64, 1 }, 186 { ISD 334 int ISD = TLI->InstructionOpcodeToISD(Opcode); local 440 int ISD = TLI->InstructionOpcodeToISD(Opcode); local [all...] |
/freebsd-10.0-release/contrib/llvm/include/llvm/Target/ |
H A D | CostTable.h | 23 int ISD; member in struct:llvm::CostTblEntry 31 unsigned len, int ISD, TypeTy Ty) { 33 if (Tbl[i].ISD == ISD && Tbl[i].Type == Ty) 43 int ISD; member in struct:llvm::TypeConversionCostTblEntry 52 unsigned len, int ISD, TypeTy Dst, TypeTy Src) { 54 if (Tbl[i].ISD == ISD && Tbl[i].Src == Src && Tbl[i].Dst == Dst) 30 CostTableLookup(const CostTblEntry<TypeTy> *Tbl, unsigned len, int ISD, TypeTy Ty) argument 51 ConvertCostTableLookup(const TypeConversionCostTblEntry<TypeTy> *Tbl, unsigned len, int ISD, TypeTy Dst, TypeTy Src) argument
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/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 181 int ISD = TLI->InstructionOpcodeToISD(Opcode); local 182 assert(ISD && "Invalid opcode"); 187 { ISD::FP_ROUND, MVT::v2f64, 2 }, 188 { ISD::FP_EXTEND, MVT::v2f32, 2 }, 189 { ISD::FP_EXTEND, MVT::v4f32, 4 } 192 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || 193 ISD == ISD::FP_EXTEND)) { 196 ISD, L 399 int ISD = TLI->InstructionOpcodeToISD(Opcode); local [all...] |
H A D | ARMSelectionDAGInfo.h | 26 case ISD::SHL: return ARM_AM::lsl; 27 case ISD::SRL: return ARM_AM::lsr; 28 case ISD::SRA: return ARM_AM::asr; 29 case ISD::ROTR: return ARM_AM::ror; 30 //case ISD::ROTL: // Only if imm -> turn into ROTR.
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/freebsd-10.0-release/contrib/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 37 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 41 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 42 setOperationAction(ISD::FEXP2, MVT::f32, Legal); 43 setOperationAction(ISD::FPOW, MVT::f32, Legal); 44 setOperationAction(ISD::FLOG2, MVT::f32, Legal); 45 setOperationAction(ISD::FABS, MVT::f32, Legal); 46 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 47 setOperationAction(ISD::FRINT, MVT::f32, Legal); 51 setOperationAction(ISD::STORE, MVT::f32, Promote); 52 AddPromotedToType(ISD [all...] |
H A D | AMDILISelLowering.cpp | 100 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); 101 setOperationAction(ISD::SUBE, VT, Expand); 102 setOperationAction(ISD::SUBC, VT, Expand); 103 setOperationAction(ISD::ADDE, VT, Expand); 104 setOperationAction(ISD::ADDC, VT, Expand); 105 setOperationAction(ISD::BRCOND, VT, Custom); 106 setOperationAction(ISD::BR_JT, VT, Expand); 107 setOperationAction(ISD::BRIND, VT, Expand); 109 setOperationAction(ISD::SREM, VT, Expand); 110 setOperationAction(ISD [all...] |
H A D | R600ISelLowering.cpp | 37 setOperationAction(ISD::FADD, MVT::v4f32, Expand); 38 setOperationAction(ISD::FMUL, MVT::v4f32, Expand); 39 setOperationAction(ISD::FDIV, MVT::v4f32, Expand); 40 setOperationAction(ISD::FSUB, MVT::v4f32, Expand); 42 setOperationAction(ISD::ADD, MVT::v4i32, Expand); 43 setOperationAction(ISD::AND, MVT::v4i32, Expand); 44 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand); 45 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand); 46 setOperationAction(ISD::MUL, MVT::v2i32, Expand); 47 setOperationAction(ISD [all...] |
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/ |
H A D | BasicTargetTransformInfo.cpp | 161 (TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 162 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 202 int ISD = TLI->InstructionOpcodeToISD(Opcode); local 203 assert(ISD && "Invalid opcode"); 212 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) { 222 if (!TLI->isOperationExpand(ISD, LT.second)) { 248 int ISD = TLI->InstructionOpcodeToISD(Opcode); local 249 assert(ISD && "Invalid opcode"); 272 if (TLI->isOperationLegalOrPromote(ISD, DstLT.second)) 283 if (!TLI->isOperationExpand(ISD, DstL 341 int ISD = TLI->InstructionOpcodeToISD(Opcode); local 393 unsigned ISD = 0; local [all...] |
H A D | Analysis.cpp | 146 /// getFCmpCondCode - Return the ISD condition code corresponding to 150 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { 152 case FCmpInst::FCMP_FALSE: return ISD::SETFALSE; 153 case FCmpInst::FCMP_OEQ: return ISD::SETOEQ; 154 case FCmpInst::FCMP_OGT: return ISD::SETOGT; 155 case FCmpInst::FCMP_OGE: return ISD::SETOGE; 156 case FCmpInst::FCMP_OLT: return ISD::SETOLT; 157 case FCmpInst::FCMP_OLE: return ISD::SETOLE; 158 case FCmpInst::FCMP_ONE: return ISD::SETONE; 159 case FCmpInst::FCMP_ORD: return ISD [all...] |
H A D | TargetLoweringBase.cpp | 591 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 592 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 593 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 594 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 595 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 596 CCs[RTLIB::UNE_F32] = ISD::SETNE; 597 CCs[RTLIB::UNE_F64] = ISD::SETNE; 598 CCs[RTLIB::UNE_F128] = ISD::SETNE; 599 CCs[RTLIB::OGE_F32] = ISD [all...] |
/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | Analysis.h | 68 /// getFCmpCondCode - Return the ISD condition code corresponding to 72 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred); 74 /// getFCmpCodeWithoutNaN - Given an ISD condition code comparing floats, 76 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC); 78 /// getICmpCondCode - Return the ISD condition code corresponding to 81 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
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H A D | SelectionDAGNodes.h | 62 namespace ISD { namespace in namespace:llvm 74 /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 79 /// and all operands of the specified node are ISD::UNDEF. 81 } // end llvm:ISD namespace 360 /// are the opcode values in the ISD and <target>ISD namespaces. For 365 /// \<target\>ISD namespace). 366 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; } 369 /// memory-referencing opcode (in the \<target\>ISD namespace and 372 return NodeType >= ISD 1791 namespace ISD { namespace in class:llvm::SDNode [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 54 ISD::ArgFlagsTy ArgFlags, CCState &State); 59 ISD::ArgFlagsTy ArgFlags, CCState &State); 64 ISD::ArgFlagsTy ArgFlags, CCState &State); 69 ISD::ArgFlagsTy ArgFlags, CCState &State); 74 ISD::ArgFlagsTy ArgFlags, CCState &State); 79 ISD::ArgFlagsTy ArgFlags, CCState &State); 84 ISD::ArgFlagsTy ArgFlags, CCState &State) { 133 ISD::ArgFlagsTy ArgFlags, CCState &State) { 171 ISD::ArgFlagsTy ArgFlags, CCState &State) { 189 ISD [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 113 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl); 126 if (N.getOpcode() == ISD::TargetConstant || 127 N.getOpcode() == ISD::TargetGlobalAddress) { 282 if (N->getOpcode() != ISD::Constant) 300 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 310 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { 368 if (Opcode == ISD::SHL) { 373 } else if (Opcode == ISD::SRL) { 380 } else if (Opcode == ISD::ROTL) { 418 if (Op0Opc == ISD [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 83 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 84 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); 95 setOperationAction(ISD::SRA, MVT::i8, Custom); 96 setOperationAction(ISD::SHL, MVT::i8, Custom); 97 setOperationAction(ISD [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 39 ISD::ArgFlagsTy &ArgFlags, CCState &State) 52 ISD::ArgFlagsTy &ArgFlags, CCState &State) 81 ISD::ArgFlagsTy &ArgFlags, CCState &State) { 120 ISD::ArgFlagsTy &ArgFlags, CCState &State) { 165 const SmallVectorImpl<ISD::OutputArg> &Outs, 176 const SmallVectorImpl<ISD::OutputArg> &Outs, 239 const SmallVectorImpl<ISD::OutputArg> &Outs, 268 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); 271 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); 274 OutVal = DAG.getNode(ISD [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/MBlaze/ |
H A D | MBlazeISelLowering.cpp | 40 ISD::ArgFlagsTy &ArgFlags, 68 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); 72 setOperationAction(ISD::FREM, MVT::f32, Expand); 73 setOperationAction(ISD::FMA, MVT::f32, Expand); 74 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Expand); 75 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Expand); 76 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 77 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 78 setOperationAction(ISD::FP_ROUND, MVT::f32, Expand); 79 setOperationAction(ISD [all...] |