Searched refs:ARM (Results 1 - 25 of 73) sorted by relevance

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/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp18 #include "ARM.h"
34 cl::desc("Verify machine code after expanding ARM pseudos"));
50 return "ARM pseudo instruction expansion pass";
131 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
132 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
133 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
134 { ARM
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H A DARMInstrInfo.cpp1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
15 #include "ARM.h"
38 NopInst.setOpcode(ARM::HINT);
43 NopInst.setOpcode(ARM::MOVr);
44 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
55 case ARM::LDR_PRE_IMM:
56 case ARM::LDR_PRE_REG:
57 case ARM
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H A DARMBaseInstrInfo.cpp1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
15 #include "ARM.h"
46 cl::desc("Enable ARM 2-addr to 3-addr conv"));
50 cl::desc("Widen ARM vmovs to vmovd when possible"));
69 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
70 { ARM::VMLSS, ARM
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H A DThumb2InstrInfo.cpp15 #include "ARM.h"
39 NopInst.setOpcode(ARM::tNOP);
80 if (MBBI->getOpcode() == ARM::t2IT) {
118 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
121 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
141 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
142 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
143 RC == &ARM
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H A DThumb2SizeReduction.cpp11 #include "ARM.h"
62 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
63 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
64 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
65 { ARM
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H A DARMAsmPrinter.cpp1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
17 #include "ARM.h"
236 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
237 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
242 unsigned SReg = Reg - ARM::S0;
263 } else if (Reg >= ARM
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H A DARMLoadStoreOptimizer.cpp1 //===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ------------===//
16 #include "ARM.h"
75 return "ARM load / store optimization pass";
140 case ARM::LDRi12:
144 case ARM_AM::ia: return ARM::LDMIA;
145 case ARM_AM::da: return ARM::LDMDA;
146 case ARM_AM::db: return ARM::LDMDB;
147 case ARM_AM::ib: return ARM::LDMIB;
149 case ARM::STRi12:
153 case ARM_AM::ia: return ARM
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H A DARMFrameLowering.cpp1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
33 cl::desc("Align ARM NEON spills in prolog and epilog"));
67 // stack frame. ARM (especially Thumb) has small immediate offset to
96 if (MI->getOpcode() == ARM::LDMIA_RET ||
97 MI->getOpcode() == ARM::t2LDMIA_RET ||
98 MI->getOpcode() == ARM::LDMIA_UPD ||
99 MI->getOpcode() == ARM::t2LDMIA_UPD ||
100 MI->getOpcode() == ARM::VLDMDIA_UPD) {
108 if ((MI->getOpcode() == ARM
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H A DARMRelocations.h1 //===-- ARMRelocations.h - ARM Code Relocations -----------------*- C++ -*-===//
10 // This file defines the ARM target-specific relocation types.
20 namespace ARM { namespace in namespace:llvm
38 // reloc_arm_machine_cp_entry - Relocation of a ARM machine constantpool
H A DThumb1InstrInfo.cpp15 #include "ARM.h"
30 NopInst.setOpcode(ARM::tMOVr);
31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
32 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
45 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
56 assert((RC == &ARM::tGPRRegClass ||
60 if (RC == &ARM::tGPRRegClass ||
73 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
84 assert((RC == &ARM
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H A DThumb1FrameLowering.cpp27 // stack frame. ARM (especially Thumb) has small immediate offset to
42 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
70 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
73 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
122 case ARM::R4:
123 case ARM::R5:
124 case ARM
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H A DARMBaseRegisterInfo.cpp1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
15 #include "ARM.h"
48 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), TII(tii), STI(sti),
49 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
50 BasePtr(ARM::R6) {
94 Reserved.set(ARM::SP);
95 Reserved.set(ARM
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H A DARMISelDAGToDAG.cpp1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
10 // This file defines an instruction selector for the ARM target.
15 #include "ARM.h"
52 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
79 return "ARM Instruction Selection";
202 /// ARM.
240 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
243 /// SelectCMOVOp - Select CMOV instructions for ARM.
418 /// least on current ARM implementation
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/freebsd-10.0-release/lib/clang/include/llvm/Config/
H A DAsmParsers.def3 LLVM_ASM_PARSER(ARM)
H A DAsmPrinters.def3 LLVM_ASM_PRINTER(ARM)
H A DDisassemblers.def3 LLVM_DISASSEMBLER(ARM)
H A DTargets.def3 LLVM_TARGET(ARM)
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
88 /// ARMDisassembler - ARM disassembler for all ARM platforms.
401 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
402 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
424 // VFP and NEON instructions, similarly, are shared between ARM
628 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
630 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
635 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
649 case ARM
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/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAsmBackend.cpp1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
54 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
57 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
61 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
154 case ARM::tBcc: return ARM::t2Bcc;
155 case ARM::tLDRpciASM: return ARM::t2LDRpci;
156 case ARM::tADR: return ARM
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H A DARMELFObjectWriter.cpp1 //===-- ARMELFObjectWriter.cpp - ARM ELF Writer ---------------------------===//
55 // In ARM, _MergedGlobals and other most symbols get emitted directly.
57 // This code is an approximation of what ARM/gcc does.
176 case ARM::fixup_arm_blx:
177 case ARM::fixup_arm_uncondbl:
187 case ARM::fixup_arm_condbl:
188 case ARM::fixup_arm_condbranch:
189 case ARM::fixup_arm_uncondbranch:
192 case ARM::fixup_t2_condbranch:
193 case ARM
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/freebsd-10.0-release/lib/clang/libllvmarmasmparser/
H A DMakefile7 SRCDIR= lib/Target/ARM/AsmParser
8 INCDIR= lib/Target/ARM
/freebsd-10.0-release/lib/clang/libllvmarmdisassembler/
H A DMakefile7 SRCDIR= lib/Target/ARM/Disassembler
8 INCDIR= lib/Target/ARM
/freebsd-10.0-release/lib/clang/libllvmarminfo/
H A DMakefile7 SRCDIR= lib/Target/ARM/TargetInfo
8 INCDIR= lib/Target/ARM
/freebsd-10.0-release/lib/clang/libllvmarminstprinter/
H A DMakefile7 SRCDIR= lib/Target/ARM/InstPrinter
8 INCDIR= lib/Target/ARM
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
125 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
128 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
131 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
134 return STI.getFeatureBits() & ARM::HasV6Ops;
137 return STI.getFeatureBits() & ARM::HasV7Ops;
140 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
144 return STI.getFeatureBits() & ARM::FeatureMClass;
260 // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
284 /// ARMOperand - Instances of this class represent a parsed ARM machin
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