Lines Matching refs:ARM
1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
125 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
128 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
131 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
134 return STI.getFeatureBits() & ARM::HasV6Ops;
137 return STI.getFeatureBits() & ARM::HasV7Ops;
140 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
144 return STI.getFeatureBits() & ARM::FeatureMClass;
260 // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
284 /// ARMOperand - Instances of this class represent a parsed ARM machine
372 /// Combined record for all forms of ARM address expressions.
927 if (Memory.BaseRegNum != ARM::PC)
1066 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1099 if (Memory.BaseRegNum == ARM::PC) return false;
1117 if (Memory.BaseRegNum == ARM::PC) return false;
1178 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1194 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1221 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1449 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
2235 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2237 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2514 .Case("r13", ARM::SP)
2515 .Case("r14", ARM::LR)
2516 .Case("r15", ARM::PC)
2517 .Case("ip", ARM::R12)
2519 .Case("a1", ARM::R0)
2520 .Case("a2", ARM::R1)
2521 .Case("a3", ARM::R2)
2522 .Case("a4", ARM::R3)
2523 .Case("v1", ARM::R4)
2524 .Case("v2", ARM::R5)
2525 .Case("v3", ARM::R6)
2526 .Case("v4", ARM::R7)
2527 .Case("v5", ARM::R8)
2528 .Case("v6", ARM::R9)
2529 .Case("v7", ARM::R10)
2530 .Case("v8", ARM::R11)
2531 .Case("sb", ARM::R9)
2532 .Case("sl", ARM::R10)
2533 .Case("fp", ARM::R11)
2858 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2862 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2863 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2864 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2865 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2866 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2867 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2868 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2869 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2877 case ARM::Q0: return ARM::D0;
2878 case ARM::Q1: return ARM::D2;
2879 case ARM::Q2: return ARM::D4;
2880 case ARM::Q3: return ARM::D6;
2881 case ARM::Q4: return ARM::D8;
2882 case ARM::Q5: return ARM::D10;
2883 case ARM::Q6: return ARM::D12;
2884 case ARM::Q7: return ARM::D14;
2885 case ARM::Q8: return ARM::D16;
2886 case ARM::Q9: return ARM::D18;
2887 case ARM::Q10: return ARM::D20;
2888 case ARM::Q11: return ARM::D22;
2889 case ARM::Q12: return ARM::D24;
2890 case ARM::Q13: return ARM::D26;
2891 case ARM::Q14: return ARM::D28;
2892 case ARM::Q15: return ARM::D30;
2916 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2922 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2923 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2924 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2925 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2926 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2927 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2946 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2975 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2984 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2997 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3013 // The ARM system instruction variants for LDM/STM have a '^' token here.
3087 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3107 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3114 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3115 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3119 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3120 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3152 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3182 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3189 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3228 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3293 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3294 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3295 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3306 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3307 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3308 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3434 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
4256 /// Parse an ARM memory expression, return false if successful else return true
4700 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4915 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4938 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5000 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5040 // First check for the ARM-specific .req directive.
5125 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5195 // table driven matcher doesn't fit well with the ARM instruction set.
5202 // ARM mode 'blx' need special handling, as the register operand version
5227 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5243 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5244 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5306 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5307 Inst.getOpcode() != ARM::BKPT) {
5333 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5334 Inst.getOpcode() != ARM::t2B)
5338 case ARM::LDRD:
5339 case ARM::LDRD_PRE:
5340 case ARM::LDRD_POST: {
5349 case ARM::STRD: {
5358 case ARM::STRD_PRE:
5359 case ARM::STRD_POST: {
5368 case ARM::SBFX:
5369 case ARM::UBFX: {
5378 case ARM::tLDMIA: {
5407 case ARM::t2LDMIA_UPD: {
5414 case ARM::tMUL: {
5436 case ARM::tPOP: {
5438 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5444 case ARM::tPUSH: {
5446 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5452 case ARM::tSTMIA_UPD: {
5459 case ARM::tADDrSP: {
5478 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5479 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5480 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5481 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5482 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5483 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5484 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5485 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5486 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5489 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5490 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5491 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5492 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5493 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5495 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5496 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5497 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5498 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5499 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5501 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5502 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5503 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5504 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5505 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5508 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5509 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5510 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5511 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5512 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5513 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5514 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5515 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5516 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5517 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5518 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5519 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5520 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5521 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5522 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5525 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5526 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5527 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5528 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5529 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5530 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5531 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5532 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5533 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5534 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5535 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5536 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5537 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5538 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5539 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5540 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5541 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5542 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5545 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5546 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5547 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5548 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5549 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5550 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5551 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5552 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5553 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5554 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5555 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5556 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5557 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5558 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5559 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5562 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5563 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5564 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5565 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5566 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5567 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5568 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5569 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5570 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5571 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5572 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5573 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5574 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5575 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5576 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5577 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5578 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5579 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5587 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5588 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5589 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5590 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5591 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5592 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5593 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5594 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5595 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5598 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5599 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5600 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5601 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5602 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5603 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5604 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5605 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5606 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5607 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5608 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5609 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5610 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5611 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5612 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5615 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5616 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5617 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5618 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5619 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5620 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5621 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5622 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5623 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5624 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5625 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5626 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5627 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5628 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5629 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5630 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5631 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5632 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5635 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5636 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5637 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5638 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5639 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5640 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5641 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5642 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5643 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5644 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5645 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5646 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5647 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5648 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5649 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5652 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5653 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5654 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5655 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5656 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5657 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5658 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5659 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5660 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5661 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5662 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5663 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5664 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5665 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5666 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5667 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5668 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5669 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5672 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5673 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5674 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5675 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5676 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5677 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5678 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5679 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5680 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5681 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5682 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5683 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5684 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5685 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5686 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5689 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5690 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5691 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5692 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5693 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5694 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5695 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5696 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5697 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5698 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5699 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5700 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5701 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5702 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5703 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5704 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5705 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5706 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5709 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5710 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5711 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5712 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5713 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5714 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5715 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5716 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5717 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5718 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5719 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5720 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5721 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5722 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5723 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5724 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5725 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5726 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5735 case ARM::ADDri: {
5736 if (Inst.getOperand(1).getReg() != ARM::PC ||
5740 TmpInst.setOpcode(ARM::ADR);
5749 case ARM::t2LDRpcrel:
5753 Inst.setOpcode(ARM::tLDRpci);
5755 Inst.setOpcode(ARM::t2LDRpci);
5757 case ARM::t2LDRBpcrel:
5758 Inst.setOpcode(ARM::t2LDRBpci);
5760 case ARM::t2LDRHpcrel:
5761 Inst.setOpcode(ARM::t2LDRHpci);
5763 case ARM::t2LDRSBpcrel:
5764 Inst.setOpcode(ARM::t2LDRSBpci);
5766 case ARM::t2LDRSHpcrel:
5767 Inst.setOpcode(ARM::t2LDRSHpci);
5770 case ARM::VST1LNdWB_register_Asm_8:
5771 case ARM::VST1LNdWB_register_Asm_16:
5772 case ARM::VST1LNdWB_register_Asm_32: {
5790 case ARM::VST2LNdWB_register_Asm_8:
5791 case ARM::VST2LNdWB_register_Asm_16:
5792 case ARM::VST2LNdWB_register_Asm_32:
5793 case ARM::VST2LNqWB_register_Asm_16:
5794 case ARM::VST2LNqWB_register_Asm_32: {
5814 case ARM::VST3LNdWB_register_Asm_8:
5815 case ARM::VST3LNdWB_register_Asm_16:
5816 case ARM::VST3LNdWB_register_Asm_32:
5817 case ARM::VST3LNqWB_register_Asm_16:
5818 case ARM::VST3LNqWB_register_Asm_32: {
5840 case ARM::VST4LNdWB_register_Asm_8:
5841 case ARM::VST4LNdWB_register_Asm_16:
5842 case ARM::VST4LNdWB_register_Asm_32:
5843 case ARM::VST4LNqWB_register_Asm_16:
5844 case ARM::VST4LNqWB_register_Asm_32: {
5868 case ARM::VST1LNdWB_fixed_Asm_8:
5869 case ARM::VST1LNdWB_fixed_Asm_16:
5870 case ARM::VST1LNdWB_fixed_Asm_32: {
5888 case ARM::VST2LNdWB_fixed_Asm_8:
5889 case ARM::VST2LNdWB_fixed_Asm_16:
5890 case ARM::VST2LNdWB_fixed_Asm_32:
5891 case ARM::VST2LNqWB_fixed_Asm_16:
5892 case ARM::VST2LNqWB_fixed_Asm_32: {
5912 case ARM::VST3LNdWB_fixed_Asm_8:
5913 case ARM::VST3LNdWB_fixed_Asm_16:
5914 case ARM::VST3LNdWB_fixed_Asm_32:
5915 case ARM::VST3LNqWB_fixed_Asm_16:
5916 case ARM::VST3LNqWB_fixed_Asm_32: {
5938 case ARM::VST4LNdWB_fixed_Asm_8:
5939 case ARM::VST4LNdWB_fixed_Asm_16:
5940 case ARM::VST4LNdWB_fixed_Asm_32:
5941 case ARM::VST4LNqWB_fixed_Asm_16:
5942 case ARM::VST4LNqWB_fixed_Asm_32: {
5966 case ARM::VST1LNdAsm_8:
5967 case ARM::VST1LNdAsm_16:
5968 case ARM::VST1LNdAsm_32: {
5984 case ARM::VST2LNdAsm_8:
5985 case ARM::VST2LNdAsm_16:
5986 case ARM::VST2LNdAsm_32:
5987 case ARM::VST2LNqAsm_16:
5988 case ARM::VST2LNqAsm_32: {
6006 case ARM::VST3LNdAsm_8:
6007 case ARM::VST3LNdAsm_16:
6008 case ARM::VST3LNdAsm_32:
6009 case ARM::VST3LNqAsm_16:
6010 case ARM::VST3LNqAsm_32: {
6030 case ARM::VST4LNdAsm_8:
6031 case ARM::VST4LNdAsm_16:
6032 case ARM::VST4LNdAsm_32:
6033 case ARM::VST4LNqAsm_16:
6034 case ARM::VST4LNqAsm_32: {
6057 case ARM::VLD1LNdWB_register_Asm_8:
6058 case ARM::VLD1LNdWB_register_Asm_16:
6059 case ARM::VLD1LNdWB_register_Asm_32: {
6078 case ARM::VLD2LNdWB_register_Asm_8:
6079 case ARM::VLD2LNdWB_register_Asm_16:
6080 case ARM::VLD2LNdWB_register_Asm_32:
6081 case ARM::VLD2LNqWB_register_Asm_16:
6082 case ARM::VLD2LNqWB_register_Asm_32: {
6105 case ARM::VLD3LNdWB_register_Asm_8:
6106 case ARM::VLD3LNdWB_register_Asm_16:
6107 case ARM::VLD3LNdWB_register_Asm_32:
6108 case ARM::VLD3LNqWB_register_Asm_16:
6109 case ARM::VLD3LNqWB_register_Asm_32: {
6136 case ARM::VLD4LNdWB_register_Asm_8:
6137 case ARM::VLD4LNdWB_register_Asm_16:
6138 case ARM::VLD4LNdWB_register_Asm_32:
6139 case ARM::VLD4LNqWB_register_Asm_16:
6140 case ARM::VLD4LNqWB_register_Asm_32: {
6171 case ARM::VLD1LNdWB_fixed_Asm_8:
6172 case ARM::VLD1LNdWB_fixed_Asm_16:
6173 case ARM::VLD1LNdWB_fixed_Asm_32: {
6192 case ARM::VLD2LNdWB_fixed_Asm_8:
6193 case ARM::VLD2LNdWB_fixed_Asm_16:
6194 case ARM::VLD2LNdWB_fixed_Asm_32:
6195 case ARM::VLD2LNqWB_fixed_Asm_16:
6196 case ARM::VLD2LNqWB_fixed_Asm_32: {
6219 case ARM::VLD3LNdWB_fixed_Asm_8:
6220 case ARM::VLD3LNdWB_fixed_Asm_16:
6221 case ARM::VLD3LNdWB_fixed_Asm_32:
6222 case ARM::VLD3LNqWB_fixed_Asm_16:
6223 case ARM::VLD3LNqWB_fixed_Asm_32: {
6250 case ARM::VLD4LNdWB_fixed_Asm_8:
6251 case ARM::VLD4LNdWB_fixed_Asm_16:
6252 case ARM::VLD4LNdWB_fixed_Asm_32:
6253 case ARM::VLD4LNqWB_fixed_Asm_16:
6254 case ARM::VLD4LNqWB_fixed_Asm_32: {
6285 case ARM::VLD1LNdAsm_8:
6286 case ARM::VLD1LNdAsm_16:
6287 case ARM::VLD1LNdAsm_32: {
6304 case ARM::VLD2LNdAsm_8:
6305 case ARM::VLD2LNdAsm_16:
6306 case ARM::VLD2LNdAsm_32:
6307 case ARM::VLD2LNqAsm_16:
6308 case ARM::VLD2LNqAsm_32: {
6329 case ARM::VLD3LNdAsm_8:
6330 case ARM::VLD3LNdAsm_16:
6331 case ARM::VLD3LNdAsm_32:
6332 case ARM::VLD3LNqAsm_16:
6333 case ARM::VLD3LNqAsm_32: {
6358 case ARM::VLD4LNdAsm_8:
6359 case ARM::VLD4LNdAsm_16:
6360 case ARM::VLD4LNdAsm_32:
6361 case ARM::VLD4LNqAsm_16:
6362 case ARM::VLD4LNqAsm_32: {
6392 case ARM::VLD3DUPdAsm_8:
6393 case ARM::VLD3DUPdAsm_16:
6394 case ARM::VLD3DUPdAsm_32:
6395 case ARM::VLD3DUPqAsm_8:
6396 case ARM::VLD3DUPqAsm_16:
6397 case ARM::VLD3DUPqAsm_32: {
6414 case ARM::VLD3DUPdWB_fixed_Asm_8:
6415 case ARM::VLD3DUPdWB_fixed_Asm_16:
6416 case ARM::VLD3DUPdWB_fixed_Asm_32:
6417 case ARM::VLD3DUPqWB_fixed_Asm_8:
6418 case ARM::VLD3DUPqWB_fixed_Asm_16:
6419 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6438 case ARM::VLD3DUPdWB_register_Asm_8:
6439 case ARM::VLD3DUPdWB_register_Asm_16:
6440 case ARM::VLD3DUPdWB_register_Asm_32:
6441 case ARM::VLD3DUPqWB_register_Asm_8:
6442 case ARM::VLD3DUPqWB_register_Asm_16:
6443 case ARM::VLD3DUPqWB_register_Asm_32: {
6463 case ARM::VLD3dAsm_8:
6464 case ARM::VLD3dAsm_16:
6465 case ARM::VLD3dAsm_32:
6466 case ARM::VLD3qAsm_8:
6467 case ARM::VLD3qAsm_16:
6468 case ARM::VLD3qAsm_32: {
6485 case ARM::VLD3dWB_fixed_Asm_8:
6486 case ARM::VLD3dWB_fixed_Asm_16:
6487 case ARM::VLD3dWB_fixed_Asm_32:
6488 case ARM::VLD3qWB_fixed_Asm_8:
6489 case ARM::VLD3qWB_fixed_Asm_16:
6490 case ARM::VLD3qWB_fixed_Asm_32: {
6509 case ARM::VLD3dWB_register_Asm_8:
6510 case ARM::VLD3dWB_register_Asm_16:
6511 case ARM::VLD3dWB_register_Asm_32:
6512 case ARM::VLD3qWB_register_Asm_8:
6513 case ARM::VLD3qWB_register_Asm_16:
6514 case ARM::VLD3qWB_register_Asm_32: {
6534 case ARM::VLD4DUPdAsm_8:
6535 case ARM::VLD4DUPdAsm_16:
6536 case ARM::VLD4DUPdAsm_32:
6537 case ARM::VLD4DUPqAsm_8:
6538 case ARM::VLD4DUPqAsm_16:
6539 case ARM::VLD4DUPqAsm_32: {
6558 case ARM::VLD4DUPdWB_fixed_Asm_8:
6559 case ARM::VLD4DUPdWB_fixed_Asm_16:
6560 case ARM::VLD4DUPdWB_fixed_Asm_32:
6561 case ARM::VLD4DUPqWB_fixed_Asm_8:
6562 case ARM::VLD4DUPqWB_fixed_Asm_16:
6563 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6584 case ARM::VLD4DUPdWB_register_Asm_8:
6585 case ARM::VLD4DUPdWB_register_Asm_16:
6586 case ARM::VLD4DUPdWB_register_Asm_32:
6587 case ARM::VLD4DUPqWB_register_Asm_8:
6588 case ARM::VLD4DUPqWB_register_Asm_16:
6589 case ARM::VLD4DUPqWB_register_Asm_32: {
6611 case ARM::VLD4dAsm_8:
6612 case ARM::VLD4dAsm_16:
6613 case ARM::VLD4dAsm_32:
6614 case ARM::VLD4qAsm_8:
6615 case ARM::VLD4qAsm_16:
6616 case ARM::VLD4qAsm_32: {
6635 case ARM::VLD4dWB_fixed_Asm_8:
6636 case ARM::VLD4dWB_fixed_Asm_16:
6637 case ARM::VLD4dWB_fixed_Asm_32:
6638 case ARM::VLD4qWB_fixed_Asm_8:
6639 case ARM::VLD4qWB_fixed_Asm_16:
6640 case ARM::VLD4qWB_fixed_Asm_32: {
6661 case ARM::VLD4dWB_register_Asm_8:
6662 case ARM::VLD4dWB_register_Asm_16:
6663 case ARM::VLD4dWB_register_Asm_32:
6664 case ARM::VLD4qWB_register_Asm_8:
6665 case ARM::VLD4qWB_register_Asm_16:
6666 case ARM::VLD4qWB_register_Asm_32: {
6688 case ARM::VST3dAsm_8:
6689 case ARM::VST3dAsm_16:
6690 case ARM::VST3dAsm_32:
6691 case ARM::VST3qAsm_8:
6692 case ARM::VST3qAsm_16:
6693 case ARM::VST3qAsm_32: {
6710 case ARM::VST3dWB_fixed_Asm_8:
6711 case ARM::VST3dWB_fixed_Asm_16:
6712 case ARM::VST3dWB_fixed_Asm_32:
6713 case ARM::VST3qWB_fixed_Asm_8:
6714 case ARM::VST3qWB_fixed_Asm_16:
6715 case ARM::VST3qWB_fixed_Asm_32: {
6734 case ARM::VST3dWB_register_Asm_8:
6735 case ARM::VST3dWB_register_Asm_16:
6736 case ARM::VST3dWB_register_Asm_32:
6737 case ARM::VST3qWB_register_Asm_8:
6738 case ARM::VST3qWB_register_Asm_16:
6739 case ARM::VST3qWB_register_Asm_32: {
6759 case ARM::VST4dAsm_8:
6760 case ARM::VST4dAsm_16:
6761 case ARM::VST4dAsm_32:
6762 case ARM::VST4qAsm_8:
6763 case ARM::VST4qAsm_16:
6764 case ARM::VST4qAsm_32: {
6783 case ARM::VST4dWB_fixed_Asm_8:
6784 case ARM::VST4dWB_fixed_Asm_16:
6785 case ARM::VST4dWB_fixed_Asm_32:
6786 case ARM::VST4qWB_fixed_Asm_8:
6787 case ARM::VST4qWB_fixed_Asm_16:
6788 case ARM::VST4qWB_fixed_Asm_32: {
6809 case ARM::VST4dWB_register_Asm_8:
6810 case ARM::VST4dWB_register_Asm_16:
6811 case ARM::VST4dWB_register_Asm_32:
6812 case ARM::VST4qWB_register_Asm_8:
6813 case ARM::VST4qWB_register_Asm_16:
6814 case ARM::VST4qWB_register_Asm_32: {
6836 case ARM::t2LSLri:
6837 case ARM::t2LSRri:
6838 case ARM::t2ASRri: {
6841 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6847 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6848 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6849 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6867 case ARM::t2MOVsr:
6868 case ARM::t2MOVSsr: {
6877 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6883 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6884 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6885 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6886 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
6892 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6899 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6903 case ARM::t2MOVsi:
6904 case ARM::t2MOVSsi: {
6911 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6917 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6918 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6919 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6920 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6921 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6929 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6931 if (newOpc != ARM::t2RRX)
6937 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6941 // Handle the ARM mode MOV complex aliases.
6942 case ARM::ASRr:
6943 case ARM::LSRr:
6944 case ARM::LSLr:
6945 case ARM::RORr: {
6949 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6950 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6951 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6952 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6956 TmpInst.setOpcode(ARM::MOVsr);
6967 case ARM::ASRi:
6968 case ARM::LSRi:
6969 case ARM::LSLi:
6970 case ARM::RORi: {
6974 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6975 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6976 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6977 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6981 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6990 if (Opc == ARM::MOVsi)
6998 case ARM::RRXi: {
7001 TmpInst.setOpcode(ARM::MOVsi);
7011 case ARM::t2LDMIA_UPD: {
7013 // a post-indexed LDR instruction instead, per the ARM ARM.
7017 TmpInst.setOpcode(ARM::t2LDR_POST);
7027 case ARM::t2STMDB_UPD: {
7029 // a pre-indexed STR instruction instead, per the ARM ARM.
7033 TmpInst.setOpcode(ARM::t2STR_PRE);
7043 case ARM::LDMIA_UPD:
7045 // a post-indexed LDR instruction instead, per the ARM ARM.
7049 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7061 case ARM::STMDB_UPD:
7063 // a pre-indexed STR instruction instead, per the ARM ARM.
7067 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7077 case ARM::t2ADDri12:
7083 Inst.setOpcode(ARM::t2ADDri);
7086 case ARM::t2SUBri12:
7092 Inst.setOpcode(ARM::t2SUBri);
7095 case ARM::tADDi8:
7097 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7101 Inst.setOpcode(ARM::tADDi3);
7105 case ARM::tSUBi8:
7107 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7111 Inst.setOpcode(ARM::tSUBi3);
7115 case ARM::t2ADDri:
7116 case ARM::t2SUBri: {
7124 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7130 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7131 ARM::tADDi8 : ARM::tSUBi8);
7141 case ARM::t2ADDrr: {
7152 TmpInst.setOpcode(ARM::tADDhirr);
7161 case ARM::tADDrSP: {
7165 Inst.setOpcode(ARM::t2ADDrr);
7171 case ARM::tB:
7174 Inst.setOpcode(ARM::tBcc);
7178 case ARM::t2B:
7181 Inst.setOpcode(ARM::t2Bcc);
7185 case ARM::t2Bcc:
7188 Inst.setOpcode(ARM::t2B);
7192 case ARM::tBcc:
7195 Inst.setOpcode(ARM::tB);
7199 case ARM::tLDMIA: {
7214 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7224 case ARM::tSTMIA_UPD: {
7233 Inst.setOpcode(ARM::t2STMIA_UPD);
7238 case ARM::tPOP: {
7243 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7246 Inst.setOpcode(ARM::t2LDMIA_UPD);
7248 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7249 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7252 case ARM::tPUSH: {
7254 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7257 Inst.setOpcode(ARM::t2STMDB_UPD);
7259 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7260 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7263 case ARM::t2MOVi: {
7269 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7275 TmpInst.setOpcode(ARM::tMOVi8);
7286 case ARM::t2MOVr: {
7292 Inst.getOperand(4).getReg() == ARM::CPSR &&
7297 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7307 case ARM::t2SXTH:
7308 case ARM::t2SXTB:
7309 case ARM::t2UXTH:
7310 case ARM::t2UXTB: {
7321 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7322 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7323 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7324 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7338 case ARM::MOVsi: {
7346 TmpInst.setOpcode(ARM::MOVr);
7357 case ARM::ANDrsi:
7358 case ARM::ORRrsi:
7359 case ARM::EORrsi:
7360 case ARM::BICrsi:
7361 case ARM::SUBrsi:
7362 case ARM::ADDrsi: {
7368 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7369 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7370 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7371 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7372 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7373 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7392 case ARM::ITasm:
7393 case ARM::t2IT: {
7418 case ARM::t2LSLrr:
7419 case ARM::t2LSRrr:
7420 case ARM::t2ASRrr:
7421 case ARM::t2SBCrr:
7422 case ARM::t2RORrr:
7423 case ARM::t2BICrr:
7429 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7430 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7436 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7437 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7438 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7439 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7440 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7441 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7456 case ARM::t2ANDrr:
7457 case ARM::t2EORrr:
7458 case ARM::t2ADCrr:
7459 case ARM::t2ORRrr:
7468 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7469 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7475 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7476 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7477 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7478 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7519 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7523 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7526 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7532 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7537 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7579 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7581 if (Inst.getOpcode() == ARM::ITasm)
7590 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).