Searched refs:AM (Results 1 - 25 of 48) sorted by relevance

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/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp106 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
107 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
108 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
139 bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) { argument
142 if (AM.hasSymbolicDisplacement())
148 AM.GV = G->getGlobal();
149 AM.Disp += G->getOffset();
150 //AM.SymbolFlags = G->getTargetFlags();
152 AM.CP = CP->getConstVal();
153 AM
171 MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) argument
184 MatchAddress(SDValue N, MSP430ISelAddressMode &AM) argument
250 MSP430ISelAddressMode AM; local
303 ISD::MemIndexedMode AM = LD->getAddressingMode(); local
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H A DMSP430ISelLowering.h170 ISD::MemIndexedMode &AM,
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/
H A DX86InstrBuilder.h123 const X86AddressMode &AM) {
124 assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
126 if (AM.BaseType == X86AddressMode::RegBase)
127 MIB.addReg(AM.Base.Reg);
129 assert(AM.BaseType == X86AddressMode::FrameIndexBase);
130 MIB.addFrameIndex(AM.Base.FrameIndex);
133 MIB.addImm(AM
122 addFullAddress(const MachineInstrBuilder &MIB, const X86AddressMode &AM) argument
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H A DX86ISelDAGToDAG.cpp193 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
194 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
195 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
196 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
197 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
199 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
228 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, argument
231 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
232 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, TLI.getPointerTy()) :
233 AM
583 FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM) argument
602 MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM) argument
630 MatchWrapper(SDValue N, X86ISelAddressMode &AM) argument
725 MatchAddress(SDValue N, X86ISelAddressMode &AM) argument
770 FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument
813 FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument
880 FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument
961 MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, unsigned Depth) argument
1272 MatchAddressBase(SDValue N, X86ISelAddressMode &AM) argument
1302 X86ISelAddressMode AM; local
1389 X86ISelAddressMode AM; local
1453 X86ISelAddressMode AM; local
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H A DX86FastISel.cpp85 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
87 bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM);
88 bool X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM);
93 bool X86SelectAddress(const Value *V, X86AddressMode &AM);
94 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM);
182 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, argument
232 DL, TII.get(Opc), ResultReg), AM);
241 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM) { argument
282 DL, TII.get(Opc)), AM).addReg(Val);
287 const X86AddressMode &AM) {
286 X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM) argument
342 X86SelectAddress(const Value *V, X86AddressMode &AM) argument
602 X86SelectCallAddress(const Value *V, X86AddressMode &AM) argument
1573 X86AddressMode AM; local
1580 X86AddressMode AM; local
1990 X86AddressMode AM; local
2292 X86AddressMode AM; local
2403 X86AddressMode AM; local
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/freebsd-10.0-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp103 // Try to fold more of the base or index of AM into AM, where IsBase
105 bool expandAddress(SystemZAddressingMode &AM, bool IsBase);
107 // Try to describe N in AM, returning true on success.
108 bool selectAddress(SDValue N, SystemZAddressingMode &AM);
110 // Extract individual target operands from matched address AM.
111 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
113 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
259 // Change the base or index in AM to Value, where IsBase selects
261 static void changeComponent(SystemZAddressingMode &AM, boo argument
272 expandAdjDynAlloc(SystemZAddressingMode &AM, bool IsBase, SDValue Value) argument
284 expandIndex(SystemZAddressingMode &AM, SDValue Base, SDValue Index) argument
296 expandDisp(SystemZAddressingMode &AM, bool IsBase, SDValue Op0, ConstantSDNode *Op1) argument
311 expandAddress(SystemZAddressingMode &AM, bool IsBase) argument
416 selectAddress(SDValue Addr, SystemZAddressingMode &AM) argument
462 getAddressOperands(const SystemZAddressingMode &AM, EVT VT, SDValue &Base, SDValue &Disp) argument
487 getAddressOperands(const SystemZAddressingMode &AM, EVT VT, SDValue &Base, SDValue &Disp, SDValue &Index) argument
[all...]
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/
H A DBasicTargetTransformInfo.cpp134 TargetLoweringBase::AddrMode AM; local
135 AM.BaseGV = BaseGV;
136 AM.BaseOffs = BaseOffset;
137 AM.HasBaseReg = HasBaseReg;
138 AM.Scale = Scale;
139 return TLI->isLegalAddressingMode(AM, Ty);
H A DTargetLoweringBase.cpp1278 /// by AM is legal for this target, for a load/store of the specified type.
1279 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM, argument
1285 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1289 if (AM.BaseGV)
1293 switch (AM.Scale) {
1297 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1302 if (AM.HasBaseReg || AM
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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp319 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { argument
320 switch (AM) {
458 const char *AM = getIndexedModeName(LD->getAddressingMode()); local
459 if (*AM)
460 OS << ", " << AM; local
469 const char *AM = getIndexedModeName(ST->getAddressingMode()); local
470 if (*AM)
471 OS << ", " << AM; local
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h148 ISD::MemIndexedMode &AM,
159 /// by AM is legal for this target, for a load/store of the specified type.
163 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
H A DHexagonISelLowering.cpp641 ISD::MemIndexedMode &AM,
666 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
1627 /// AM is legal for this target, for a load/store of the specified type.
1628 bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument
1631 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) {
1636 if (AM.BaseGV) {
1640 int Scale = AM.Scale;
638 getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument
/freebsd-10.0-release/tools/regression/bin/date/
H A Dregress.sh73 check p AM PM
75 check r "07:04:03 AM" "09:20:00 PM"
/freebsd-10.0-release/contrib/llvm/lib/Analysis/
H A DTypeBasedAliasAnalysis.cpp377 const MDNode *AM = LocA.TBAATag; local
378 if (!AM) return AliasAnalysis::alias(LocA, LocB);
383 if (Aliases(AM, BM))
H A DDependenceAnalysis.cpp1272 // Computes the GCD of AM and BM.
1276 bool findGCD(unsigned Bits, APInt AM, APInt BM, APInt Delta, argument
1280 APInt G0 = AM.abs();
1293 X = AM.slt(0) ? -A1 : A1;
1373 DEBUG(dbgs() << "\t SrcCoeff = " << *SrcCoeff << " = AM\n");
1393 APInt AM = ConstSrcCoeff->getValue()->getValue(); local
1395 unsigned Bits = AM.getBitWidth();
1396 if (findGCD(Bits, AM, BM, ConstDelta->getValue()->getValue(), G, X, Y)) {
1438 // test(AM/G, LM-Y) and test(-AM/
1797 APInt AM = ConstSrcCoeff->getValue()->getValue(); local
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/freebsd-10.0-release/usr.bin/at/
H A Dparsetime.c29 * /NUMBER [DOT NUMBER] [AM|PM]\ /[MONTH NUMBER [NUMBER]] \
65 PM, AM, TOMORROW, TODAY, NOW, enumerator in enum:__anon11391
83 { "am", AM,0 }, /* morning times for 0-12 clock */
358 * [NUMBER [DOT NUMBER] [AM|PM]]
386 /* check if an AM or PM specifier was given
388 if (sc_tokid == AM || sc_tokid == PM) {
396 if (hour == 12) /* 12:xx AM is 00:xx, not 12:xx */
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.h302 /// by AM is legal for this target, for a load/store of the specified type.
303 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
304 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
323 ISD::MemIndexedMode &AM,
331 ISD::MemIndexedMode &AM,
H A DARMISelDAGToDAG.cpp811 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local
814 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
847 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local
850 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
867 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local
870 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
940 ISD::MemIndexedMode AM local
1026 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); local
1342 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local
1415 ISD::MemIndexedMode AM = LD->getAddressingMode(); local
1488 ISD::MemIndexedMode AM = LD->getAddressingMode(); local
[all...]
/freebsd-10.0-release/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1538 /// by AM is legal for this target, for a load/store of the specified type.
1540 XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument
1543 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
1547 if (AM.BaseGV) {
1548 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
1549 AM.BaseOffs%4 == 0;
1555 if (AM
[all...]
H A DXCoreISelLowering.h106 virtual bool isLegalAddressingMode(const AddrMode &AM,
/freebsd-10.0-release/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.h94 /// by AM is legal for this target, for a load/store of the specified type
98 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
H A DNVPTXISelLowering.cpp1358 /// by AM is legal for this target, for a load/store of the specified type.
1362 bool NVPTXTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument
1374 if (AM.BaseGV) {
1375 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale)
1380 switch (AM.Scale) {
1384 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h616 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
1593 unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM,
1596 SubclassData |= AM << 2;
1597 assert(getAddressingMode() == AM && "MemIndexedMode encoding error!");
1630 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
1633 VTs, AM, MemVT, MMO) {
1660 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
1663 VTs, AM, MemVT, MMO) {
1592 LSBaseSDNode(ISD::NodeType NodeTy, DebugLoc dl, SDValue *Operands, unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, MachineMemOperand *MMO) argument
1629 LoadSDNode(SDValue *ChainPtrOff, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, MachineMemOperand *MMO) argument
1659 StoreSDNode(SDValue *ChainValuePtrOff, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, MachineMemOperand *MMO) argument
H A DSelectionDAG.h707 SDValue Offset, ISD::MemIndexedMode AM);
708 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
715 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
736 SDValue Offset, ISD::MemIndexedMode AM);
/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h350 ISD::MemIndexedMode &AM,
436 /// by AM is legal for this target, for a load/store of the specified type.
437 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
/freebsd-10.0-release/contrib/ntp/ntpd/
H A Dntp_peer.c47 int AM[AM_MODES][AM_MODES] = { variable
65 #define MATCH_ASSOC(x,y) AM[(x)][(y)]

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