Searched refs:reg_offset (Results 1 - 25 of 34) sorted by relevance

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/freebsd-10-stable/sys/dev/drm2/i915/
H A Dintel_iic.c241 int reg_offset = dev_priv->gpio_mmio_base; local
245 I915_WRITE(GMBUS1 + reg_offset,
257 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
265 val = I915_READ(GMBUS3 + reg_offset);
278 int reg_offset = dev_priv->gpio_mmio_base; local
289 I915_WRITE(GMBUS3 + reg_offset, val);
290 I915_WRITE(GMBUS1 + reg_offset,
304 I915_WRITE(GMBUS3 + reg_offset, val);
307 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
333 int reg_offset local
363 int error, i, ret, reg_offset, unit; local
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/freebsd-10-stable/contrib/gdb/gdb/
H A Damd64-nat.c58 int *reg_offset = amd64_native_gregset64_reg_offset; local
65 reg_offset = amd64_native_gregset32_reg_offset;
73 return reg_offset[regnum];
H A Dia64-fbsd-tdep.c39 static int reg_offset[462] = { variable
109 ofs = reg_offset[regno];
133 ofs = reg_offset[regno];
138 IA64_BSP_REGNUM in the reg_offset array above is that of the
142 bsp += *((uint64_t*)((char *)regs + reg_offset[IA64_BSPSTORE_REGNUM]));
H A Damd64fbsd-nat.c56 /* At reg_offset[REGNUM] you'll find the offset to the gregset_t
59 static int reg_offset[] =
162 amd64_native_gregset64_reg_offset = reg_offset;
58 static int reg_offset[] = variable
H A Di386bsd-nat.c68 /* At reg_offset[REGNO] you'll find the offset to the gregset_t
71 static int reg_offset[] =
99 #define REG_ADDR(regset, regno) ((char *) (regset) + reg_offset[regno])
116 return (reg_offset[regno] == -1);
70 static int reg_offset[] = variable
H A Dmips-tdep.c294 int reg_offset = 0; local
301 reg_offset = register_size (current_gdbarch, reg_num) - length;
304 reg_offset = 0;
307 reg_offset = 0;
315 reg_num, reg_offset, buf_offset, length);
324 regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
327 regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
1498 long reg_offset; local
1518 reg_offset = PROC_REG_OFFSET (proc_desc);
1573 CORE_ADDR reg_position = (cache->base + reg_offset);
2594 int reg_offset; member in struct:return_value_word
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H A Di386gnu-nat.c51 static int reg_offset[] = variable
59 #define REG_ADDR(state, regnum) ((char *)(state) + reg_offset[regnum])
H A Dvalops.c656 int reg_offset; local
665 for (reg_offset = value_reg, offset = 0;
666 offset + DEPRECATED_REGISTER_RAW_SIZE (reg_offset) <= VALUE_OFFSET (toval);
667 reg_offset++);
682 for (regno = reg_offset, amount_copied = 0;
699 for (regno = reg_offset, amount_copied = 0;
/freebsd-10-stable/sys/dev/qlnx/qlnxe/
H A Decore_init_fw_funcs.c1030 u32 ctrl, inc_val, reg_offset; local
1070 for (tc = 0, reg_offset = 0; tc < NUM_OF_PHYS_TCS; tc++, reg_offset += 4) {
1074 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_CTRL_0 + reg_offset, ctrl);
1081 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0 + reg_offset, NIG_RL_PERIOD_CLK_25M);
1083 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_INC_VALUE_0 + reg_offset, inc_val);
1084 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_MAX_VALUE_0 + reg_offset, NIG_RL_MAX_VAL(inc_val, req->mtu));
1088 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_CTRL_0 + reg_offset, ctrl);
1197 u32 active_port_blocks, reg_offset = 0; local
1233 for (tc = 0; tc < NUM_OF_TCS; tc++, reg_offset
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H A Decore_dbg_fw_funcs.c2467 u32 reg_offset = constraint_id * BYTES_IN_DWORD; local
2473 reg_offset += curr_trigger_state * TRIGGER_SETS_PER_STATE * MAX_CONSTRAINTS * BYTES_IN_DWORD;
2476 ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_OPRTN_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_0) + reg_offset, hw_op_val);
2477 ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_DATA_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_0) + reg_offset, data_val);
2478 ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_DATA_MASK_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_0) + reg_offset, data_mask);
2479 ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_FRAME_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_0) + reg_offset, frame_bit);
2480 ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_FRAME_MASK_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0) + reg_offset, frame_mask);
2481 ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_OFFSET_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0) + reg_offset, dword_offset);
2482 ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_RANGE_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0) + reg_offset, range);
2483 ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_CYCLIC_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_0) + reg_offset, cyclic_bi
3076 u32 offset = 0, reg_offset = 0; local
5413 u8 reg_offset; local
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H A Decore_cxt.c2402 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line; local
2501 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2512 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2555 u32 reg_offset, elem_size, hw_p_size, elems_per_p; local
2616 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2625 reg_offset,
/freebsd-10-stable/contrib/gcc/
H A Dpostreload.c1164 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
1169 reg_offset[n] in mode reg_mode[n] .
1171 sum of reg_offset[n] and the value of register reg_base_reg[n] variable
1173 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
1183 invalidate all previously collected reg_offset data. */
1250 rtx new_src = gen_int_mode (INTVAL (src) - reg_offset[regno],
1264 if (INTVAL (src) == reg_offset [regno])
1282 && ((reg_offset[regno]
1304 reg_offset[regno] = INTVAL (src);
1336 HOST_WIDE_INT base_offset = reg_offset[REGN
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H A Dlocal-alloc.c218 static char *reg_offset;
327 reg_offset[regno] = 0;
382 reg_offset = XNEWVEC (char, max_regno);
447 free (reg_offset);
1737 reg_renumber[i] = qty[q].phys_reg + reg_offset[i];
2033 reg_offset[sreg] = reg_offset[ureg] + offset;
2051 reg_offset[i] -= offset;
217 static char *reg_offset; variable
/freebsd-10-stable/sys/dev/drm2/radeon/
H A Dni.c1291 u32 reg_offset, wb_offset; local
1303 reg_offset = DMA0_REGISTER_OFFSET;
1307 reg_offset = DMA1_REGISTER_OFFSET;
1311 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
1312 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
1320 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
1323 WREG32(DMA_RB_RPTR + reg_offset, 0);
1324 WREG32(DMA_RB_WPTR + reg_offset, 0);
1327 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,
1329 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,
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H A Dsi.c925 u32 reg_offset, gb_tile_moden, split_equal_to_row_size; local
942 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
943 switch (reg_offset) {
1178 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1181 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1182 switch (reg_offset) {
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/freebsd-10-stable/sys/dev/ieee488/
H A Dupd7210.h53 u_int reg_offset[8]; member in struct:upd7210
H A Dupd7210.c76 r = bus_read_1(u->reg_res[reg], u->reg_offset[reg]);
85 bus_write_1(u->reg_res[reg], u->reg_offset[reg], val);
H A Dpcii.c238 sc->upd7210.reg_offset[rid] = 0;
H A Dtnt4882.c272 sc->upd7210.reg_offset[i] = i * 2;
/freebsd-10-stable/sys/dev/ixgbe/
H A Dixv_mbx.c486 u32 reg_offset = (vf_number < 32) ? 0 : 1; local
495 vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset));
501 vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset));
509 IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift));
H A Dixgbe_mbx.c597 u32 reg_offset = (vf_number < 32) ? 0 : 1; local
606 vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset));
612 vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset));
620 IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift));
/freebsd-10-stable/contrib/llvm/tools/lldb/source/Expression/
H A DDWARFExpression.cpp495 int64_t reg_offset = m_data.GetSLEB128(&offset); local
503 s->Printf("[%s%+" PRIi64 "]", reg_info.name, reg_offset);
508 s->Printf("[%s%+" PRIi64 "]", reg_info.alt_name, reg_offset);
513 s->Printf("DW_OP_breg%i(0x%" PRIx64 ")", reg_num, reg_offset);
546 int64_t reg_offset = m_data.GetSLEB128(&offset); local
554 s->Printf("[%s%+" PRIi64 "]", reg_info.name, reg_offset);
559 s->Printf("[%s%+" PRIi64 "]", reg_info.alt_name, reg_offset);
564 s->Printf("DW_OP_bregx(reg=%" PRIu32 ",offset=%" PRIi64 ")", reg_num, reg_offset);
/freebsd-10-stable/contrib/llvm/tools/lldb/source/Plugins/Process/gdb-remote/
H A DProcessGDBRemote.cpp378 uint32_t reg_offset = 0; local
402 reg_offset, // offset
433 if (reg_offset != offset)
435 reg_offset = offset;
522 reg_info.byte_offset = reg_offset;
524 reg_offset += reg_info.byte_size;
/freebsd-10-stable/sys/dev/e1000/
H A De1000_82575.c2277 u32 reg_val, reg_offset; local
2281 reg_offset = E1000_DTXSWC;
2285 reg_offset = E1000_TXSWC;
2291 reg_val = E1000_READ_REG(hw, reg_offset);
2303 E1000_WRITE_REG(hw, reg_offset, reg_val);
/freebsd-10-stable/contrib/gcc/config/mips/
H A Dmips.c480 unsigned int reg_offset; member in struct:mips_arg_info
3813 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3819 info->reg_offset += info->reg_offset & 1;
3826 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3854 cum->num_gprs = info.reg_offset + info.reg_words;
3888 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3941 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3943 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3967 reg = FP_ARG_FIRST + info.reg_offset;
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