1316485Sdavidcs/* 2316485Sdavidcs * Copyright (c) 2017-2018 Cavium, Inc. 3316485Sdavidcs * All rights reserved. 4316485Sdavidcs * 5316485Sdavidcs * Redistribution and use in source and binary forms, with or without 6316485Sdavidcs * modification, are permitted provided that the following conditions 7316485Sdavidcs * are met: 8316485Sdavidcs * 9316485Sdavidcs * 1. Redistributions of source code must retain the above copyright 10316485Sdavidcs * notice, this list of conditions and the following disclaimer. 11316485Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12316485Sdavidcs * notice, this list of conditions and the following disclaimer in the 13316485Sdavidcs * documentation and/or other materials provided with the distribution. 14316485Sdavidcs * 15316485Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16316485Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17316485Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18316485Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19316485Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20316485Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21316485Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22316485Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23316485Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24316485Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25316485Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26316485Sdavidcs */ 27316485Sdavidcs 28316485Sdavidcs/* 29316485Sdavidcs * File : ecore_dbg_fw_funcs.c 30316485Sdavidcs */ 31316485Sdavidcs#include <sys/cdefs.h> 32316485Sdavidcs__FBSDID("$FreeBSD: stable/10/sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c 337519 2018-08-09 01:39:47Z davidcs $"); 33316485Sdavidcs 34316485Sdavidcs#include "bcm_osal.h" 35316485Sdavidcs#include "ecore.h" 36316485Sdavidcs#include "ecore_hw.h" 37316485Sdavidcs#include "ecore_mcp.h" 38316485Sdavidcs#include "spad_layout.h" 39316485Sdavidcs#include "nvm_map.h" 40316485Sdavidcs#include "reg_addr.h" 41316485Sdavidcs#include "ecore_hsi_common.h" 42316485Sdavidcs#include "ecore_hsi_debug_tools.h" 43316485Sdavidcs#include "mcp_public.h" 44316485Sdavidcs#include "nvm_map.h" 45316485Sdavidcs#ifndef USE_DBG_BIN_FILE 46316485Sdavidcs#include "ecore_dbg_values.h" 47316485Sdavidcs#endif 48316485Sdavidcs#include "ecore_dbg_fw_funcs.h" 49316485Sdavidcs 50316485Sdavidcs/* Memory groups enum */ 51316485Sdavidcsenum mem_groups { 52316485Sdavidcs MEM_GROUP_PXP_MEM, 53316485Sdavidcs MEM_GROUP_DMAE_MEM, 54316485Sdavidcs MEM_GROUP_CM_MEM, 55316485Sdavidcs MEM_GROUP_QM_MEM, 56337519Sdavidcs MEM_GROUP_DORQ_MEM, 57316485Sdavidcs MEM_GROUP_BRB_RAM, 58316485Sdavidcs MEM_GROUP_BRB_MEM, 59316485Sdavidcs MEM_GROUP_PRS_MEM, 60316485Sdavidcs MEM_GROUP_IOR, 61316485Sdavidcs MEM_GROUP_BTB_RAM, 62316485Sdavidcs MEM_GROUP_CONN_CFC_MEM, 63316485Sdavidcs MEM_GROUP_TASK_CFC_MEM, 64316485Sdavidcs MEM_GROUP_CAU_PI, 65316485Sdavidcs MEM_GROUP_CAU_MEM, 66316485Sdavidcs MEM_GROUP_PXP_ILT, 67337519Sdavidcs MEM_GROUP_TM_MEM, 68337519Sdavidcs MEM_GROUP_SDM_MEM, 69316485Sdavidcs MEM_GROUP_PBUF, 70337519Sdavidcs MEM_GROUP_RAM, 71316485Sdavidcs MEM_GROUP_MULD_MEM, 72316485Sdavidcs MEM_GROUP_BTB_MEM, 73320162Sdavidcs MEM_GROUP_RDIF_CTX, 74320162Sdavidcs MEM_GROUP_TDIF_CTX, 75320162Sdavidcs MEM_GROUP_CFC_MEM, 76316485Sdavidcs MEM_GROUP_IGU_MEM, 77316485Sdavidcs MEM_GROUP_IGU_MSIX, 78316485Sdavidcs MEM_GROUP_CAU_SB, 79316485Sdavidcs MEM_GROUP_BMB_RAM, 80316485Sdavidcs MEM_GROUP_BMB_MEM, 81316485Sdavidcs MEM_GROUPS_NUM 82316485Sdavidcs}; 83316485Sdavidcs 84316485Sdavidcs/* Memory groups names */ 85316485Sdavidcsstatic const char* s_mem_group_names[] = { 86316485Sdavidcs "PXP_MEM", 87316485Sdavidcs "DMAE_MEM", 88316485Sdavidcs "CM_MEM", 89316485Sdavidcs "QM_MEM", 90337519Sdavidcs "DORQ_MEM", 91316485Sdavidcs "BRB_RAM", 92316485Sdavidcs "BRB_MEM", 93316485Sdavidcs "PRS_MEM", 94316485Sdavidcs "IOR", 95316485Sdavidcs "BTB_RAM", 96316485Sdavidcs "CONN_CFC_MEM", 97316485Sdavidcs "TASK_CFC_MEM", 98316485Sdavidcs "CAU_PI", 99316485Sdavidcs "CAU_MEM", 100316485Sdavidcs "PXP_ILT", 101337519Sdavidcs "TM_MEM", 102337519Sdavidcs "SDM_MEM", 103316485Sdavidcs "PBUF", 104337519Sdavidcs "RAM", 105316485Sdavidcs "MULD_MEM", 106316485Sdavidcs "BTB_MEM", 107320162Sdavidcs "RDIF_CTX", 108320162Sdavidcs "TDIF_CTX", 109320162Sdavidcs "CFC_MEM", 110316485Sdavidcs "IGU_MEM", 111316485Sdavidcs "IGU_MSIX", 112316485Sdavidcs "CAU_SB", 113316485Sdavidcs "BMB_RAM", 114316485Sdavidcs "BMB_MEM", 115316485Sdavidcs}; 116316485Sdavidcs 117316485Sdavidcs/* Idle check conditions */ 118316485Sdavidcs 119316485Sdavidcs#ifndef __PREVENT_COND_ARR__ 120316485Sdavidcs 121316485Sdavidcsstatic u32 cond5(const u32 *r, const u32 *imm) { 122316485Sdavidcs return (((r[0] & imm[0]) != imm[1]) && ((r[1] & imm[2]) != imm[3])); 123316485Sdavidcs} 124316485Sdavidcs 125316485Sdavidcsstatic u32 cond7(const u32 *r, const u32 *imm) { 126316485Sdavidcs return (((r[0] >> imm[0]) & imm[1]) != imm[2]); 127316485Sdavidcs} 128316485Sdavidcs 129316485Sdavidcsstatic u32 cond6(const u32 *r, const u32 *imm) { 130316485Sdavidcs return ((r[0] & imm[0]) != imm[1]); 131316485Sdavidcs} 132316485Sdavidcs 133316485Sdavidcsstatic u32 cond9(const u32 *r, const u32 *imm) { 134316485Sdavidcs return ((r[0] & imm[0]) >> imm[1]) != (((r[0] & imm[2]) >> imm[3]) | ((r[1] & imm[4]) << imm[5])); 135316485Sdavidcs} 136316485Sdavidcs 137316485Sdavidcsstatic u32 cond10(const u32 *r, const u32 *imm) { 138316485Sdavidcs return ((r[0] & imm[0]) >> imm[1]) != (r[0] & imm[2]); 139316485Sdavidcs} 140316485Sdavidcs 141316485Sdavidcsstatic u32 cond4(const u32 *r, const u32 *imm) { 142316485Sdavidcs return ((r[0] & ~imm[0]) != imm[1]); 143316485Sdavidcs} 144316485Sdavidcs 145316485Sdavidcsstatic u32 cond0(const u32 *r, const u32 *imm) { 146316485Sdavidcs return ((r[0] & ~r[1]) != imm[0]); 147316485Sdavidcs} 148316485Sdavidcs 149316485Sdavidcsstatic u32 cond1(const u32 *r, const u32 *imm) { 150316485Sdavidcs return (r[0] != imm[0]); 151316485Sdavidcs} 152316485Sdavidcs 153316485Sdavidcsstatic u32 cond11(const u32 *r, const u32 *imm) { 154316485Sdavidcs return (r[0] != r[1] && r[2] == imm[0]); 155316485Sdavidcs} 156316485Sdavidcs 157316485Sdavidcsstatic u32 cond12(const u32 *r, const u32 *imm) { 158316485Sdavidcs return (r[0] != r[1] && r[2] > imm[0]); 159316485Sdavidcs} 160316485Sdavidcs 161320162Sdavidcsstatic u32 cond3(const u32 *r, const u32 OSAL_UNUSED *imm) { 162316485Sdavidcs return (r[0] != r[1]); 163316485Sdavidcs} 164316485Sdavidcs 165316485Sdavidcsstatic u32 cond13(const u32 *r, const u32 *imm) { 166316485Sdavidcs return (r[0] & imm[0]); 167316485Sdavidcs} 168316485Sdavidcs 169316485Sdavidcsstatic u32 cond8(const u32 *r, const u32 *imm) { 170316485Sdavidcs return (r[0] < (r[1] - imm[0])); 171316485Sdavidcs} 172316485Sdavidcs 173316485Sdavidcsstatic u32 cond2(const u32 *r, const u32 *imm) { 174316485Sdavidcs return (r[0] > imm[0]); 175316485Sdavidcs} 176316485Sdavidcs 177316485Sdavidcs/* Array of Idle Check conditions */ 178316485Sdavidcsstatic u32 (*cond_arr[])(const u32 *r, const u32 *imm) = { 179316485Sdavidcs cond0, 180316485Sdavidcs cond1, 181316485Sdavidcs cond2, 182316485Sdavidcs cond3, 183316485Sdavidcs cond4, 184316485Sdavidcs cond5, 185316485Sdavidcs cond6, 186316485Sdavidcs cond7, 187316485Sdavidcs cond8, 188316485Sdavidcs cond9, 189316485Sdavidcs cond10, 190316485Sdavidcs cond11, 191316485Sdavidcs cond12, 192316485Sdavidcs cond13, 193316485Sdavidcs}; 194316485Sdavidcs 195316485Sdavidcs#endif /* __PREVENT_COND_ARR__ */ 196316485Sdavidcs 197316485Sdavidcs 198316485Sdavidcs/******************************* Data Types **********************************/ 199316485Sdavidcs 200316485Sdavidcsenum platform_ids { 201316485Sdavidcs PLATFORM_ASIC, 202316485Sdavidcs PLATFORM_EMUL_FULL, 203316485Sdavidcs PLATFORM_EMUL_REDUCED, 204316485Sdavidcs PLATFORM_FPGA, 205316485Sdavidcs MAX_PLATFORM_IDS 206316485Sdavidcs}; 207316485Sdavidcs 208316485Sdavidcsstruct chip_platform_defs { 209316485Sdavidcs u8 num_ports; 210316485Sdavidcs u8 num_pfs; 211316485Sdavidcs u8 num_vfs; 212316485Sdavidcs}; 213316485Sdavidcs 214316485Sdavidcs/* Chip constant definitions */ 215316485Sdavidcsstruct chip_defs { 216316485Sdavidcs const char *name; 217316485Sdavidcs struct chip_platform_defs per_platform[MAX_PLATFORM_IDS]; 218316485Sdavidcs}; 219316485Sdavidcs 220316485Sdavidcs/* Platform constant definitions */ 221316485Sdavidcsstruct platform_defs { 222316485Sdavidcs const char *name; 223316485Sdavidcs u32 delay_factor; 224337519Sdavidcs u32 dmae_thresh; 225337519Sdavidcs u32 log_thresh; 226316485Sdavidcs}; 227316485Sdavidcs 228316485Sdavidcs/* Storm constant definitions. 229316485Sdavidcs * Addresses are in bytes, sizes are in quad-regs. 230316485Sdavidcs */ 231316485Sdavidcsstruct storm_defs { 232316485Sdavidcs char letter; 233316485Sdavidcs enum block_id block_id; 234316485Sdavidcs enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS]; 235316485Sdavidcs bool has_vfc; 236316485Sdavidcs u32 sem_fast_mem_addr; 237316485Sdavidcs u32 sem_frame_mode_addr; 238316485Sdavidcs u32 sem_slow_enable_addr; 239316485Sdavidcs u32 sem_slow_mode_addr; 240316485Sdavidcs u32 sem_slow_mode1_conf_addr; 241316485Sdavidcs u32 sem_sync_dbg_empty_addr; 242316485Sdavidcs u32 sem_slow_dbg_empty_addr; 243316485Sdavidcs u32 cm_ctx_wr_addr; 244316485Sdavidcs u32 cm_conn_ag_ctx_lid_size; 245316485Sdavidcs u32 cm_conn_ag_ctx_rd_addr; 246316485Sdavidcs u32 cm_conn_st_ctx_lid_size; 247316485Sdavidcs u32 cm_conn_st_ctx_rd_addr; 248316485Sdavidcs u32 cm_task_ag_ctx_lid_size; 249316485Sdavidcs u32 cm_task_ag_ctx_rd_addr; 250316485Sdavidcs u32 cm_task_st_ctx_lid_size; 251316485Sdavidcs u32 cm_task_st_ctx_rd_addr; 252316485Sdavidcs}; 253316485Sdavidcs 254316485Sdavidcs/* Block constant definitions */ 255316485Sdavidcsstruct block_defs { 256316485Sdavidcs const char *name; 257320162Sdavidcs bool exists[MAX_CHIP_IDS]; 258316485Sdavidcs bool associated_to_storm; 259316485Sdavidcs 260316485Sdavidcs /* Valid only if associated_to_storm is true */ 261316485Sdavidcs u32 storm_id; 262316485Sdavidcs enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS]; 263316485Sdavidcs u32 dbg_select_addr; 264316485Sdavidcs u32 dbg_enable_addr; 265316485Sdavidcs u32 dbg_shift_addr; 266316485Sdavidcs u32 dbg_force_valid_addr; 267316485Sdavidcs u32 dbg_force_frame_addr; 268316485Sdavidcs bool has_reset_bit; 269316485Sdavidcs 270316485Sdavidcs /* If true, block is taken out of reset before dump */ 271316485Sdavidcs bool unreset; 272316485Sdavidcs enum dbg_reset_regs reset_reg; 273316485Sdavidcs 274316485Sdavidcs /* Bit offset in reset register */ 275316485Sdavidcs u8 reset_bit_offset; 276316485Sdavidcs}; 277316485Sdavidcs 278316485Sdavidcs/* Reset register definitions */ 279316485Sdavidcsstruct reset_reg_defs { 280316485Sdavidcs u32 addr; 281316485Sdavidcs bool exists[MAX_CHIP_IDS]; 282320162Sdavidcs u32 unreset_val[MAX_CHIP_IDS]; 283316485Sdavidcs}; 284316485Sdavidcs 285316485Sdavidcs/* Debug Bus Constraint operation constant definitions */ 286316485Sdavidcsstruct dbg_bus_constraint_op_defs { 287316485Sdavidcs u8 hw_op_val; 288316485Sdavidcs bool is_cyclic; 289316485Sdavidcs}; 290316485Sdavidcs 291316485Sdavidcs/* Storm Mode definitions */ 292316485Sdavidcsstruct storm_mode_defs { 293316485Sdavidcs const char *name; 294316485Sdavidcs bool is_fast_dbg; 295316485Sdavidcs u8 id_in_hw; 296316485Sdavidcs}; 297316485Sdavidcs 298316485Sdavidcsstruct grc_param_defs { 299316485Sdavidcs u32 default_val[MAX_CHIP_IDS]; 300316485Sdavidcs u32 min; 301316485Sdavidcs u32 max; 302316485Sdavidcs bool is_preset; 303316485Sdavidcs u32 exclude_all_preset_val; 304316485Sdavidcs u32 crash_preset_val; 305316485Sdavidcs}; 306316485Sdavidcs 307316485Sdavidcs/* address is in 128b units. Width is in bits. */ 308316485Sdavidcsstruct rss_mem_defs { 309316485Sdavidcs const char *mem_name; 310316485Sdavidcs const char *type_name; 311316485Sdavidcs u32 addr; 312320162Sdavidcs u32 entry_width; 313316485Sdavidcs u32 num_entries[MAX_CHIP_IDS]; 314316485Sdavidcs}; 315316485Sdavidcs 316316485Sdavidcsstruct vfc_ram_defs { 317316485Sdavidcs const char *mem_name; 318316485Sdavidcs const char *type_name; 319316485Sdavidcs u32 base_row; 320316485Sdavidcs u32 num_rows; 321316485Sdavidcs}; 322316485Sdavidcs 323316485Sdavidcsstruct big_ram_defs { 324316485Sdavidcs const char *instance_name; 325316485Sdavidcs enum mem_groups mem_group_id; 326316485Sdavidcs enum mem_groups ram_mem_group_id; 327316485Sdavidcs enum dbg_grc_params grc_param; 328316485Sdavidcs u32 addr_reg_addr; 329316485Sdavidcs u32 data_reg_addr; 330337519Sdavidcs u32 is_256b_reg_addr; 331337519Sdavidcs u32 is_256b_bit_offset[MAX_CHIP_IDS]; 332337519Sdavidcs u32 ram_size[MAX_CHIP_IDS]; /* In dwords */ 333316485Sdavidcs}; 334316485Sdavidcs 335316485Sdavidcsstruct phy_defs { 336316485Sdavidcs const char *phy_name; 337316485Sdavidcs 338316485Sdavidcs /* PHY base GRC address */ 339316485Sdavidcs u32 base_addr; 340316485Sdavidcs 341316485Sdavidcs /* Relative address of indirect TBUS address register (bits 0..7) */ 342316485Sdavidcs u32 tbus_addr_lo_addr; 343316485Sdavidcs 344316485Sdavidcs /* Relative address of indirect TBUS address register (bits 8..10) */ 345316485Sdavidcs u32 tbus_addr_hi_addr; 346316485Sdavidcs 347316485Sdavidcs /* Relative address of indirect TBUS data register (bits 0..7) */ 348316485Sdavidcs u32 tbus_data_lo_addr; 349316485Sdavidcs 350316485Sdavidcs /* Relative address of indirect TBUS data register (bits 8..11) */ 351316485Sdavidcs u32 tbus_data_hi_addr; 352316485Sdavidcs}; 353316485Sdavidcs 354316485Sdavidcs/******************************** Constants **********************************/ 355316485Sdavidcs 356316485Sdavidcs#define MAX_LCIDS 320 357316485Sdavidcs#define MAX_LTIDS 320 358316485Sdavidcs 359316485Sdavidcs#define NUM_IOR_SETS 2 360316485Sdavidcs#define IORS_PER_SET 176 361316485Sdavidcs#define IOR_SET_OFFSET(set_id) ((set_id) * 256) 362316485Sdavidcs 363316485Sdavidcs#define BYTES_IN_DWORD sizeof(u32) 364316485Sdavidcs 365316485Sdavidcs/* Cyclic right */ 366316485Sdavidcs#define SHR(val, val_width, amount) (((val) | ((val) << (val_width))) >> (amount)) & ((1 << (val_width)) - 1) 367316485Sdavidcs 368316485Sdavidcs/* In the macros below, size and offset are specified in bits */ 369316485Sdavidcs#define CEIL_DWORDS(size) DIV_ROUND_UP(size, 32) 370316485Sdavidcs#define FIELD_BIT_OFFSET(type, field) type##_##field##_##OFFSET 371316485Sdavidcs#define FIELD_BIT_SIZE(type, field) type##_##field##_##SIZE 372316485Sdavidcs#define FIELD_DWORD_OFFSET(type, field) (int)(FIELD_BIT_OFFSET(type, field) / 32) 373316485Sdavidcs#define FIELD_DWORD_SHIFT(type, field) (FIELD_BIT_OFFSET(type, field) % 32) 374316485Sdavidcs#define FIELD_BIT_MASK(type, field) (((1 << FIELD_BIT_SIZE(type, field)) - 1) << FIELD_DWORD_SHIFT(type, field)) 375316485Sdavidcs 376316485Sdavidcs#define SET_VAR_FIELD(var, type, field, val) var[FIELD_DWORD_OFFSET(type, field)] &= (~FIELD_BIT_MASK(type, field)); var[FIELD_DWORD_OFFSET(type, field)] |= (val) << FIELD_DWORD_SHIFT(type, field) 377316485Sdavidcs 378316485Sdavidcs#define ARR_REG_WR(dev, ptt, addr, arr, arr_size) for (i = 0; i < (arr_size); i++) ecore_wr(dev, ptt, addr, (arr)[i]) 379316485Sdavidcs 380316485Sdavidcs#define ARR_REG_RD(dev, ptt, addr, arr, arr_size) for (i = 0; i < (arr_size); i++) (arr)[i] = ecore_rd(dev, ptt, addr) 381316485Sdavidcs 382316485Sdavidcs#define CHECK_ARR_SIZE(arr, size) OSAL_BUILD_BUG_ON(!(OSAL_ARRAY_SIZE(arr) == size)) 383316485Sdavidcs 384316485Sdavidcs#ifndef DWORDS_TO_BYTES 385316485Sdavidcs#define DWORDS_TO_BYTES(dwords) ((dwords) * BYTES_IN_DWORD) 386316485Sdavidcs#endif 387316485Sdavidcs#ifndef BYTES_TO_DWORDS 388316485Sdavidcs#define BYTES_TO_DWORDS(bytes) ((bytes) / BYTES_IN_DWORD) 389316485Sdavidcs#endif 390316485Sdavidcs 391316485Sdavidcs/* extra lines include a signature line + optional latency events line */ 392316485Sdavidcs#ifndef NUM_DBG_LINES 393316485Sdavidcs#define NUM_EXTRA_DBG_LINES(block_desc) (1 + (block_desc->has_latency_events ? 1 : 0)) 394316485Sdavidcs#define NUM_DBG_LINES(block_desc) (block_desc->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc)) 395316485Sdavidcs#endif 396316485Sdavidcs 397337519Sdavidcs#define USE_DMAE true 398337519Sdavidcs#define PROTECT_WIDE_BUS true 399337519Sdavidcs 400316485Sdavidcs#define RAM_LINES_TO_DWORDS(lines) ((lines) * 2) 401316485Sdavidcs#define RAM_LINES_TO_BYTES(lines) DWORDS_TO_BYTES(RAM_LINES_TO_DWORDS(lines)) 402316485Sdavidcs 403316485Sdavidcs#define REG_DUMP_LEN_SHIFT 24 404316485Sdavidcs#define MEM_DUMP_ENTRY_SIZE_DWORDS BYTES_TO_DWORDS(sizeof(struct dbg_dump_mem)) 405316485Sdavidcs 406316485Sdavidcs#define IDLE_CHK_RULE_SIZE_DWORDS BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_rule)) 407316485Sdavidcs 408316485Sdavidcs#define IDLE_CHK_RESULT_HDR_DWORDS BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_hdr)) 409316485Sdavidcs 410316485Sdavidcs#define IDLE_CHK_RESULT_REG_HDR_DWORDS BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_reg_hdr)) 411316485Sdavidcs 412316485Sdavidcs#define IDLE_CHK_MAX_ENTRIES_SIZE 32 413316485Sdavidcs 414316485Sdavidcs/* The sizes and offsets below are specified in bits */ 415316485Sdavidcs#define VFC_CAM_CMD_STRUCT_SIZE 64 416316485Sdavidcs#define VFC_CAM_CMD_ROW_OFFSET 48 417316485Sdavidcs#define VFC_CAM_CMD_ROW_SIZE 9 418316485Sdavidcs#define VFC_CAM_ADDR_STRUCT_SIZE 16 419316485Sdavidcs#define VFC_CAM_ADDR_OP_OFFSET 0 420316485Sdavidcs#define VFC_CAM_ADDR_OP_SIZE 4 421316485Sdavidcs#define VFC_CAM_RESP_STRUCT_SIZE 256 422316485Sdavidcs#define VFC_RAM_ADDR_STRUCT_SIZE 16 423316485Sdavidcs#define VFC_RAM_ADDR_OP_OFFSET 0 424316485Sdavidcs#define VFC_RAM_ADDR_OP_SIZE 2 425316485Sdavidcs#define VFC_RAM_ADDR_ROW_OFFSET 2 426316485Sdavidcs#define VFC_RAM_ADDR_ROW_SIZE 10 427316485Sdavidcs#define VFC_RAM_RESP_STRUCT_SIZE 256 428316485Sdavidcs 429316485Sdavidcs#define VFC_CAM_CMD_DWORDS CEIL_DWORDS(VFC_CAM_CMD_STRUCT_SIZE) 430316485Sdavidcs#define VFC_CAM_ADDR_DWORDS CEIL_DWORDS(VFC_CAM_ADDR_STRUCT_SIZE) 431316485Sdavidcs#define VFC_CAM_RESP_DWORDS CEIL_DWORDS(VFC_CAM_RESP_STRUCT_SIZE) 432316485Sdavidcs#define VFC_RAM_CMD_DWORDS VFC_CAM_CMD_DWORDS 433316485Sdavidcs#define VFC_RAM_ADDR_DWORDS CEIL_DWORDS(VFC_RAM_ADDR_STRUCT_SIZE) 434316485Sdavidcs#define VFC_RAM_RESP_DWORDS CEIL_DWORDS(VFC_RAM_RESP_STRUCT_SIZE) 435316485Sdavidcs 436316485Sdavidcs#define NUM_VFC_RAM_TYPES 4 437316485Sdavidcs 438316485Sdavidcs#define VFC_CAM_NUM_ROWS 512 439316485Sdavidcs 440316485Sdavidcs#define VFC_OPCODE_CAM_RD 14 441316485Sdavidcs#define VFC_OPCODE_RAM_RD 0 442316485Sdavidcs 443316485Sdavidcs#define NUM_RSS_MEM_TYPES 5 444316485Sdavidcs 445316485Sdavidcs#define NUM_BIG_RAM_TYPES 3 446316485Sdavidcs 447316485Sdavidcs#define NUM_PHY_TBUS_ADDRESSES 2048 448316485Sdavidcs#define PHY_DUMP_SIZE_DWORDS (NUM_PHY_TBUS_ADDRESSES / 2) 449316485Sdavidcs 450337519Sdavidcs#define SEM_FAST_MODE23_SRC_ENABLE_VAL 0x0 451337519Sdavidcs#define SEM_FAST_MODE23_SRC_DISABLE_VAL 0x7 452337519Sdavidcs#define SEM_FAST_MODE4_SRC_ENABLE_VAL 0x0 453337519Sdavidcs#define SEM_FAST_MODE4_SRC_DISABLE_VAL 0x3 454337519Sdavidcs#define SEM_FAST_MODE6_SRC_ENABLE_VAL 0x10 455337519Sdavidcs#define SEM_FAST_MODE6_SRC_DISABLE_VAL 0x3f 456316485Sdavidcs 457316485Sdavidcs#define SEM_SLOW_MODE1_DATA_ENABLE 0x1 458316485Sdavidcs 459316485Sdavidcs#define VALUES_PER_CYCLE 4 460316485Sdavidcs#define MAX_CYCLE_VALUES_MASK ((1 << VALUES_PER_CYCLE) - 1) 461316485Sdavidcs 462316485Sdavidcs#define MAX_DWORDS_PER_CYCLE 8 463316485Sdavidcs 464316485Sdavidcs#define HW_ID_BITS 3 465316485Sdavidcs 466316485Sdavidcs#define NUM_CALENDAR_SLOTS 16 467316485Sdavidcs 468316485Sdavidcs#define MAX_TRIGGER_STATES 3 469316485Sdavidcs#define TRIGGER_SETS_PER_STATE 2 470316485Sdavidcs#define MAX_CONSTRAINTS 4 471316485Sdavidcs 472337519Sdavidcs#define SEM_FILTER_CID_EN_MASK 0x00b 473337519Sdavidcs#define SEM_FILTER_EID_MASK_EN_MASK 0x013 474337519Sdavidcs#define SEM_FILTER_EID_RANGE_EN_MASK 0x113 475316485Sdavidcs 476316485Sdavidcs#define CHUNK_SIZE_IN_DWORDS 64 477316485Sdavidcs#define CHUNK_SIZE_IN_BYTES DWORDS_TO_BYTES(CHUNK_SIZE_IN_DWORDS) 478316485Sdavidcs 479316485Sdavidcs#define INT_BUF_NUM_OF_LINES 192 480316485Sdavidcs#define INT_BUF_LINE_SIZE_IN_DWORDS 16 481316485Sdavidcs#define INT_BUF_SIZE_IN_DWORDS (INT_BUF_NUM_OF_LINES * INT_BUF_LINE_SIZE_IN_DWORDS) 482316485Sdavidcs#define INT_BUF_SIZE_IN_CHUNKS (INT_BUF_SIZE_IN_DWORDS / CHUNK_SIZE_IN_DWORDS) 483316485Sdavidcs 484316485Sdavidcs#define PCI_BUF_LINE_SIZE_IN_DWORDS 8 485316485Sdavidcs#define PCI_BUF_LINE_SIZE_IN_BYTES DWORDS_TO_BYTES(PCI_BUF_LINE_SIZE_IN_DWORDS) 486316485Sdavidcs 487316485Sdavidcs#define TARGET_EN_MASK_PCI 0x3 488316485Sdavidcs#define TARGET_EN_MASK_NIG 0x4 489316485Sdavidcs 490316485Sdavidcs#define PCI_REQ_CREDIT 1 491316485Sdavidcs#define PCI_PHYS_ADDR_TYPE 0 492316485Sdavidcs 493316485Sdavidcs#define OPAQUE_FID(pci_func) ((pci_func << 4) | 0xff00) 494316485Sdavidcs 495316485Sdavidcs#define RESET_REG_UNRESET_OFFSET 4 496316485Sdavidcs 497316485Sdavidcs#define PCI_PKT_SIZE_IN_CHUNKS 1 498316485Sdavidcs#define PCI_PKT_SIZE_IN_BYTES (PCI_PKT_SIZE_IN_CHUNKS * CHUNK_SIZE_IN_BYTES) 499316485Sdavidcs 500316485Sdavidcs#define NIG_PKT_SIZE_IN_CHUNKS 4 501316485Sdavidcs 502316485Sdavidcs#define FLUSH_DELAY_MS 500 503316485Sdavidcs#define STALL_DELAY_MS 500 504316485Sdavidcs 505316485Sdavidcs#define SRC_MAC_ADDR_LO16 0x0a0b 506316485Sdavidcs#define SRC_MAC_ADDR_HI32 0x0c0d0e0f 507316485Sdavidcs#define ETH_TYPE 0x1000 508316485Sdavidcs 509316485Sdavidcs#define STATIC_DEBUG_LINE_DWORDS 9 510316485Sdavidcs 511316485Sdavidcs#define NUM_COMMON_GLOBAL_PARAMS 8 512316485Sdavidcs 513316485Sdavidcs#define FW_IMG_KUKU 0 514316485Sdavidcs#define FW_IMG_MAIN 1 515316485Sdavidcs#define FW_IMG_L2B 2 516316485Sdavidcs 517316485Sdavidcs#ifndef REG_FIFO_ELEMENT_DWORDS 518316485Sdavidcs#define REG_FIFO_ELEMENT_DWORDS 2 519316485Sdavidcs#endif 520316485Sdavidcs#define REG_FIFO_DEPTH_ELEMENTS 32 521316485Sdavidcs#define REG_FIFO_DEPTH_DWORDS (REG_FIFO_ELEMENT_DWORDS * REG_FIFO_DEPTH_ELEMENTS) 522316485Sdavidcs 523316485Sdavidcs#ifndef IGU_FIFO_ELEMENT_DWORDS 524316485Sdavidcs#define IGU_FIFO_ELEMENT_DWORDS 4 525316485Sdavidcs#endif 526316485Sdavidcs#define IGU_FIFO_DEPTH_ELEMENTS 64 527316485Sdavidcs#define IGU_FIFO_DEPTH_DWORDS (IGU_FIFO_ELEMENT_DWORDS * IGU_FIFO_DEPTH_ELEMENTS) 528316485Sdavidcs 529316485Sdavidcs#define SEMI_SYNC_FIFO_POLLING_DELAY_MS 5 530316485Sdavidcs#define SEMI_SYNC_FIFO_POLLING_COUNT 20 531316485Sdavidcs 532316485Sdavidcs#ifndef PROTECTION_OVERRIDE_ELEMENT_DWORDS 533316485Sdavidcs#define PROTECTION_OVERRIDE_ELEMENT_DWORDS 2 534316485Sdavidcs#endif 535316485Sdavidcs#define PROTECTION_OVERRIDE_DEPTH_ELEMENTS 20 536316485Sdavidcs#define PROTECTION_OVERRIDE_DEPTH_DWORDS (PROTECTION_OVERRIDE_DEPTH_ELEMENTS * PROTECTION_OVERRIDE_ELEMENT_DWORDS) 537316485Sdavidcs 538316485Sdavidcs#define MCP_SPAD_TRACE_OFFSIZE_ADDR (MCP_REG_SCRATCH + OFFSETOF(struct static_init, sections[SPAD_SECTION_TRACE])) 539316485Sdavidcs 540316485Sdavidcs#define EMPTY_FW_VERSION_STR "???_???_???_???" 541316485Sdavidcs#define EMPTY_FW_IMAGE_STR "???????????????" 542316485Sdavidcs 543316485Sdavidcs 544316485Sdavidcs/***************************** Constant Arrays *******************************/ 545316485Sdavidcs 546316485Sdavidcsstruct dbg_array { 547316485Sdavidcs const u32 *ptr; 548316485Sdavidcs u32 size_in_dwords; 549316485Sdavidcs}; 550316485Sdavidcs 551316485Sdavidcs/* Debug arrays */ 552316485Sdavidcs#ifdef USE_DBG_BIN_FILE 553316485Sdavidcsstatic struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { { OSAL_NULL } }; 554316485Sdavidcs#else 555316485Sdavidcsstatic struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { 556316485Sdavidcs 557316485Sdavidcs /* BIN_BUF_DBG_MODE_TREE */ 558337519Sdavidcs { (const u32 *)dbg_modes_tree_buf, OSAL_ARRAY_SIZE(dbg_modes_tree_buf)}, 559316485Sdavidcs 560316485Sdavidcs /* BIN_BUF_DBG_DUMP_REG */ 561316485Sdavidcs { dump_reg, OSAL_ARRAY_SIZE(dump_reg) }, 562316485Sdavidcs 563316485Sdavidcs /* BIN_BUF_DBG_DUMP_MEM */ 564316485Sdavidcs { dump_mem, OSAL_ARRAY_SIZE(dump_mem) }, 565316485Sdavidcs 566316485Sdavidcs /* BIN_BUF_DBG_IDLE_CHK_REGS */ 567316485Sdavidcs { idle_chk_regs, OSAL_ARRAY_SIZE(idle_chk_regs) }, 568316485Sdavidcs 569316485Sdavidcs /* BIN_BUF_DBG_IDLE_CHK_IMMS */ 570316485Sdavidcs { idle_chk_imms, OSAL_ARRAY_SIZE(idle_chk_imms) }, 571316485Sdavidcs 572316485Sdavidcs /* BIN_BUF_DBG_IDLE_CHK_RULES */ 573316485Sdavidcs { idle_chk_rules, OSAL_ARRAY_SIZE(idle_chk_rules) }, 574316485Sdavidcs 575316485Sdavidcs /* BIN_BUF_DBG_IDLE_CHK_PARSING_DATA */ 576316485Sdavidcs { OSAL_NULL, 0 }, 577316485Sdavidcs 578316485Sdavidcs /* BIN_BUF_DBG_ATTN_BLOCKS */ 579316485Sdavidcs { attn_block, OSAL_ARRAY_SIZE(attn_block) }, 580316485Sdavidcs 581316485Sdavidcs /* BIN_BUF_DBG_ATTN_REGSS */ 582316485Sdavidcs { attn_reg, OSAL_ARRAY_SIZE(attn_reg) }, 583316485Sdavidcs 584316485Sdavidcs /* BIN_BUF_DBG_ATTN_INDEXES */ 585316485Sdavidcs { OSAL_NULL, 0 }, 586316485Sdavidcs 587316485Sdavidcs /* BIN_BUF_DBG_ATTN_NAME_OFFSETS */ 588316485Sdavidcs { OSAL_NULL, 0 }, 589316485Sdavidcs 590316485Sdavidcs /* BIN_BUF_DBG_BUS_BLOCKS */ 591316485Sdavidcs { dbg_bus_blocks, OSAL_ARRAY_SIZE(dbg_bus_blocks) }, 592316485Sdavidcs 593316485Sdavidcs /* BIN_BUF_DBG_BUS_LINES */ 594316485Sdavidcs { dbg_bus_lines, OSAL_ARRAY_SIZE(dbg_bus_lines) }, 595316485Sdavidcs 596316485Sdavidcs /* BIN_BUF_DBG_BUS_BLOCKS_USER_DATA */ 597316485Sdavidcs { OSAL_NULL, 0 }, 598316485Sdavidcs 599316485Sdavidcs /* BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS */ 600316485Sdavidcs { OSAL_NULL, 0 }, 601316485Sdavidcs 602316485Sdavidcs /* BIN_BUF_DBG_PARSING_STRINGS */ 603316485Sdavidcs { OSAL_NULL, 0 } 604316485Sdavidcs}; 605316485Sdavidcs#endif 606316485Sdavidcs 607316485Sdavidcs/* Chip constant definitions array */ 608316485Sdavidcsstatic struct chip_defs s_chip_defs[MAX_CHIP_IDS] = { 609316485Sdavidcs { "bb", 610316485Sdavidcs 611316485Sdavidcs /* ASIC */ 612316485Sdavidcs { { MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB }, 613316485Sdavidcs 614316485Sdavidcs /* EMUL_FULL */ 615316485Sdavidcs { MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB }, 616316485Sdavidcs 617316485Sdavidcs /* EMUL_REDUCED */ 618316485Sdavidcs { MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB }, 619316485Sdavidcs 620316485Sdavidcs /* FPGA */ 621316485Sdavidcs { MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB } } }, 622316485Sdavidcs 623320162Sdavidcs { "ah", 624316485Sdavidcs 625316485Sdavidcs /* ASIC */ 626316485Sdavidcs { { MAX_NUM_PORTS_K2, MAX_NUM_PFS_K2, MAX_NUM_VFS_K2 }, 627316485Sdavidcs 628316485Sdavidcs /* EMUL_FULL */ 629316485Sdavidcs { MAX_NUM_PORTS_K2, MAX_NUM_PFS_K2, MAX_NUM_VFS_K2 }, 630316485Sdavidcs 631316485Sdavidcs /* EMUL_REDUCED */ 632316485Sdavidcs { MAX_NUM_PORTS_K2, MAX_NUM_PFS_K2, MAX_NUM_VFS_K2 }, 633316485Sdavidcs 634316485Sdavidcs /* FPGA */ 635320162Sdavidcs { MAX_NUM_PORTS_K2, 8, MAX_NUM_VFS_K2 } } }, 636320162Sdavidcs 637320162Sdavidcs { "e5", 638320162Sdavidcs 639320162Sdavidcs /* ASIC */ 640320162Sdavidcs { { MAX_NUM_PORTS_E5, MAX_NUM_PFS_E5, MAX_NUM_VFS_E5 }, 641320162Sdavidcs 642320162Sdavidcs /* EMUL_FULL */ 643320162Sdavidcs { MAX_NUM_PORTS_E5, MAX_NUM_PFS_E5, MAX_NUM_VFS_E5 }, 644320162Sdavidcs 645320162Sdavidcs /* EMUL_REDUCED */ 646320162Sdavidcs { MAX_NUM_PORTS_E5, MAX_NUM_PFS_E5, MAX_NUM_VFS_E5 }, 647320162Sdavidcs 648320162Sdavidcs /* FPGA */ 649320162Sdavidcs { MAX_NUM_PORTS_E5, 8, MAX_NUM_VFS_E5 } } } 650316485Sdavidcs}; 651316485Sdavidcs 652316485Sdavidcs/* Storm constant definitions array */ 653316485Sdavidcsstatic struct storm_defs s_storm_defs[] = { 654316485Sdavidcs 655316485Sdavidcs /* Tstorm */ 656316485Sdavidcs { 'T', BLOCK_TSEM, 657320162Sdavidcs { DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT }, true, 658316485Sdavidcs TSEM_REG_FAST_MEMORY, 659316485Sdavidcs TSEM_REG_DBG_FRAME_MODE_BB_K2, TSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 660316485Sdavidcs TSEM_REG_SLOW_DBG_MODE_BB_K2, TSEM_REG_DBG_MODE1_CFG_BB_K2, 661316485Sdavidcs TSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2, 662316485Sdavidcs TCM_REG_CTX_RBC_ACCS, 663316485Sdavidcs 4, TCM_REG_AGG_CON_CTX, 664316485Sdavidcs 16, TCM_REG_SM_CON_CTX, 665316485Sdavidcs 2, TCM_REG_AGG_TASK_CTX, 666316485Sdavidcs 4, TCM_REG_SM_TASK_CTX }, 667316485Sdavidcs 668316485Sdavidcs /* Mstorm */ 669316485Sdavidcs { 'M', BLOCK_MSEM, 670320162Sdavidcs { DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM }, false, 671316485Sdavidcs MSEM_REG_FAST_MEMORY, 672316485Sdavidcs MSEM_REG_DBG_FRAME_MODE_BB_K2, MSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 673316485Sdavidcs MSEM_REG_SLOW_DBG_MODE_BB_K2, MSEM_REG_DBG_MODE1_CFG_BB_K2, 674316485Sdavidcs MSEM_REG_SYNC_DBG_EMPTY, MSEM_REG_SLOW_DBG_EMPTY_BB_K2, 675316485Sdavidcs MCM_REG_CTX_RBC_ACCS, 676316485Sdavidcs 1, MCM_REG_AGG_CON_CTX, 677316485Sdavidcs 10, MCM_REG_SM_CON_CTX, 678316485Sdavidcs 2, MCM_REG_AGG_TASK_CTX, 679316485Sdavidcs 7, MCM_REG_SM_TASK_CTX }, 680316485Sdavidcs 681316485Sdavidcs /* Ustorm */ 682316485Sdavidcs { 'U', BLOCK_USEM, 683320162Sdavidcs { DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU }, false, 684316485Sdavidcs USEM_REG_FAST_MEMORY, 685316485Sdavidcs USEM_REG_DBG_FRAME_MODE_BB_K2, USEM_REG_SLOW_DBG_ACTIVE_BB_K2, 686316485Sdavidcs USEM_REG_SLOW_DBG_MODE_BB_K2, USEM_REG_DBG_MODE1_CFG_BB_K2, 687316485Sdavidcs USEM_REG_SYNC_DBG_EMPTY, USEM_REG_SLOW_DBG_EMPTY_BB_K2, 688316485Sdavidcs UCM_REG_CTX_RBC_ACCS, 689316485Sdavidcs 2, UCM_REG_AGG_CON_CTX, 690316485Sdavidcs 13, UCM_REG_SM_CON_CTX, 691316485Sdavidcs 3, UCM_REG_AGG_TASK_CTX, 692316485Sdavidcs 3, UCM_REG_SM_TASK_CTX }, 693316485Sdavidcs 694316485Sdavidcs /* Xstorm */ 695316485Sdavidcs { 'X', BLOCK_XSEM, 696320162Sdavidcs { DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX }, false, 697316485Sdavidcs XSEM_REG_FAST_MEMORY, 698316485Sdavidcs XSEM_REG_DBG_FRAME_MODE_BB_K2, XSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 699316485Sdavidcs XSEM_REG_SLOW_DBG_MODE_BB_K2, XSEM_REG_DBG_MODE1_CFG_BB_K2, 700316485Sdavidcs XSEM_REG_SYNC_DBG_EMPTY, XSEM_REG_SLOW_DBG_EMPTY_BB_K2, 701316485Sdavidcs XCM_REG_CTX_RBC_ACCS, 702316485Sdavidcs 9, XCM_REG_AGG_CON_CTX, 703316485Sdavidcs 15, XCM_REG_SM_CON_CTX, 704316485Sdavidcs 0, 0, 705316485Sdavidcs 0, 0 }, 706316485Sdavidcs 707316485Sdavidcs /* Ystorm */ 708316485Sdavidcs { 'Y', BLOCK_YSEM, 709320162Sdavidcs { DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY }, false, 710316485Sdavidcs YSEM_REG_FAST_MEMORY, 711316485Sdavidcs YSEM_REG_DBG_FRAME_MODE_BB_K2, YSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 712316485Sdavidcs YSEM_REG_SLOW_DBG_MODE_BB_K2, YSEM_REG_DBG_MODE1_CFG_BB_K2, 713316485Sdavidcs YSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2, 714316485Sdavidcs YCM_REG_CTX_RBC_ACCS, 715316485Sdavidcs 2, YCM_REG_AGG_CON_CTX, 716316485Sdavidcs 3, YCM_REG_SM_CON_CTX, 717316485Sdavidcs 2, YCM_REG_AGG_TASK_CTX, 718316485Sdavidcs 12, YCM_REG_SM_TASK_CTX }, 719316485Sdavidcs 720316485Sdavidcs /* Pstorm */ 721316485Sdavidcs { 'P', BLOCK_PSEM, 722320162Sdavidcs { DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS }, true, 723316485Sdavidcs PSEM_REG_FAST_MEMORY, 724316485Sdavidcs PSEM_REG_DBG_FRAME_MODE_BB_K2, PSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 725316485Sdavidcs PSEM_REG_SLOW_DBG_MODE_BB_K2, PSEM_REG_DBG_MODE1_CFG_BB_K2, 726316485Sdavidcs PSEM_REG_SYNC_DBG_EMPTY, PSEM_REG_SLOW_DBG_EMPTY_BB_K2, 727316485Sdavidcs PCM_REG_CTX_RBC_ACCS, 728316485Sdavidcs 0, 0, 729316485Sdavidcs 10, PCM_REG_SM_CON_CTX, 730316485Sdavidcs 0, 0, 731316485Sdavidcs 0, 0 } 732316485Sdavidcs}; 733316485Sdavidcs 734316485Sdavidcs/* Block definitions array */ 735316485Sdavidcs 736316485Sdavidcsstatic struct block_defs block_grc_defs = { 737320162Sdavidcs "grc", { true, true, true }, false, 0, 738320162Sdavidcs { DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN }, 739316485Sdavidcs GRC_REG_DBG_SELECT, GRC_REG_DBG_DWORD_ENABLE, 740316485Sdavidcs GRC_REG_DBG_SHIFT, GRC_REG_DBG_FORCE_VALID, 741316485Sdavidcs GRC_REG_DBG_FORCE_FRAME, 742316485Sdavidcs true, false, DBG_RESET_REG_MISC_PL_UA, 1 }; 743316485Sdavidcs 744316485Sdavidcsstatic struct block_defs block_miscs_defs = { 745320162Sdavidcs "miscs", { true, true, true }, false, 0, 746320162Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 747316485Sdavidcs 0, 0, 0, 0, 0, 748316485Sdavidcs false, false, MAX_DBG_RESET_REGS, 0 }; 749316485Sdavidcs 750316485Sdavidcsstatic struct block_defs block_misc_defs = { 751320162Sdavidcs "misc", { true, true, true }, false, 0, 752320162Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 753316485Sdavidcs 0, 0, 0, 0, 0, 754316485Sdavidcs false, false, MAX_DBG_RESET_REGS, 0 }; 755316485Sdavidcs 756316485Sdavidcsstatic struct block_defs block_dbu_defs = { 757320162Sdavidcs "dbu", { true, true, true }, false, 0, 758320162Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 759316485Sdavidcs 0, 0, 0, 0, 0, 760316485Sdavidcs false, false, MAX_DBG_RESET_REGS, 0 }; 761316485Sdavidcs 762316485Sdavidcsstatic struct block_defs block_pglue_b_defs = { 763320162Sdavidcs "pglue_b", { true, true, true }, false, 0, 764320162Sdavidcs { DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH }, 765316485Sdavidcs PGLUE_B_REG_DBG_SELECT, PGLUE_B_REG_DBG_DWORD_ENABLE, 766316485Sdavidcs PGLUE_B_REG_DBG_SHIFT, PGLUE_B_REG_DBG_FORCE_VALID, 767316485Sdavidcs PGLUE_B_REG_DBG_FORCE_FRAME, 768316485Sdavidcs true, false, DBG_RESET_REG_MISCS_PL_HV, 1 }; 769316485Sdavidcs 770316485Sdavidcsstatic struct block_defs block_cnig_defs = { 771320162Sdavidcs "cnig", { true, true, true }, false, 0, 772320162Sdavidcs { MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW }, 773316485Sdavidcs CNIG_REG_DBG_SELECT_K2_E5, CNIG_REG_DBG_DWORD_ENABLE_K2_E5, 774316485Sdavidcs CNIG_REG_DBG_SHIFT_K2_E5, CNIG_REG_DBG_FORCE_VALID_K2_E5, 775316485Sdavidcs CNIG_REG_DBG_FORCE_FRAME_K2_E5, 776316485Sdavidcs true, false, DBG_RESET_REG_MISCS_PL_HV, 0 }; 777316485Sdavidcs 778316485Sdavidcsstatic struct block_defs block_cpmu_defs = { 779320162Sdavidcs "cpmu", { true, true, true }, false, 0, 780320162Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 781316485Sdavidcs 0, 0, 0, 0, 0, 782316485Sdavidcs true, false, DBG_RESET_REG_MISCS_PL_HV, 8 }; 783316485Sdavidcs 784316485Sdavidcsstatic struct block_defs block_ncsi_defs = { 785320162Sdavidcs "ncsi", { true, true, true }, false, 0, 786320162Sdavidcs { DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ }, 787316485Sdavidcs NCSI_REG_DBG_SELECT, NCSI_REG_DBG_DWORD_ENABLE, 788316485Sdavidcs NCSI_REG_DBG_SHIFT, NCSI_REG_DBG_FORCE_VALID, 789316485Sdavidcs NCSI_REG_DBG_FORCE_FRAME, 790316485Sdavidcs true, false, DBG_RESET_REG_MISCS_PL_HV, 5 }; 791316485Sdavidcs 792316485Sdavidcsstatic struct block_defs block_opte_defs = { 793320162Sdavidcs "opte", { true, true, false }, false, 0, 794320162Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 795316485Sdavidcs 0, 0, 0, 0, 0, 796316485Sdavidcs true, false, DBG_RESET_REG_MISCS_PL_HV, 4 }; 797316485Sdavidcs 798316485Sdavidcsstatic struct block_defs block_bmb_defs = { 799320162Sdavidcs "bmb", { true, true, true }, false, 0, 800320162Sdavidcs { DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCB, DBG_BUS_CLIENT_RBCB }, 801316485Sdavidcs BMB_REG_DBG_SELECT, BMB_REG_DBG_DWORD_ENABLE, 802316485Sdavidcs BMB_REG_DBG_SHIFT, BMB_REG_DBG_FORCE_VALID, 803316485Sdavidcs BMB_REG_DBG_FORCE_FRAME, 804316485Sdavidcs true, false, DBG_RESET_REG_MISCS_PL_UA, 7 }; 805316485Sdavidcs 806316485Sdavidcsstatic struct block_defs block_pcie_defs = { 807320162Sdavidcs "pcie", { true, true, true }, false, 0, 808320162Sdavidcs { MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH }, 809316485Sdavidcs PCIE_REG_DBG_COMMON_SELECT_K2_E5, PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5, 810316485Sdavidcs PCIE_REG_DBG_COMMON_SHIFT_K2_E5, PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5, 811316485Sdavidcs PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5, 812316485Sdavidcs false, false, MAX_DBG_RESET_REGS, 0 }; 813316485Sdavidcs 814316485Sdavidcsstatic struct block_defs block_mcp_defs = { 815320162Sdavidcs "mcp", { true, true, true }, false, 0, 816320162Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 817316485Sdavidcs 0, 0, 0, 0, 0, 818316485Sdavidcs false, false, MAX_DBG_RESET_REGS, 0 }; 819316485Sdavidcs 820316485Sdavidcsstatic struct block_defs block_mcp2_defs = { 821320162Sdavidcs "mcp2", { true, true, true }, false, 0, 822320162Sdavidcs { DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ }, 823316485Sdavidcs MCP2_REG_DBG_SELECT, MCP2_REG_DBG_DWORD_ENABLE, 824316485Sdavidcs MCP2_REG_DBG_SHIFT, MCP2_REG_DBG_FORCE_VALID, 825316485Sdavidcs MCP2_REG_DBG_FORCE_FRAME, 826316485Sdavidcs false, false, MAX_DBG_RESET_REGS, 0 }; 827316485Sdavidcs 828316485Sdavidcsstatic struct block_defs block_pswhst_defs = { 829320162Sdavidcs "pswhst", { true, true, true }, false, 0, 830320162Sdavidcs { DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP }, 831316485Sdavidcs PSWHST_REG_DBG_SELECT, PSWHST_REG_DBG_DWORD_ENABLE, 832316485Sdavidcs PSWHST_REG_DBG_SHIFT, PSWHST_REG_DBG_FORCE_VALID, 833316485Sdavidcs PSWHST_REG_DBG_FORCE_FRAME, 834316485Sdavidcs true, false, DBG_RESET_REG_MISC_PL_HV, 0 }; 835316485Sdavidcs 836316485Sdavidcsstatic struct block_defs block_pswhst2_defs = { 837320162Sdavidcs "pswhst2", { true, true, true }, false, 0, 838320162Sdavidcs { DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP }, 839316485Sdavidcs PSWHST2_REG_DBG_SELECT, PSWHST2_REG_DBG_DWORD_ENABLE, 840316485Sdavidcs PSWHST2_REG_DBG_SHIFT, PSWHST2_REG_DBG_FORCE_VALID, 841316485Sdavidcs PSWHST2_REG_DBG_FORCE_FRAME, 842316485Sdavidcs true, false, DBG_RESET_REG_MISC_PL_HV, 0 }; 843316485Sdavidcs 844316485Sdavidcsstatic struct block_defs block_pswrd_defs = { 845320162Sdavidcs "pswrd", { true, true, true }, false, 0, 846320162Sdavidcs { DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP }, 847316485Sdavidcs PSWRD_REG_DBG_SELECT, PSWRD_REG_DBG_DWORD_ENABLE, 848316485Sdavidcs PSWRD_REG_DBG_SHIFT, PSWRD_REG_DBG_FORCE_VALID, 849316485Sdavidcs PSWRD_REG_DBG_FORCE_FRAME, 850316485Sdavidcs true, false, DBG_RESET_REG_MISC_PL_HV, 2 }; 851316485Sdavidcs 852316485Sdavidcsstatic struct block_defs block_pswrd2_defs = { 853320162Sdavidcs "pswrd2", { true, true, true }, false, 0, 854320162Sdavidcs { DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP }, 855316485Sdavidcs PSWRD2_REG_DBG_SELECT, PSWRD2_REG_DBG_DWORD_ENABLE, 856316485Sdavidcs PSWRD2_REG_DBG_SHIFT, PSWRD2_REG_DBG_FORCE_VALID, 857316485Sdavidcs PSWRD2_REG_DBG_FORCE_FRAME, 858316485Sdavidcs true, false, DBG_RESET_REG_MISC_PL_HV, 2 }; 859316485Sdavidcs 860316485Sdavidcsstatic struct block_defs block_pswwr_defs = { 861320162Sdavidcs "pswwr", { true, true, true }, false, 0, 862320162Sdavidcs { DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP }, 863316485Sdavidcs PSWWR_REG_DBG_SELECT, PSWWR_REG_DBG_DWORD_ENABLE, 864316485Sdavidcs PSWWR_REG_DBG_SHIFT, PSWWR_REG_DBG_FORCE_VALID, 865316485Sdavidcs PSWWR_REG_DBG_FORCE_FRAME, 866316485Sdavidcs true, false, DBG_RESET_REG_MISC_PL_HV, 3 }; 867316485Sdavidcs 868316485Sdavidcsstatic struct block_defs block_pswwr2_defs = { 869320162Sdavidcs "pswwr2", { true, true, true }, false, 0, 870320162Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 871316485Sdavidcs 0, 0, 0, 0, 0, 872316485Sdavidcs true, false, DBG_RESET_REG_MISC_PL_HV, 3 }; 873316485Sdavidcs 874316485Sdavidcsstatic struct block_defs block_pswrq_defs = { 875320162Sdavidcs "pswrq", { true, true, true }, false, 0, 876320162Sdavidcs { DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP }, 877316485Sdavidcs PSWRQ_REG_DBG_SELECT, PSWRQ_REG_DBG_DWORD_ENABLE, 878316485Sdavidcs PSWRQ_REG_DBG_SHIFT, PSWRQ_REG_DBG_FORCE_VALID, 879316485Sdavidcs PSWRQ_REG_DBG_FORCE_FRAME, 880316485Sdavidcs true, false, DBG_RESET_REG_MISC_PL_HV, 1 }; 881316485Sdavidcs 882316485Sdavidcsstatic struct block_defs block_pswrq2_defs = { 883320162Sdavidcs "pswrq2", { true, true, true }, false, 0, 884320162Sdavidcs { DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP }, 885316485Sdavidcs PSWRQ2_REG_DBG_SELECT, PSWRQ2_REG_DBG_DWORD_ENABLE, 886316485Sdavidcs PSWRQ2_REG_DBG_SHIFT, PSWRQ2_REG_DBG_FORCE_VALID, 887316485Sdavidcs PSWRQ2_REG_DBG_FORCE_FRAME, 888316485Sdavidcs true, false, DBG_RESET_REG_MISC_PL_HV, 1 }; 889316485Sdavidcs 890316485Sdavidcsstatic struct block_defs block_pglcs_defs = { 891320162Sdavidcs "pglcs", { true, true, true }, false, 0, 892320162Sdavidcs { MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH }, 893316485Sdavidcs PGLCS_REG_DBG_SELECT_K2_E5, PGLCS_REG_DBG_DWORD_ENABLE_K2_E5, 894316485Sdavidcs PGLCS_REG_DBG_SHIFT_K2_E5, PGLCS_REG_DBG_FORCE_VALID_K2_E5, 895316485Sdavidcs PGLCS_REG_DBG_FORCE_FRAME_K2_E5, 896316485Sdavidcs true, false, DBG_RESET_REG_MISCS_PL_HV, 2 }; 897316485Sdavidcs 898316485Sdavidcsstatic struct block_defs block_ptu_defs ={ 899320162Sdavidcs "ptu", { true, true, true }, false, 0, 900320162Sdavidcs { DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP }, 901316485Sdavidcs PTU_REG_DBG_SELECT, PTU_REG_DBG_DWORD_ENABLE, 902316485Sdavidcs PTU_REG_DBG_SHIFT, PTU_REG_DBG_FORCE_VALID, 903316485Sdavidcs PTU_REG_DBG_FORCE_FRAME, 904316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 20 }; 905316485Sdavidcs 906316485Sdavidcsstatic struct block_defs block_dmae_defs = { 907320162Sdavidcs "dmae", { true, true, true }, false, 0, 908320162Sdavidcs { DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP }, 909316485Sdavidcs DMAE_REG_DBG_SELECT, DMAE_REG_DBG_DWORD_ENABLE, 910316485Sdavidcs DMAE_REG_DBG_SHIFT, DMAE_REG_DBG_FORCE_VALID, 911316485Sdavidcs DMAE_REG_DBG_FORCE_FRAME, 912316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 28 }; 913316485Sdavidcs 914316485Sdavidcsstatic struct block_defs block_tcm_defs = { 915320162Sdavidcs "tcm", { true, true, true }, true, DBG_TSTORM_ID, 916320162Sdavidcs { DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT }, 917316485Sdavidcs TCM_REG_DBG_SELECT, TCM_REG_DBG_DWORD_ENABLE, 918316485Sdavidcs TCM_REG_DBG_SHIFT, TCM_REG_DBG_FORCE_VALID, 919316485Sdavidcs TCM_REG_DBG_FORCE_FRAME, 920316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 5 }; 921316485Sdavidcs 922316485Sdavidcsstatic struct block_defs block_mcm_defs = { 923320162Sdavidcs "mcm", { true, true, true }, true, DBG_MSTORM_ID, 924320162Sdavidcs { DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM }, 925316485Sdavidcs MCM_REG_DBG_SELECT, MCM_REG_DBG_DWORD_ENABLE, 926316485Sdavidcs MCM_REG_DBG_SHIFT, MCM_REG_DBG_FORCE_VALID, 927316485Sdavidcs MCM_REG_DBG_FORCE_FRAME, 928316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 3 }; 929316485Sdavidcs 930316485Sdavidcsstatic struct block_defs block_ucm_defs = { 931320162Sdavidcs "ucm", { true, true, true }, true, DBG_USTORM_ID, 932320162Sdavidcs { DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU }, 933316485Sdavidcs UCM_REG_DBG_SELECT, UCM_REG_DBG_DWORD_ENABLE, 934316485Sdavidcs UCM_REG_DBG_SHIFT, UCM_REG_DBG_FORCE_VALID, 935316485Sdavidcs UCM_REG_DBG_FORCE_FRAME, 936316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 8 }; 937316485Sdavidcs 938316485Sdavidcsstatic struct block_defs block_xcm_defs = { 939320162Sdavidcs "xcm", { true, true, true }, true, DBG_XSTORM_ID, 940320162Sdavidcs { DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX }, 941316485Sdavidcs XCM_REG_DBG_SELECT, XCM_REG_DBG_DWORD_ENABLE, 942316485Sdavidcs XCM_REG_DBG_SHIFT, XCM_REG_DBG_FORCE_VALID, 943316485Sdavidcs XCM_REG_DBG_FORCE_FRAME, 944316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 19 }; 945316485Sdavidcs 946316485Sdavidcsstatic struct block_defs block_ycm_defs = { 947320162Sdavidcs "ycm", { true, true, true }, true, DBG_YSTORM_ID, 948320162Sdavidcs { DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY }, 949316485Sdavidcs YCM_REG_DBG_SELECT, YCM_REG_DBG_DWORD_ENABLE, 950316485Sdavidcs YCM_REG_DBG_SHIFT, YCM_REG_DBG_FORCE_VALID, 951316485Sdavidcs YCM_REG_DBG_FORCE_FRAME, 952316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 5 }; 953316485Sdavidcs 954316485Sdavidcsstatic struct block_defs block_pcm_defs = { 955320162Sdavidcs "pcm", { true, true, true }, true, DBG_PSTORM_ID, 956320162Sdavidcs { DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS }, 957316485Sdavidcs PCM_REG_DBG_SELECT, PCM_REG_DBG_DWORD_ENABLE, 958316485Sdavidcs PCM_REG_DBG_SHIFT, PCM_REG_DBG_FORCE_VALID, 959316485Sdavidcs PCM_REG_DBG_FORCE_FRAME, 960316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 4 }; 961316485Sdavidcs 962316485Sdavidcsstatic struct block_defs block_qm_defs = { 963320162Sdavidcs "qm", { true, true, true }, false, 0, 964320162Sdavidcs { DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCQ, DBG_BUS_CLIENT_RBCQ }, 965316485Sdavidcs QM_REG_DBG_SELECT, QM_REG_DBG_DWORD_ENABLE, 966316485Sdavidcs QM_REG_DBG_SHIFT, QM_REG_DBG_FORCE_VALID, 967316485Sdavidcs QM_REG_DBG_FORCE_FRAME, 968316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 16 }; 969316485Sdavidcs 970316485Sdavidcsstatic struct block_defs block_tm_defs = { 971320162Sdavidcs "tm", { true, true, true }, false, 0, 972320162Sdavidcs { DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS }, 973316485Sdavidcs TM_REG_DBG_SELECT, TM_REG_DBG_DWORD_ENABLE, 974316485Sdavidcs TM_REG_DBG_SHIFT, TM_REG_DBG_FORCE_VALID, 975316485Sdavidcs TM_REG_DBG_FORCE_FRAME, 976316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 17 }; 977316485Sdavidcs 978316485Sdavidcsstatic struct block_defs block_dorq_defs = { 979320162Sdavidcs "dorq", { true, true, true }, false, 0, 980320162Sdavidcs { DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY }, 981316485Sdavidcs DORQ_REG_DBG_SELECT, DORQ_REG_DBG_DWORD_ENABLE, 982316485Sdavidcs DORQ_REG_DBG_SHIFT, DORQ_REG_DBG_FORCE_VALID, 983316485Sdavidcs DORQ_REG_DBG_FORCE_FRAME, 984316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 18 }; 985316485Sdavidcs 986316485Sdavidcsstatic struct block_defs block_brb_defs = { 987320162Sdavidcs "brb", { true, true, true }, false, 0, 988320162Sdavidcs { DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR }, 989316485Sdavidcs BRB_REG_DBG_SELECT, BRB_REG_DBG_DWORD_ENABLE, 990316485Sdavidcs BRB_REG_DBG_SHIFT, BRB_REG_DBG_FORCE_VALID, 991316485Sdavidcs BRB_REG_DBG_FORCE_FRAME, 992316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 0 }; 993316485Sdavidcs 994316485Sdavidcsstatic struct block_defs block_src_defs = { 995320162Sdavidcs "src", { true, true, true }, false, 0, 996320162Sdavidcs { DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF }, 997316485Sdavidcs SRC_REG_DBG_SELECT, SRC_REG_DBG_DWORD_ENABLE, 998316485Sdavidcs SRC_REG_DBG_SHIFT, SRC_REG_DBG_FORCE_VALID, 999316485Sdavidcs SRC_REG_DBG_FORCE_FRAME, 1000316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 2 }; 1001316485Sdavidcs 1002316485Sdavidcsstatic struct block_defs block_prs_defs = { 1003320162Sdavidcs "prs", { true, true, true }, false, 0, 1004320162Sdavidcs { DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR }, 1005316485Sdavidcs PRS_REG_DBG_SELECT, PRS_REG_DBG_DWORD_ENABLE, 1006316485Sdavidcs PRS_REG_DBG_SHIFT, PRS_REG_DBG_FORCE_VALID, 1007316485Sdavidcs PRS_REG_DBG_FORCE_FRAME, 1008316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1 }; 1009316485Sdavidcs 1010316485Sdavidcsstatic struct block_defs block_tsdm_defs = { 1011320162Sdavidcs "tsdm", { true, true, true }, true, DBG_TSTORM_ID, 1012320162Sdavidcs { DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT }, 1013316485Sdavidcs TSDM_REG_DBG_SELECT, TSDM_REG_DBG_DWORD_ENABLE, 1014316485Sdavidcs TSDM_REG_DBG_SHIFT, TSDM_REG_DBG_FORCE_VALID, 1015316485Sdavidcs TSDM_REG_DBG_FORCE_FRAME, 1016316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 3 }; 1017316485Sdavidcs 1018316485Sdavidcsstatic struct block_defs block_msdm_defs = { 1019320162Sdavidcs "msdm", { true, true, true }, true, DBG_MSTORM_ID, 1020320162Sdavidcs { DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM }, 1021316485Sdavidcs MSDM_REG_DBG_SELECT, MSDM_REG_DBG_DWORD_ENABLE, 1022316485Sdavidcs MSDM_REG_DBG_SHIFT, MSDM_REG_DBG_FORCE_VALID, 1023316485Sdavidcs MSDM_REG_DBG_FORCE_FRAME, 1024316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 6 }; 1025316485Sdavidcs 1026316485Sdavidcsstatic struct block_defs block_usdm_defs = { 1027320162Sdavidcs "usdm", { true, true, true }, true, DBG_USTORM_ID, 1028320162Sdavidcs { DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU }, 1029316485Sdavidcs USDM_REG_DBG_SELECT, USDM_REG_DBG_DWORD_ENABLE, 1030316485Sdavidcs USDM_REG_DBG_SHIFT, USDM_REG_DBG_FORCE_VALID, 1031316485Sdavidcs USDM_REG_DBG_FORCE_FRAME, 1032316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 7 1033316485Sdavidcs }; 1034316485Sdavidcsstatic struct block_defs block_xsdm_defs = { 1035320162Sdavidcs "xsdm", { true, true, true }, true, DBG_XSTORM_ID, 1036320162Sdavidcs { DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX }, 1037316485Sdavidcs XSDM_REG_DBG_SELECT, XSDM_REG_DBG_DWORD_ENABLE, 1038316485Sdavidcs XSDM_REG_DBG_SHIFT, XSDM_REG_DBG_FORCE_VALID, 1039316485Sdavidcs XSDM_REG_DBG_FORCE_FRAME, 1040316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 20 }; 1041316485Sdavidcs 1042316485Sdavidcsstatic struct block_defs block_ysdm_defs = { 1043320162Sdavidcs "ysdm", { true, true, true }, true, DBG_YSTORM_ID, 1044320162Sdavidcs { DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY }, 1045316485Sdavidcs YSDM_REG_DBG_SELECT, YSDM_REG_DBG_DWORD_ENABLE, 1046316485Sdavidcs YSDM_REG_DBG_SHIFT, YSDM_REG_DBG_FORCE_VALID, 1047316485Sdavidcs YSDM_REG_DBG_FORCE_FRAME, 1048316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 8 }; 1049316485Sdavidcs 1050316485Sdavidcsstatic struct block_defs block_psdm_defs = { 1051320162Sdavidcs "psdm", { true, true, true }, true, DBG_PSTORM_ID, 1052320162Sdavidcs { DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS }, 1053316485Sdavidcs PSDM_REG_DBG_SELECT, PSDM_REG_DBG_DWORD_ENABLE, 1054316485Sdavidcs PSDM_REG_DBG_SHIFT, PSDM_REG_DBG_FORCE_VALID, 1055316485Sdavidcs PSDM_REG_DBG_FORCE_FRAME, 1056316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 7 }; 1057316485Sdavidcs 1058316485Sdavidcsstatic struct block_defs block_tsem_defs = { 1059320162Sdavidcs "tsem", { true, true, true }, true, DBG_TSTORM_ID, 1060320162Sdavidcs { DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT }, 1061316485Sdavidcs TSEM_REG_DBG_SELECT, TSEM_REG_DBG_DWORD_ENABLE, 1062316485Sdavidcs TSEM_REG_DBG_SHIFT, TSEM_REG_DBG_FORCE_VALID, 1063316485Sdavidcs TSEM_REG_DBG_FORCE_FRAME, 1064316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 4 }; 1065316485Sdavidcs 1066316485Sdavidcsstatic struct block_defs block_msem_defs = { 1067320162Sdavidcs "msem", { true, true, true }, true, DBG_MSTORM_ID, 1068320162Sdavidcs { DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM }, 1069316485Sdavidcs MSEM_REG_DBG_SELECT, MSEM_REG_DBG_DWORD_ENABLE, 1070316485Sdavidcs MSEM_REG_DBG_SHIFT, MSEM_REG_DBG_FORCE_VALID, 1071316485Sdavidcs MSEM_REG_DBG_FORCE_FRAME, 1072316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 9 }; 1073316485Sdavidcs 1074316485Sdavidcsstatic struct block_defs block_usem_defs = { 1075320162Sdavidcs "usem", { true, true, true }, true, DBG_USTORM_ID, 1076320162Sdavidcs { DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU }, 1077316485Sdavidcs USEM_REG_DBG_SELECT, USEM_REG_DBG_DWORD_ENABLE, 1078316485Sdavidcs USEM_REG_DBG_SHIFT, USEM_REG_DBG_FORCE_VALID, 1079316485Sdavidcs USEM_REG_DBG_FORCE_FRAME, 1080316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 9 }; 1081316485Sdavidcs 1082316485Sdavidcsstatic struct block_defs block_xsem_defs = { 1083320162Sdavidcs "xsem", { true, true, true }, true, DBG_XSTORM_ID, 1084320162Sdavidcs { DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX }, 1085316485Sdavidcs XSEM_REG_DBG_SELECT, XSEM_REG_DBG_DWORD_ENABLE, 1086316485Sdavidcs XSEM_REG_DBG_SHIFT, XSEM_REG_DBG_FORCE_VALID, 1087316485Sdavidcs XSEM_REG_DBG_FORCE_FRAME, 1088316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 21 }; 1089316485Sdavidcs 1090316485Sdavidcsstatic struct block_defs block_ysem_defs = { 1091320162Sdavidcs "ysem", { true, true, true }, true, DBG_YSTORM_ID, 1092320162Sdavidcs { DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY }, 1093316485Sdavidcs YSEM_REG_DBG_SELECT, YSEM_REG_DBG_DWORD_ENABLE, 1094316485Sdavidcs YSEM_REG_DBG_SHIFT, YSEM_REG_DBG_FORCE_VALID, 1095316485Sdavidcs YSEM_REG_DBG_FORCE_FRAME, 1096316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 11 }; 1097316485Sdavidcs 1098316485Sdavidcsstatic struct block_defs block_psem_defs = { 1099320162Sdavidcs "psem", { true, true, true }, true, DBG_PSTORM_ID, 1100320162Sdavidcs { DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS }, 1101316485Sdavidcs PSEM_REG_DBG_SELECT, PSEM_REG_DBG_DWORD_ENABLE, 1102316485Sdavidcs PSEM_REG_DBG_SHIFT, PSEM_REG_DBG_FORCE_VALID, 1103316485Sdavidcs PSEM_REG_DBG_FORCE_FRAME, 1104316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 10 }; 1105316485Sdavidcs 1106316485Sdavidcsstatic struct block_defs block_rss_defs = { 1107320162Sdavidcs "rss", { true, true, true }, false, 0, 1108320162Sdavidcs { DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT }, 1109316485Sdavidcs RSS_REG_DBG_SELECT, RSS_REG_DBG_DWORD_ENABLE, 1110316485Sdavidcs RSS_REG_DBG_SHIFT, RSS_REG_DBG_FORCE_VALID, 1111316485Sdavidcs RSS_REG_DBG_FORCE_FRAME, 1112316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 18 }; 1113316485Sdavidcs 1114316485Sdavidcsstatic struct block_defs block_tmld_defs = { 1115320162Sdavidcs "tmld", { true, true, true }, false, 0, 1116320162Sdavidcs { DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM }, 1117316485Sdavidcs TMLD_REG_DBG_SELECT, TMLD_REG_DBG_DWORD_ENABLE, 1118316485Sdavidcs TMLD_REG_DBG_SHIFT, TMLD_REG_DBG_FORCE_VALID, 1119316485Sdavidcs TMLD_REG_DBG_FORCE_FRAME, 1120316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 13 }; 1121316485Sdavidcs 1122316485Sdavidcsstatic struct block_defs block_muld_defs = { 1123320162Sdavidcs "muld", { true, true, true }, false, 0, 1124320162Sdavidcs { DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU }, 1125316485Sdavidcs MULD_REG_DBG_SELECT, MULD_REG_DBG_DWORD_ENABLE, 1126316485Sdavidcs MULD_REG_DBG_SHIFT, MULD_REG_DBG_FORCE_VALID, 1127316485Sdavidcs MULD_REG_DBG_FORCE_FRAME, 1128316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 14 }; 1129316485Sdavidcs 1130316485Sdavidcsstatic struct block_defs block_yuld_defs = { 1131320162Sdavidcs "yuld", { true, true, false }, false, 0, 1132320162Sdavidcs { DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, MAX_DBG_BUS_CLIENTS }, 1133316485Sdavidcs YULD_REG_DBG_SELECT_BB_K2, YULD_REG_DBG_DWORD_ENABLE_BB_K2, 1134316485Sdavidcs YULD_REG_DBG_SHIFT_BB_K2, YULD_REG_DBG_FORCE_VALID_BB_K2, 1135316485Sdavidcs YULD_REG_DBG_FORCE_FRAME_BB_K2, 1136316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 15 }; 1137316485Sdavidcs 1138316485Sdavidcsstatic struct block_defs block_xyld_defs = { 1139320162Sdavidcs "xyld", { true, true, true }, false, 0, 1140320162Sdavidcs { DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX }, 1141316485Sdavidcs XYLD_REG_DBG_SELECT, XYLD_REG_DBG_DWORD_ENABLE, 1142316485Sdavidcs XYLD_REG_DBG_SHIFT, XYLD_REG_DBG_FORCE_VALID, 1143316485Sdavidcs XYLD_REG_DBG_FORCE_FRAME, 1144316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 12 }; 1145316485Sdavidcs 1146337519Sdavidcsstatic struct block_defs block_ptld_defs = { 1147337519Sdavidcs "ptld", { false, false, true }, false, 0, 1148337519Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCT }, 1149337519Sdavidcs PTLD_REG_DBG_SELECT_E5, PTLD_REG_DBG_DWORD_ENABLE_E5, 1150337519Sdavidcs PTLD_REG_DBG_SHIFT_E5, PTLD_REG_DBG_FORCE_VALID_E5, 1151337519Sdavidcs PTLD_REG_DBG_FORCE_FRAME_E5, 1152337519Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 28 }; 1153337519Sdavidcs 1154337519Sdavidcsstatic struct block_defs block_ypld_defs = { 1155337519Sdavidcs "ypld", { false, false, true }, false, 0, 1156337519Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCS }, 1157337519Sdavidcs YPLD_REG_DBG_SELECT_E5, YPLD_REG_DBG_DWORD_ENABLE_E5, 1158337519Sdavidcs YPLD_REG_DBG_SHIFT_E5, YPLD_REG_DBG_FORCE_VALID_E5, 1159337519Sdavidcs YPLD_REG_DBG_FORCE_FRAME_E5, 1160337519Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 27 }; 1161337519Sdavidcs 1162316485Sdavidcsstatic struct block_defs block_prm_defs = { 1163320162Sdavidcs "prm", { true, true, true }, false, 0, 1164320162Sdavidcs { DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM }, 1165316485Sdavidcs PRM_REG_DBG_SELECT, PRM_REG_DBG_DWORD_ENABLE, 1166316485Sdavidcs PRM_REG_DBG_SHIFT, PRM_REG_DBG_FORCE_VALID, 1167316485Sdavidcs PRM_REG_DBG_FORCE_FRAME, 1168316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 21 }; 1169316485Sdavidcs 1170316485Sdavidcsstatic struct block_defs block_pbf_pb1_defs = { 1171320162Sdavidcs "pbf_pb1", { true, true, true }, false, 0, 1172320162Sdavidcs { DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV }, 1173316485Sdavidcs PBF_PB1_REG_DBG_SELECT, PBF_PB1_REG_DBG_DWORD_ENABLE, 1174316485Sdavidcs PBF_PB1_REG_DBG_SHIFT, PBF_PB1_REG_DBG_FORCE_VALID, 1175316485Sdavidcs PBF_PB1_REG_DBG_FORCE_FRAME, 1176316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 11 }; 1177316485Sdavidcs 1178316485Sdavidcsstatic struct block_defs block_pbf_pb2_defs = { 1179320162Sdavidcs "pbf_pb2", { true, true, true }, false, 0, 1180320162Sdavidcs { DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV }, 1181316485Sdavidcs PBF_PB2_REG_DBG_SELECT, PBF_PB2_REG_DBG_DWORD_ENABLE, 1182316485Sdavidcs PBF_PB2_REG_DBG_SHIFT, PBF_PB2_REG_DBG_FORCE_VALID, 1183316485Sdavidcs PBF_PB2_REG_DBG_FORCE_FRAME, 1184316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 12 }; 1185316485Sdavidcs 1186316485Sdavidcsstatic struct block_defs block_rpb_defs = { 1187320162Sdavidcs "rpb", { true, true, true }, false, 0, 1188320162Sdavidcs { DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM }, 1189316485Sdavidcs RPB_REG_DBG_SELECT, RPB_REG_DBG_DWORD_ENABLE, 1190316485Sdavidcs RPB_REG_DBG_SHIFT, RPB_REG_DBG_FORCE_VALID, 1191316485Sdavidcs RPB_REG_DBG_FORCE_FRAME, 1192316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 13 }; 1193316485Sdavidcs 1194316485Sdavidcsstatic struct block_defs block_btb_defs = { 1195320162Sdavidcs "btb", { true, true, true }, false, 0, 1196320162Sdavidcs { DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV }, 1197316485Sdavidcs BTB_REG_DBG_SELECT, BTB_REG_DBG_DWORD_ENABLE, 1198316485Sdavidcs BTB_REG_DBG_SHIFT, BTB_REG_DBG_FORCE_VALID, 1199316485Sdavidcs BTB_REG_DBG_FORCE_FRAME, 1200316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 10 }; 1201316485Sdavidcs 1202316485Sdavidcsstatic struct block_defs block_pbf_defs = { 1203320162Sdavidcs "pbf", { true, true, true }, false, 0, 1204320162Sdavidcs { DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV }, 1205316485Sdavidcs PBF_REG_DBG_SELECT, PBF_REG_DBG_DWORD_ENABLE, 1206316485Sdavidcs PBF_REG_DBG_SHIFT, PBF_REG_DBG_FORCE_VALID, 1207316485Sdavidcs PBF_REG_DBG_FORCE_FRAME, 1208316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 15 }; 1209316485Sdavidcs 1210316485Sdavidcsstatic struct block_defs block_rdif_defs = { 1211320162Sdavidcs "rdif", { true, true, true }, false, 0, 1212320162Sdavidcs { DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM }, 1213316485Sdavidcs RDIF_REG_DBG_SELECT, RDIF_REG_DBG_DWORD_ENABLE, 1214316485Sdavidcs RDIF_REG_DBG_SHIFT, RDIF_REG_DBG_FORCE_VALID, 1215316485Sdavidcs RDIF_REG_DBG_FORCE_FRAME, 1216316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 16 }; 1217316485Sdavidcs 1218316485Sdavidcsstatic struct block_defs block_tdif_defs = { 1219320162Sdavidcs "tdif", { true, true, true }, false, 0, 1220320162Sdavidcs { DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS }, 1221316485Sdavidcs TDIF_REG_DBG_SELECT, TDIF_REG_DBG_DWORD_ENABLE, 1222316485Sdavidcs TDIF_REG_DBG_SHIFT, TDIF_REG_DBG_FORCE_VALID, 1223316485Sdavidcs TDIF_REG_DBG_FORCE_FRAME, 1224316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 17 }; 1225316485Sdavidcs 1226316485Sdavidcsstatic struct block_defs block_cdu_defs = { 1227320162Sdavidcs "cdu", { true, true, true }, false, 0, 1228320162Sdavidcs { DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF }, 1229316485Sdavidcs CDU_REG_DBG_SELECT, CDU_REG_DBG_DWORD_ENABLE, 1230316485Sdavidcs CDU_REG_DBG_SHIFT, CDU_REG_DBG_FORCE_VALID, 1231316485Sdavidcs CDU_REG_DBG_FORCE_FRAME, 1232316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 23 }; 1233316485Sdavidcs 1234316485Sdavidcsstatic struct block_defs block_ccfc_defs = { 1235320162Sdavidcs "ccfc", { true, true, true }, false, 0, 1236320162Sdavidcs { DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF }, 1237316485Sdavidcs CCFC_REG_DBG_SELECT, CCFC_REG_DBG_DWORD_ENABLE, 1238316485Sdavidcs CCFC_REG_DBG_SHIFT, CCFC_REG_DBG_FORCE_VALID, 1239316485Sdavidcs CCFC_REG_DBG_FORCE_FRAME, 1240316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 24 }; 1241316485Sdavidcs 1242316485Sdavidcsstatic struct block_defs block_tcfc_defs = { 1243320162Sdavidcs "tcfc", { true, true, true }, false, 0, 1244320162Sdavidcs { DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF }, 1245316485Sdavidcs TCFC_REG_DBG_SELECT, TCFC_REG_DBG_DWORD_ENABLE, 1246316485Sdavidcs TCFC_REG_DBG_SHIFT, TCFC_REG_DBG_FORCE_VALID, 1247316485Sdavidcs TCFC_REG_DBG_FORCE_FRAME, 1248316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 25 }; 1249316485Sdavidcs 1250316485Sdavidcsstatic struct block_defs block_igu_defs = { 1251320162Sdavidcs "igu", { true, true, true }, false, 0, 1252320162Sdavidcs { DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP }, 1253316485Sdavidcs IGU_REG_DBG_SELECT, IGU_REG_DBG_DWORD_ENABLE, 1254316485Sdavidcs IGU_REG_DBG_SHIFT, IGU_REG_DBG_FORCE_VALID, 1255316485Sdavidcs IGU_REG_DBG_FORCE_FRAME, 1256316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 27 }; 1257316485Sdavidcs 1258316485Sdavidcsstatic struct block_defs block_cau_defs = { 1259320162Sdavidcs "cau", { true, true, true }, false, 0, 1260320162Sdavidcs { DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP }, 1261316485Sdavidcs CAU_REG_DBG_SELECT, CAU_REG_DBG_DWORD_ENABLE, 1262316485Sdavidcs CAU_REG_DBG_SHIFT, CAU_REG_DBG_FORCE_VALID, 1263316485Sdavidcs CAU_REG_DBG_FORCE_FRAME, 1264316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 19 }; 1265316485Sdavidcs 1266337519Sdavidcs/* TODO: add debug bus parameters when E5 RGFS RF is added */ 1267337519Sdavidcsstatic struct block_defs block_rgfs_defs = { 1268337519Sdavidcs "rgfs", { false, false, true }, false, 0, 1269337519Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 1270337519Sdavidcs 0, 0, 0, 0, 0, 1271337519Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 29 }; 1272337519Sdavidcs 1273337519Sdavidcsstatic struct block_defs block_rgsrc_defs = { 1274337519Sdavidcs "rgsrc", { false, false, true }, false, 0, 1275337519Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH }, 1276337519Sdavidcs RGSRC_REG_DBG_SELECT_E5, RGSRC_REG_DBG_DWORD_ENABLE_E5, 1277337519Sdavidcs RGSRC_REG_DBG_SHIFT_E5, RGSRC_REG_DBG_FORCE_VALID_E5, 1278337519Sdavidcs RGSRC_REG_DBG_FORCE_FRAME_E5, 1279337519Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 30 }; 1280337519Sdavidcs 1281337519Sdavidcs/* TODO: add debug bus parameters when E5 TGFS RF is added */ 1282337519Sdavidcsstatic struct block_defs block_tgfs_defs = { 1283337519Sdavidcs "tgfs", { false, false, true }, false, 0, 1284337519Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 1285337519Sdavidcs 0, 0, 0, 0, 0, 1286337519Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 30 }; 1287337519Sdavidcs 1288337519Sdavidcsstatic struct block_defs block_tgsrc_defs = { 1289337519Sdavidcs "tgsrc", { false, false, true }, false, 0, 1290337519Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCV }, 1291337519Sdavidcs TGSRC_REG_DBG_SELECT_E5, TGSRC_REG_DBG_DWORD_ENABLE_E5, 1292337519Sdavidcs TGSRC_REG_DBG_SHIFT_E5, TGSRC_REG_DBG_FORCE_VALID_E5, 1293337519Sdavidcs TGSRC_REG_DBG_FORCE_FRAME_E5, 1294337519Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 31 }; 1295337519Sdavidcs 1296316485Sdavidcsstatic struct block_defs block_umac_defs = { 1297320162Sdavidcs "umac", { true, true, true }, false, 0, 1298320162Sdavidcs { MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ }, 1299316485Sdavidcs UMAC_REG_DBG_SELECT_K2_E5, UMAC_REG_DBG_DWORD_ENABLE_K2_E5, 1300316485Sdavidcs UMAC_REG_DBG_SHIFT_K2_E5, UMAC_REG_DBG_FORCE_VALID_K2_E5, 1301316485Sdavidcs UMAC_REG_DBG_FORCE_FRAME_K2_E5, 1302316485Sdavidcs true, false, DBG_RESET_REG_MISCS_PL_HV, 6 }; 1303316485Sdavidcs 1304316485Sdavidcsstatic struct block_defs block_xmac_defs = { 1305320162Sdavidcs "xmac", { true, false, false }, false, 0, 1306320162Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 1307316485Sdavidcs 0, 0, 0, 0, 0, 1308316485Sdavidcs false, false, MAX_DBG_RESET_REGS, 0 }; 1309316485Sdavidcs 1310316485Sdavidcsstatic struct block_defs block_dbg_defs = { 1311320162Sdavidcs "dbg", { true, true, true }, false, 0, 1312320162Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 1313316485Sdavidcs 0, 0, 0, 0, 0, 1314316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 3 }; 1315316485Sdavidcs 1316316485Sdavidcsstatic struct block_defs block_nig_defs = { 1317320162Sdavidcs "nig", { true, true, true }, false, 0, 1318320162Sdavidcs { DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN }, 1319316485Sdavidcs NIG_REG_DBG_SELECT, NIG_REG_DBG_DWORD_ENABLE, 1320316485Sdavidcs NIG_REG_DBG_SHIFT, NIG_REG_DBG_FORCE_VALID, 1321316485Sdavidcs NIG_REG_DBG_FORCE_FRAME, 1322316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 0 }; 1323316485Sdavidcs 1324316485Sdavidcsstatic struct block_defs block_wol_defs = { 1325320162Sdavidcs "wol", { false, true, true }, false, 0, 1326320162Sdavidcs { MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ }, 1327316485Sdavidcs WOL_REG_DBG_SELECT_K2_E5, WOL_REG_DBG_DWORD_ENABLE_K2_E5, 1328316485Sdavidcs WOL_REG_DBG_SHIFT_K2_E5, WOL_REG_DBG_FORCE_VALID_K2_E5, 1329316485Sdavidcs WOL_REG_DBG_FORCE_FRAME_K2_E5, 1330316485Sdavidcs true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 7 }; 1331316485Sdavidcs 1332316485Sdavidcsstatic struct block_defs block_bmbn_defs = { 1333320162Sdavidcs "bmbn", { false, true, true }, false, 0, 1334320162Sdavidcs { MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCB, DBG_BUS_CLIENT_RBCB }, 1335316485Sdavidcs BMBN_REG_DBG_SELECT_K2_E5, BMBN_REG_DBG_DWORD_ENABLE_K2_E5, 1336316485Sdavidcs BMBN_REG_DBG_SHIFT_K2_E5, BMBN_REG_DBG_FORCE_VALID_K2_E5, 1337316485Sdavidcs BMBN_REG_DBG_FORCE_FRAME_K2_E5, 1338316485Sdavidcs false, false, MAX_DBG_RESET_REGS, 0 }; 1339316485Sdavidcs 1340316485Sdavidcsstatic struct block_defs block_ipc_defs = { 1341320162Sdavidcs "ipc", { true, true, true }, false, 0, 1342320162Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 1343316485Sdavidcs 0, 0, 0, 0, 0, 1344316485Sdavidcs true, false, DBG_RESET_REG_MISCS_PL_UA, 8 }; 1345316485Sdavidcs 1346316485Sdavidcsstatic struct block_defs block_nwm_defs = { 1347320162Sdavidcs "nwm", { false, true, true }, false, 0, 1348320162Sdavidcs { MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW }, 1349316485Sdavidcs NWM_REG_DBG_SELECT_K2_E5, NWM_REG_DBG_DWORD_ENABLE_K2_E5, 1350316485Sdavidcs NWM_REG_DBG_SHIFT_K2_E5, NWM_REG_DBG_FORCE_VALID_K2_E5, 1351316485Sdavidcs NWM_REG_DBG_FORCE_FRAME_K2_E5, 1352316485Sdavidcs true, false, DBG_RESET_REG_MISCS_PL_HV_2, 0 }; 1353316485Sdavidcs 1354316485Sdavidcsstatic struct block_defs block_nws_defs = { 1355320162Sdavidcs "nws", { false, true, true }, false, 0, 1356320162Sdavidcs { MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW }, 1357316485Sdavidcs NWS_REG_DBG_SELECT_K2_E5, NWS_REG_DBG_DWORD_ENABLE_K2_E5, 1358316485Sdavidcs NWS_REG_DBG_SHIFT_K2_E5, NWS_REG_DBG_FORCE_VALID_K2_E5, 1359316485Sdavidcs NWS_REG_DBG_FORCE_FRAME_K2_E5, 1360316485Sdavidcs true, false, DBG_RESET_REG_MISCS_PL_HV, 12 }; 1361316485Sdavidcs 1362316485Sdavidcsstatic struct block_defs block_ms_defs = { 1363320162Sdavidcs "ms", { false, true, true }, false, 0, 1364320162Sdavidcs { MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ }, 1365316485Sdavidcs MS_REG_DBG_SELECT_K2_E5, MS_REG_DBG_DWORD_ENABLE_K2_E5, 1366316485Sdavidcs MS_REG_DBG_SHIFT_K2_E5, MS_REG_DBG_FORCE_VALID_K2_E5, 1367316485Sdavidcs MS_REG_DBG_FORCE_FRAME_K2_E5, 1368316485Sdavidcs true, false, DBG_RESET_REG_MISCS_PL_HV, 13 }; 1369316485Sdavidcs 1370316485Sdavidcsstatic struct block_defs block_phy_pcie_defs = { 1371320162Sdavidcs "phy_pcie", { false, true, true }, false, 0, 1372320162Sdavidcs { MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH }, 1373316485Sdavidcs PCIE_REG_DBG_COMMON_SELECT_K2_E5, PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5, 1374316485Sdavidcs PCIE_REG_DBG_COMMON_SHIFT_K2_E5, PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5, 1375316485Sdavidcs PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5, 1376316485Sdavidcs false, false, MAX_DBG_RESET_REGS, 0 }; 1377316485Sdavidcs 1378316485Sdavidcsstatic struct block_defs block_led_defs = { 1379320162Sdavidcs "led", { false, true, true }, false, 0, 1380320162Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 1381316485Sdavidcs 0, 0, 0, 0, 0, 1382316485Sdavidcs true, false, DBG_RESET_REG_MISCS_PL_HV, 14 }; 1383316485Sdavidcs 1384316485Sdavidcsstatic struct block_defs block_avs_wrap_defs = { 1385320162Sdavidcs "avs_wrap", { false, true, false }, false, 0, 1386320162Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 1387316485Sdavidcs 0, 0, 0, 0, 0, 1388316485Sdavidcs true, false, DBG_RESET_REG_MISCS_PL_UA, 11 }; 1389316485Sdavidcs 1390337519Sdavidcsstatic struct block_defs block_pxpreqbus_defs = { 1391337519Sdavidcs "pxpreqbus", { false, false, false }, false, 0, 1392320162Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 1393316485Sdavidcs 0, 0, 0, 0, 0, 1394337519Sdavidcs false, false, MAX_DBG_RESET_REGS, 0 }; 1395316485Sdavidcs 1396316485Sdavidcsstatic struct block_defs block_misc_aeu_defs = { 1397320162Sdavidcs "misc_aeu", { true, true, true }, false, 0, 1398320162Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 1399316485Sdavidcs 0, 0, 0, 0, 0, 1400316485Sdavidcs false, false, MAX_DBG_RESET_REGS, 0 }; 1401316485Sdavidcs 1402316485Sdavidcsstatic struct block_defs block_bar0_map_defs = { 1403320162Sdavidcs "bar0_map", { true, true, true }, false, 0, 1404320162Sdavidcs { MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS }, 1405316485Sdavidcs 0, 0, 0, 0, 0, 1406316485Sdavidcs false, false, MAX_DBG_RESET_REGS, 0 }; 1407316485Sdavidcs 1408316485Sdavidcs 1409316485Sdavidcsstatic struct block_defs* s_block_defs[MAX_BLOCK_ID] = { 1410316485Sdavidcs &block_grc_defs, 1411316485Sdavidcs &block_miscs_defs, 1412316485Sdavidcs &block_misc_defs, 1413316485Sdavidcs &block_dbu_defs, 1414316485Sdavidcs &block_pglue_b_defs, 1415316485Sdavidcs &block_cnig_defs, 1416316485Sdavidcs &block_cpmu_defs, 1417316485Sdavidcs &block_ncsi_defs, 1418316485Sdavidcs &block_opte_defs, 1419316485Sdavidcs &block_bmb_defs, 1420316485Sdavidcs &block_pcie_defs, 1421316485Sdavidcs &block_mcp_defs, 1422316485Sdavidcs &block_mcp2_defs, 1423316485Sdavidcs &block_pswhst_defs, 1424316485Sdavidcs &block_pswhst2_defs, 1425316485Sdavidcs &block_pswrd_defs, 1426316485Sdavidcs &block_pswrd2_defs, 1427316485Sdavidcs &block_pswwr_defs, 1428316485Sdavidcs &block_pswwr2_defs, 1429316485Sdavidcs &block_pswrq_defs, 1430316485Sdavidcs &block_pswrq2_defs, 1431316485Sdavidcs &block_pglcs_defs, 1432316485Sdavidcs &block_dmae_defs, 1433316485Sdavidcs &block_ptu_defs, 1434316485Sdavidcs &block_tcm_defs, 1435316485Sdavidcs &block_mcm_defs, 1436316485Sdavidcs &block_ucm_defs, 1437316485Sdavidcs &block_xcm_defs, 1438316485Sdavidcs &block_ycm_defs, 1439316485Sdavidcs &block_pcm_defs, 1440316485Sdavidcs &block_qm_defs, 1441316485Sdavidcs &block_tm_defs, 1442316485Sdavidcs &block_dorq_defs, 1443316485Sdavidcs &block_brb_defs, 1444316485Sdavidcs &block_src_defs, 1445316485Sdavidcs &block_prs_defs, 1446316485Sdavidcs &block_tsdm_defs, 1447316485Sdavidcs &block_msdm_defs, 1448316485Sdavidcs &block_usdm_defs, 1449316485Sdavidcs &block_xsdm_defs, 1450316485Sdavidcs &block_ysdm_defs, 1451316485Sdavidcs &block_psdm_defs, 1452316485Sdavidcs &block_tsem_defs, 1453316485Sdavidcs &block_msem_defs, 1454316485Sdavidcs &block_usem_defs, 1455316485Sdavidcs &block_xsem_defs, 1456316485Sdavidcs &block_ysem_defs, 1457316485Sdavidcs &block_psem_defs, 1458316485Sdavidcs &block_rss_defs, 1459316485Sdavidcs &block_tmld_defs, 1460316485Sdavidcs &block_muld_defs, 1461316485Sdavidcs &block_yuld_defs, 1462316485Sdavidcs &block_xyld_defs, 1463316485Sdavidcs &block_ptld_defs, 1464316485Sdavidcs &block_ypld_defs, 1465316485Sdavidcs &block_prm_defs, 1466316485Sdavidcs &block_pbf_pb1_defs, 1467316485Sdavidcs &block_pbf_pb2_defs, 1468316485Sdavidcs &block_rpb_defs, 1469316485Sdavidcs &block_btb_defs, 1470316485Sdavidcs &block_pbf_defs, 1471316485Sdavidcs &block_rdif_defs, 1472316485Sdavidcs &block_tdif_defs, 1473316485Sdavidcs &block_cdu_defs, 1474316485Sdavidcs &block_ccfc_defs, 1475316485Sdavidcs &block_tcfc_defs, 1476316485Sdavidcs &block_igu_defs, 1477316485Sdavidcs &block_cau_defs, 1478316485Sdavidcs &block_rgfs_defs, 1479316485Sdavidcs &block_rgsrc_defs, 1480316485Sdavidcs &block_tgfs_defs, 1481316485Sdavidcs &block_tgsrc_defs, 1482316485Sdavidcs &block_umac_defs, 1483316485Sdavidcs &block_xmac_defs, 1484316485Sdavidcs &block_dbg_defs, 1485316485Sdavidcs &block_nig_defs, 1486316485Sdavidcs &block_wol_defs, 1487316485Sdavidcs &block_bmbn_defs, 1488316485Sdavidcs &block_ipc_defs, 1489316485Sdavidcs &block_nwm_defs, 1490316485Sdavidcs &block_nws_defs, 1491316485Sdavidcs &block_ms_defs, 1492316485Sdavidcs &block_phy_pcie_defs, 1493316485Sdavidcs &block_led_defs, 1494316485Sdavidcs &block_avs_wrap_defs, 1495337519Sdavidcs &block_pxpreqbus_defs, 1496316485Sdavidcs &block_misc_aeu_defs, 1497316485Sdavidcs &block_bar0_map_defs, 1498316485Sdavidcs 1499316485Sdavidcs}; 1500316485Sdavidcs 1501316485Sdavidcs 1502316485Sdavidcs/* Constraint operation types */ 1503316485Sdavidcsstatic struct dbg_bus_constraint_op_defs s_constraint_op_defs[] = { 1504316485Sdavidcs 1505316485Sdavidcs /* DBG_BUS_CONSTRAINT_OP_EQ */ 1506316485Sdavidcs { 0, false }, 1507337519Sdavidcs 1508316485Sdavidcs /* DBG_BUS_CONSTRAINT_OP_NE */ 1509316485Sdavidcs { 5, false }, 1510337519Sdavidcs 1511316485Sdavidcs /* DBG_BUS_CONSTRAINT_OP_LT */ 1512316485Sdavidcs { 1, false }, 1513337519Sdavidcs 1514316485Sdavidcs /* DBG_BUS_CONSTRAINT_OP_LTC */ 1515316485Sdavidcs { 1, true }, 1516337519Sdavidcs 1517316485Sdavidcs /* DBG_BUS_CONSTRAINT_OP_LE */ 1518316485Sdavidcs { 2, false }, 1519337519Sdavidcs 1520316485Sdavidcs /* DBG_BUS_CONSTRAINT_OP_LEC */ 1521316485Sdavidcs { 2, true }, 1522337519Sdavidcs 1523316485Sdavidcs /* DBG_BUS_CONSTRAINT_OP_GT */ 1524316485Sdavidcs { 4, false }, 1525337519Sdavidcs 1526316485Sdavidcs /* DBG_BUS_CONSTRAINT_OP_GTC */ 1527316485Sdavidcs { 4, true }, 1528337519Sdavidcs 1529316485Sdavidcs /* DBG_BUS_CONSTRAINT_OP_GE */ 1530316485Sdavidcs { 3, false }, 1531337519Sdavidcs 1532316485Sdavidcs /* DBG_BUS_CONSTRAINT_OP_GEC */ 1533316485Sdavidcs { 3, true } 1534316485Sdavidcs}; 1535316485Sdavidcs 1536316485Sdavidcsstatic const char* s_dbg_target_names[] = { 1537316485Sdavidcs 1538337519Sdavidcs /* DBG_BUS_TARGET_ID_INT_BUF */ 1539316485Sdavidcs "int-buf", 1540337519Sdavidcs 1541316485Sdavidcs /* DBG_BUS_TARGET_ID_NIG */ 1542316485Sdavidcs "nw", 1543316485Sdavidcs 1544316485Sdavidcs /* DBG_BUS_TARGET_ID_PCI */ 1545316485Sdavidcs "pci-buf" 1546316485Sdavidcs}; 1547316485Sdavidcs 1548316485Sdavidcsstatic struct storm_mode_defs s_storm_mode_defs[] = { 1549316485Sdavidcs 1550316485Sdavidcs /* DBG_BUS_STORM_MODE_PRINTF */ 1551316485Sdavidcs { "printf", true, 0 }, 1552316485Sdavidcs 1553316485Sdavidcs /* DBG_BUS_STORM_MODE_PRAM_ADDR */ 1554316485Sdavidcs { "pram_addr", true, 1 }, 1555316485Sdavidcs 1556316485Sdavidcs /* DBG_BUS_STORM_MODE_DRA_RW */ 1557316485Sdavidcs { "dra_rw", true, 2 }, 1558316485Sdavidcs 1559316485Sdavidcs /* DBG_BUS_STORM_MODE_DRA_W */ 1560316485Sdavidcs { "dra_w", true, 3 }, 1561316485Sdavidcs 1562316485Sdavidcs /* DBG_BUS_STORM_MODE_LD_ST_ADDR */ 1563316485Sdavidcs { "ld_st_addr", true, 4 }, 1564316485Sdavidcs 1565316485Sdavidcs /* DBG_BUS_STORM_MODE_DRA_FSM */ 1566316485Sdavidcs { "dra_fsm", true, 5 }, 1567316485Sdavidcs 1568316485Sdavidcs /* DBG_BUS_STORM_MODE_RH */ 1569316485Sdavidcs { "rh", true, 6 }, 1570316485Sdavidcs 1571316485Sdavidcs /* DBG_BUS_STORM_MODE_FOC */ 1572316485Sdavidcs { "foc", false, 1 }, 1573316485Sdavidcs 1574316485Sdavidcs /* DBG_BUS_STORM_MODE_EXT_STORE */ 1575316485Sdavidcs { "ext_store", false, 3 } 1576316485Sdavidcs}; 1577316485Sdavidcs 1578316485Sdavidcsstatic struct platform_defs s_platform_defs[] = { 1579316485Sdavidcs 1580316485Sdavidcs /* PLATFORM_ASIC */ 1581337519Sdavidcs { "asic", 1, 256, 32768 }, 1582316485Sdavidcs 1583316485Sdavidcs /* PLATFORM_EMUL_FULL */ 1584337519Sdavidcs { "emul_full", 2000, 8, 4096 }, 1585316485Sdavidcs 1586316485Sdavidcs /* PLATFORM_EMUL_REDUCED */ 1587337519Sdavidcs { "emul_reduced", 2000, 8, 4096 }, 1588316485Sdavidcs 1589316485Sdavidcs /* PLATFORM_FPGA */ 1590337519Sdavidcs { "fpga", 200, 32, 8192 } 1591316485Sdavidcs}; 1592316485Sdavidcs 1593316485Sdavidcsstatic struct grc_param_defs s_grc_param_defs[] = { 1594316485Sdavidcs 1595316485Sdavidcs /* DBG_GRC_PARAM_DUMP_TSTORM */ 1596320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 1, 1 }, 1597316485Sdavidcs 1598316485Sdavidcs /* DBG_GRC_PARAM_DUMP_MSTORM */ 1599320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 1, 1 }, 1600316485Sdavidcs 1601316485Sdavidcs /* DBG_GRC_PARAM_DUMP_USTORM */ 1602320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 1, 1 }, 1603316485Sdavidcs 1604316485Sdavidcs /* DBG_GRC_PARAM_DUMP_XSTORM */ 1605320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 1, 1 }, 1606316485Sdavidcs 1607316485Sdavidcs /* DBG_GRC_PARAM_DUMP_YSTORM */ 1608320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 1, 1 }, 1609316485Sdavidcs 1610316485Sdavidcs /* DBG_GRC_PARAM_DUMP_PSTORM */ 1611320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 1, 1 }, 1612316485Sdavidcs 1613316485Sdavidcs /* DBG_GRC_PARAM_DUMP_REGS */ 1614320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1615316485Sdavidcs 1616316485Sdavidcs /* DBG_GRC_PARAM_DUMP_RAM */ 1617320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1618316485Sdavidcs 1619316485Sdavidcs /* DBG_GRC_PARAM_DUMP_PBUF */ 1620320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1621316485Sdavidcs 1622316485Sdavidcs /* DBG_GRC_PARAM_DUMP_IOR */ 1623320162Sdavidcs { { 0, 0, 0 }, 0, 1, false, 0, 1 }, 1624316485Sdavidcs 1625316485Sdavidcs /* DBG_GRC_PARAM_DUMP_VFC */ 1626320162Sdavidcs { { 0, 0, 0 }, 0, 1, false, 0, 1 }, 1627316485Sdavidcs 1628316485Sdavidcs /* DBG_GRC_PARAM_DUMP_CM_CTX */ 1629320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1630316485Sdavidcs 1631316485Sdavidcs /* DBG_GRC_PARAM_DUMP_ILT */ 1632320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1633316485Sdavidcs 1634316485Sdavidcs /* DBG_GRC_PARAM_DUMP_RSS */ 1635320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1636316485Sdavidcs 1637316485Sdavidcs /* DBG_GRC_PARAM_DUMP_CAU */ 1638320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1639316485Sdavidcs 1640316485Sdavidcs /* DBG_GRC_PARAM_DUMP_QM */ 1641320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1642316485Sdavidcs 1643316485Sdavidcs /* DBG_GRC_PARAM_DUMP_MCP */ 1644320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1645316485Sdavidcs 1646316485Sdavidcs /* DBG_GRC_PARAM_RESERVED */ 1647320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1648316485Sdavidcs 1649316485Sdavidcs /* DBG_GRC_PARAM_DUMP_CFC */ 1650320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1651316485Sdavidcs 1652316485Sdavidcs /* DBG_GRC_PARAM_DUMP_IGU */ 1653320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1654316485Sdavidcs 1655316485Sdavidcs /* DBG_GRC_PARAM_DUMP_BRB */ 1656320162Sdavidcs { { 0, 0, 0 }, 0, 1, false, 0, 1 }, 1657316485Sdavidcs 1658316485Sdavidcs /* DBG_GRC_PARAM_DUMP_BTB */ 1659320162Sdavidcs { { 0, 0, 0 }, 0, 1, false, 0, 1 }, 1660316485Sdavidcs 1661316485Sdavidcs /* DBG_GRC_PARAM_DUMP_BMB */ 1662320162Sdavidcs { { 0, 0, 0 }, 0, 1, false, 0, 1 }, 1663316485Sdavidcs 1664316485Sdavidcs /* DBG_GRC_PARAM_DUMP_NIG */ 1665320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1666316485Sdavidcs 1667316485Sdavidcs /* DBG_GRC_PARAM_DUMP_MULD */ 1668320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1669316485Sdavidcs 1670316485Sdavidcs /* DBG_GRC_PARAM_DUMP_PRS */ 1671320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1672316485Sdavidcs 1673316485Sdavidcs /* DBG_GRC_PARAM_DUMP_DMAE */ 1674320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1675316485Sdavidcs 1676316485Sdavidcs /* DBG_GRC_PARAM_DUMP_TM */ 1677320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1678316485Sdavidcs 1679316485Sdavidcs /* DBG_GRC_PARAM_DUMP_SDM */ 1680320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1681316485Sdavidcs 1682316485Sdavidcs /* DBG_GRC_PARAM_DUMP_DIF */ 1683320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1684316485Sdavidcs 1685316485Sdavidcs /* DBG_GRC_PARAM_DUMP_STATIC */ 1686320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1687316485Sdavidcs 1688316485Sdavidcs /* DBG_GRC_PARAM_UNSTALL */ 1689320162Sdavidcs { { 0, 0, 0 }, 0, 1, false, 0, 0 }, 1690316485Sdavidcs 1691316485Sdavidcs /* DBG_GRC_PARAM_NUM_LCIDS */ 1692320162Sdavidcs { { MAX_LCIDS, MAX_LCIDS, MAX_LCIDS }, 1, MAX_LCIDS, false, MAX_LCIDS, MAX_LCIDS }, 1693316485Sdavidcs 1694316485Sdavidcs /* DBG_GRC_PARAM_NUM_LTIDS */ 1695320162Sdavidcs { { MAX_LTIDS, MAX_LTIDS, MAX_LTIDS }, 1, MAX_LTIDS, false, MAX_LTIDS, MAX_LTIDS }, 1696316485Sdavidcs 1697316485Sdavidcs /* DBG_GRC_PARAM_EXCLUDE_ALL */ 1698320162Sdavidcs { { 0, 0, 0 }, 0, 1, true, 0, 0 }, 1699316485Sdavidcs 1700316485Sdavidcs /* DBG_GRC_PARAM_CRASH */ 1701320162Sdavidcs { { 0, 0, 0 }, 0, 1, true, 0, 0 }, 1702316485Sdavidcs 1703316485Sdavidcs /* DBG_GRC_PARAM_PARITY_SAFE */ 1704320162Sdavidcs { { 0, 0, 0 }, 0, 1, false, 1, 0 }, 1705316485Sdavidcs 1706316485Sdavidcs /* DBG_GRC_PARAM_DUMP_CM */ 1707320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1708316485Sdavidcs 1709316485Sdavidcs /* DBG_GRC_PARAM_DUMP_PHY */ 1710320162Sdavidcs { { 1, 1, 1 }, 0, 1, false, 0, 1 }, 1711316485Sdavidcs 1712316485Sdavidcs /* DBG_GRC_PARAM_NO_MCP */ 1713320162Sdavidcs { { 0, 0, 0 }, 0, 1, false, 0, 0 }, 1714316485Sdavidcs 1715316485Sdavidcs /* DBG_GRC_PARAM_NO_FW_VER */ 1716320162Sdavidcs { { 0, 0, 0 }, 0, 1, false, 0, 0 } 1717316485Sdavidcs}; 1718316485Sdavidcs 1719316485Sdavidcsstatic struct rss_mem_defs s_rss_mem_defs[] = { 1720320162Sdavidcs { "rss_mem_cid", "rss_cid", 0, 32, 1721320162Sdavidcs { 256, 320, 512 } }, 1722316485Sdavidcs 1723320162Sdavidcs { "rss_mem_key_msb", "rss_key", 1024, 256, 1724320162Sdavidcs { 128, 208, 257 } }, 1725316485Sdavidcs 1726320162Sdavidcs { "rss_mem_key_lsb", "rss_key", 2048, 64, 1727320162Sdavidcs { 128, 208, 257 } }, 1728316485Sdavidcs 1729320162Sdavidcs { "rss_mem_info", "rss_info", 3072, 16, 1730320162Sdavidcs { 128, 208, 256 } }, 1731316485Sdavidcs 1732320162Sdavidcs { "rss_mem_ind", "rss_ind", 4096, 16, 1733320162Sdavidcs { 16384, 26624, 32768 } } 1734316485Sdavidcs}; 1735316485Sdavidcs 1736316485Sdavidcsstatic struct vfc_ram_defs s_vfc_ram_defs[] = { 1737316485Sdavidcs { "vfc_ram_tt1", "vfc_ram", 0, 512 }, 1738316485Sdavidcs { "vfc_ram_mtt2", "vfc_ram", 512, 128 }, 1739316485Sdavidcs { "vfc_ram_stt2", "vfc_ram", 640, 32 }, 1740316485Sdavidcs { "vfc_ram_ro_vect", "vfc_ram", 672, 32 } 1741316485Sdavidcs}; 1742316485Sdavidcs 1743316485Sdavidcsstatic struct big_ram_defs s_big_ram_defs[] = { 1744337519Sdavidcs { "BRB", MEM_GROUP_BRB_MEM, MEM_GROUP_BRB_RAM, DBG_GRC_PARAM_DUMP_BRB, 1745337519Sdavidcs BRB_REG_BIG_RAM_ADDRESS, BRB_REG_BIG_RAM_DATA, MISC_REG_BLOCK_256B_EN, { 0, 0, 0 }, 1746337519Sdavidcs { 153600, 180224, 282624 } }, 1747316485Sdavidcs 1748337519Sdavidcs { "BTB", MEM_GROUP_BTB_MEM, MEM_GROUP_BTB_RAM, DBG_GRC_PARAM_DUMP_BTB, 1749337519Sdavidcs BTB_REG_BIG_RAM_ADDRESS, BTB_REG_BIG_RAM_DATA, MISC_REG_BLOCK_256B_EN, { 0, 1, 1 }, 1750337519Sdavidcs { 92160, 117760, 168960 } }, 1751316485Sdavidcs 1752337519Sdavidcs { "BMB", MEM_GROUP_BMB_MEM, MEM_GROUP_BMB_RAM, DBG_GRC_PARAM_DUMP_BMB, 1753337519Sdavidcs BMB_REG_BIG_RAM_ADDRESS, BMB_REG_BIG_RAM_DATA, MISCS_REG_BLOCK_256B_EN, { 0, 0, 0 }, 1754337519Sdavidcs { 36864, 36864, 36864 } } 1755316485Sdavidcs}; 1756316485Sdavidcs 1757316485Sdavidcsstatic struct reset_reg_defs s_reset_regs_defs[] = { 1758316485Sdavidcs 1759316485Sdavidcs /* DBG_RESET_REG_MISCS_PL_UA */ 1760320162Sdavidcs { MISCS_REG_RESET_PL_UA, { true, true, true }, { 0x0, 0x0, 0x0 } }, 1761316485Sdavidcs 1762316485Sdavidcs /* DBG_RESET_REG_MISCS_PL_HV */ 1763320162Sdavidcs { MISCS_REG_RESET_PL_HV, { true, true, true }, { 0x0, 0x400, 0x600 } }, 1764316485Sdavidcs 1765316485Sdavidcs /* DBG_RESET_REG_MISCS_PL_HV_2 */ 1766320162Sdavidcs { MISCS_REG_RESET_PL_HV_2_K2_E5, { false, true, true }, { 0x0, 0x0, 0x0 } }, 1767316485Sdavidcs 1768316485Sdavidcs /* DBG_RESET_REG_MISC_PL_UA */ 1769320162Sdavidcs { MISC_REG_RESET_PL_UA, { true, true, true }, { 0x0, 0x0, 0x0 } }, 1770316485Sdavidcs 1771316485Sdavidcs /* DBG_RESET_REG_MISC_PL_HV */ 1772320162Sdavidcs { MISC_REG_RESET_PL_HV, { true, true, true }, { 0x0, 0x0, 0x0 } }, 1773316485Sdavidcs 1774316485Sdavidcs /* DBG_RESET_REG_MISC_PL_PDA_VMAIN_1 */ 1775320162Sdavidcs { MISC_REG_RESET_PL_PDA_VMAIN_1, { true, true, true }, { 0x4404040, 0x4404040, 0x404040 } }, 1776316485Sdavidcs 1777316485Sdavidcs /* DBG_RESET_REG_MISC_PL_PDA_VMAIN_2 */ 1778320162Sdavidcs { MISC_REG_RESET_PL_PDA_VMAIN_2, { true, true, true }, { 0x7, 0x7c00007, 0x5c08007 } }, 1779316485Sdavidcs 1780316485Sdavidcs /* DBG_RESET_REG_MISC_PL_PDA_VAUX */ 1781320162Sdavidcs { MISC_REG_RESET_PL_PDA_VAUX, { true, true, true }, { 0x2, 0x2, 0x2 } }, 1782316485Sdavidcs}; 1783316485Sdavidcs 1784316485Sdavidcsstatic struct phy_defs s_phy_defs[] = { 1785337519Sdavidcs { "nw_phy", NWS_REG_NWS_CMU_K2, PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5, PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5, PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5, PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5 }, 1786316485Sdavidcs { "sgmii_phy", MS_REG_MS_CMU_K2_E5, PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 }, 1787316485Sdavidcs { "pcie_phy0", PHY_PCIE_REG_PHY0_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 }, 1788316485Sdavidcs { "pcie_phy1", PHY_PCIE_REG_PHY1_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 }, 1789316485Sdavidcs}; 1790316485Sdavidcs 1791316485Sdavidcs/* The order of indexes that should be applied to a PCI buffer line */ 1792316485Sdavidcsstatic const u8 s_pci_buf_line_ind[PCI_BUF_LINE_SIZE_IN_DWORDS] = { 1, 0, 3, 2, 5, 4, 7, 6 }; 1793316485Sdavidcs 1794316485Sdavidcs/******************************** Variables **********************************/ 1795316485Sdavidcs 1796316485Sdavidcs/* The version of the calling app */ 1797316485Sdavidcsstatic u32 s_app_ver; 1798316485Sdavidcs 1799316485Sdavidcs/**************************** Private Functions ******************************/ 1800316485Sdavidcs 1801316485Sdavidcsstatic void ecore_static_asserts(void) 1802316485Sdavidcs{ 1803316485Sdavidcs CHECK_ARR_SIZE(s_dbg_arrays, MAX_BIN_DBG_BUFFER_TYPE); 1804316485Sdavidcs CHECK_ARR_SIZE(s_big_ram_defs, NUM_BIG_RAM_TYPES); 1805316485Sdavidcs CHECK_ARR_SIZE(s_vfc_ram_defs, NUM_VFC_RAM_TYPES); 1806316485Sdavidcs CHECK_ARR_SIZE(s_rss_mem_defs, NUM_RSS_MEM_TYPES); 1807316485Sdavidcs CHECK_ARR_SIZE(s_chip_defs, MAX_CHIP_IDS); 1808316485Sdavidcs CHECK_ARR_SIZE(s_platform_defs, MAX_PLATFORM_IDS); 1809316485Sdavidcs CHECK_ARR_SIZE(s_storm_defs, MAX_DBG_STORMS); 1810316485Sdavidcs CHECK_ARR_SIZE(s_constraint_op_defs, MAX_DBG_BUS_CONSTRAINT_OPS); 1811316485Sdavidcs CHECK_ARR_SIZE(s_dbg_target_names, MAX_DBG_BUS_TARGETS); 1812316485Sdavidcs CHECK_ARR_SIZE(s_storm_mode_defs, MAX_DBG_BUS_STORM_MODES); 1813316485Sdavidcs CHECK_ARR_SIZE(s_grc_param_defs, MAX_DBG_GRC_PARAMS); 1814316485Sdavidcs CHECK_ARR_SIZE(s_reset_regs_defs, MAX_DBG_RESET_REGS); 1815316485Sdavidcs} 1816316485Sdavidcs 1817316485Sdavidcs/* Reads and returns a single dword from the specified unaligned buffer. */ 1818316485Sdavidcsstatic u32 ecore_read_unaligned_dword(u8 *buf) 1819316485Sdavidcs{ 1820316485Sdavidcs u32 dword; 1821316485Sdavidcs 1822337519Sdavidcs OSAL_MEMCPY((u8 *)&dword, buf, sizeof(dword)); 1823316485Sdavidcs return dword; 1824316485Sdavidcs} 1825316485Sdavidcs 1826316485Sdavidcs/* Returns the difference in bytes between the specified physical addresses. 1827316485Sdavidcs * Assumes that the first address is bigger then the second, and that the 1828316485Sdavidcs * difference is a 32-bit value. 1829316485Sdavidcs */ 1830316485Sdavidcsstatic u32 ecore_phys_addr_diff(struct dbg_bus_mem_addr *a, 1831316485Sdavidcs struct dbg_bus_mem_addr *b) 1832316485Sdavidcs{ 1833316485Sdavidcs return a->hi == b->hi ? a->lo - b->lo : b->lo - a->lo; 1834316485Sdavidcs} 1835316485Sdavidcs 1836316485Sdavidcs/* Sets the value of the specified GRC param */ 1837316485Sdavidcsstatic void ecore_grc_set_param(struct ecore_hwfn *p_hwfn, 1838316485Sdavidcs enum dbg_grc_params grc_param, 1839316485Sdavidcs u32 val) 1840316485Sdavidcs{ 1841316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1842316485Sdavidcs 1843316485Sdavidcs dev_data->grc.param_val[grc_param] = val; 1844316485Sdavidcs} 1845316485Sdavidcs 1846316485Sdavidcs/* Returns the value of the specified GRC param */ 1847316485Sdavidcsstatic u32 ecore_grc_get_param(struct ecore_hwfn *p_hwfn, 1848316485Sdavidcs enum dbg_grc_params grc_param) 1849316485Sdavidcs{ 1850316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1851316485Sdavidcs 1852316485Sdavidcs return dev_data->grc.param_val[grc_param]; 1853316485Sdavidcs} 1854316485Sdavidcs 1855316485Sdavidcs/* Initializes the GRC parameters */ 1856316485Sdavidcsstatic void ecore_dbg_grc_init_params(struct ecore_hwfn *p_hwfn) 1857316485Sdavidcs{ 1858316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1859316485Sdavidcs 1860316485Sdavidcs if (!dev_data->grc.params_initialized) { 1861316485Sdavidcs ecore_dbg_grc_set_params_default(p_hwfn); 1862316485Sdavidcs dev_data->grc.params_initialized = 1; 1863316485Sdavidcs } 1864316485Sdavidcs} 1865316485Sdavidcs 1866316485Sdavidcs/* Initializes debug data for the specified device */ 1867316485Sdavidcsstatic enum dbg_status ecore_dbg_dev_init(struct ecore_hwfn *p_hwfn, 1868316485Sdavidcs struct ecore_ptt *p_ptt) 1869316485Sdavidcs{ 1870316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1871316485Sdavidcs 1872316485Sdavidcs if (dev_data->initialized) 1873316485Sdavidcs return DBG_STATUS_OK; 1874316485Sdavidcs 1875316485Sdavidcs if (!s_app_ver) 1876316485Sdavidcs return DBG_STATUS_APP_VERSION_NOT_SET; 1877316485Sdavidcs 1878320162Sdavidcs if (ECORE_IS_E5(p_hwfn->p_dev)) { 1879320162Sdavidcs dev_data->chip_id = CHIP_E5; 1880320162Sdavidcs dev_data->mode_enable[MODE_E5] = 1; 1881320162Sdavidcs } 1882320162Sdavidcs else if (ECORE_IS_K2(p_hwfn->p_dev)) { 1883316485Sdavidcs dev_data->chip_id = CHIP_K2; 1884316485Sdavidcs dev_data->mode_enable[MODE_K2] = 1; 1885316485Sdavidcs } 1886316485Sdavidcs else if (ECORE_IS_BB_B0(p_hwfn->p_dev)) { 1887316485Sdavidcs dev_data->chip_id = CHIP_BB; 1888316485Sdavidcs dev_data->mode_enable[MODE_BB] = 1; 1889316485Sdavidcs } 1890316485Sdavidcs else { 1891316485Sdavidcs return DBG_STATUS_UNKNOWN_CHIP; 1892316485Sdavidcs } 1893316485Sdavidcs 1894316485Sdavidcs#ifdef ASIC_ONLY 1895316485Sdavidcs dev_data->platform_id = PLATFORM_ASIC; 1896316485Sdavidcs dev_data->mode_enable[MODE_ASIC] = 1; 1897316485Sdavidcs#else 1898316485Sdavidcs if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) { 1899316485Sdavidcs dev_data->platform_id = PLATFORM_ASIC; 1900316485Sdavidcs dev_data->mode_enable[MODE_ASIC] = 1; 1901316485Sdavidcs } 1902316485Sdavidcs else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) { 1903316485Sdavidcs if (ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED) & 0x20000000) { 1904316485Sdavidcs dev_data->platform_id = PLATFORM_EMUL_FULL; 1905316485Sdavidcs dev_data->mode_enable[MODE_EMUL_FULL] = 1; 1906316485Sdavidcs } 1907316485Sdavidcs else { 1908316485Sdavidcs dev_data->platform_id = PLATFORM_EMUL_REDUCED; 1909316485Sdavidcs dev_data->mode_enable[MODE_EMUL_REDUCED] = 1; 1910316485Sdavidcs } 1911316485Sdavidcs } 1912316485Sdavidcs else if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) { 1913316485Sdavidcs dev_data->platform_id = PLATFORM_FPGA; 1914316485Sdavidcs dev_data->mode_enable[MODE_FPGA] = 1; 1915316485Sdavidcs } 1916316485Sdavidcs else { 1917316485Sdavidcs return DBG_STATUS_UNKNOWN_CHIP; 1918316485Sdavidcs } 1919316485Sdavidcs#endif 1920316485Sdavidcs 1921316485Sdavidcs /* Initializes the GRC parameters */ 1922316485Sdavidcs ecore_dbg_grc_init_params(p_hwfn); 1923316485Sdavidcs 1924337519Sdavidcs dev_data->use_dmae = USE_DMAE; 1925337519Sdavidcs dev_data->num_regs_read = 0; 1926337519Sdavidcs dev_data->initialized = 1; 1927316485Sdavidcs 1928316485Sdavidcs return DBG_STATUS_OK; 1929316485Sdavidcs} 1930316485Sdavidcs 1931316485Sdavidcsstatic struct dbg_bus_block* get_dbg_bus_block_desc(struct ecore_hwfn *p_hwfn, 1932316485Sdavidcs enum block_id block_id) 1933316485Sdavidcs{ 1934316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1935316485Sdavidcs 1936337519Sdavidcs return (struct dbg_bus_block *)&dbg_bus_blocks[block_id * MAX_CHIP_IDS + dev_data->chip_id]; 1937316485Sdavidcs} 1938316485Sdavidcs 1939316485Sdavidcs/* Returns OSAL_NULL for signature line, latency line and non-existing lines */ 1940316485Sdavidcsstatic struct dbg_bus_line* get_dbg_bus_line_desc(struct ecore_hwfn *p_hwfn, 1941316485Sdavidcs enum block_id block_id) 1942316485Sdavidcs{ 1943316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1944316485Sdavidcs struct dbg_bus_block_data *block_bus; 1945316485Sdavidcs struct dbg_bus_block *block_desc; 1946316485Sdavidcs 1947316485Sdavidcs block_bus = &dev_data->bus.blocks[block_id]; 1948316485Sdavidcs block_desc = get_dbg_bus_block_desc(p_hwfn, block_id); 1949316485Sdavidcs 1950316485Sdavidcs if (!block_bus->line_num || 1951316485Sdavidcs (block_bus->line_num == 1 && block_desc->has_latency_events) || 1952316485Sdavidcs block_bus->line_num >= NUM_DBG_LINES(block_desc)) 1953316485Sdavidcs return OSAL_NULL; 1954316485Sdavidcs 1955337519Sdavidcs return (struct dbg_bus_line *)&dbg_bus_lines[block_desc->lines_offset + block_bus->line_num - NUM_EXTRA_DBG_LINES(block_desc)]; 1956316485Sdavidcs} 1957316485Sdavidcs 1958316485Sdavidcs/* Reads the FW info structure for the specified Storm from the chip, 1959316485Sdavidcs * and writes it to the specified fw_info pointer. 1960316485Sdavidcs */ 1961316485Sdavidcsstatic void ecore_read_fw_info(struct ecore_hwfn *p_hwfn, 1962316485Sdavidcs struct ecore_ptt *p_ptt, 1963316485Sdavidcs u8 storm_id, 1964316485Sdavidcs struct fw_info *fw_info) 1965316485Sdavidcs{ 1966316485Sdavidcs struct storm_defs *storm = &s_storm_defs[storm_id]; 1967316485Sdavidcs struct fw_info_location fw_info_location; 1968316485Sdavidcs u32 addr, i, *dest; 1969316485Sdavidcs 1970316485Sdavidcs OSAL_MEMSET(&fw_info_location, 0, sizeof(fw_info_location)); 1971316485Sdavidcs OSAL_MEMSET(fw_info, 0, sizeof(*fw_info)); 1972316485Sdavidcs 1973316485Sdavidcs /* Read first the address that points to fw_info location. 1974316485Sdavidcs * The address is located in the last line of the Storm RAM. 1975316485Sdavidcs */ 1976337519Sdavidcs addr = storm->sem_fast_mem_addr + SEM_FAST_REG_INT_RAM + 1977337519Sdavidcs (ECORE_IS_E5(p_hwfn->p_dev) ? 1978337519Sdavidcs DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE_E5) : 1979337519Sdavidcs DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE_BB_K2)) 1980337519Sdavidcs - sizeof(fw_info_location); 1981316485Sdavidcs 1982337519Sdavidcs dest = (u32 *)&fw_info_location; 1983337519Sdavidcs 1984316485Sdavidcs for (i = 0; i < BYTES_TO_DWORDS(sizeof(fw_info_location)); i++, addr += BYTES_IN_DWORD) 1985316485Sdavidcs dest[i] = ecore_rd(p_hwfn, p_ptt, addr); 1986316485Sdavidcs 1987316485Sdavidcs /* Read FW version info from Storm RAM */ 1988316485Sdavidcs if (fw_info_location.size > 0 && fw_info_location.size <= sizeof(*fw_info)) { 1989316485Sdavidcs addr = fw_info_location.grc_addr; 1990337519Sdavidcs dest = (u32 *)fw_info; 1991316485Sdavidcs for (i = 0; i < BYTES_TO_DWORDS(fw_info_location.size); i++, addr += BYTES_IN_DWORD) 1992316485Sdavidcs dest[i] = ecore_rd(p_hwfn, p_ptt, addr); 1993316485Sdavidcs } 1994316485Sdavidcs} 1995316485Sdavidcs 1996316485Sdavidcs/* Dumps the specified string to the specified buffer. 1997316485Sdavidcs * Returns the dumped size in bytes. 1998316485Sdavidcs */ 1999316485Sdavidcsstatic u32 ecore_dump_str(char *dump_buf, 2000316485Sdavidcs bool dump, 2001316485Sdavidcs const char *str) 2002316485Sdavidcs{ 2003316485Sdavidcs if (dump) 2004316485Sdavidcs OSAL_STRCPY(dump_buf, str); 2005316485Sdavidcs 2006316485Sdavidcs return (u32)OSAL_STRLEN(str) + 1; 2007316485Sdavidcs} 2008316485Sdavidcs 2009316485Sdavidcs/* Dumps zeros to align the specified buffer to dwords. 2010316485Sdavidcs * Returns the dumped size in bytes. 2011316485Sdavidcs */ 2012316485Sdavidcsstatic u32 ecore_dump_align(char *dump_buf, 2013316485Sdavidcs bool dump, 2014316485Sdavidcs u32 byte_offset) 2015316485Sdavidcs{ 2016316485Sdavidcs u8 offset_in_dword, align_size; 2017316485Sdavidcs 2018316485Sdavidcs offset_in_dword = (u8)(byte_offset & 0x3); 2019316485Sdavidcs align_size = offset_in_dword ? BYTES_IN_DWORD - offset_in_dword : 0; 2020316485Sdavidcs 2021316485Sdavidcs if (dump && align_size) 2022316485Sdavidcs OSAL_MEMSET(dump_buf, 0, align_size); 2023316485Sdavidcs 2024316485Sdavidcs return align_size; 2025316485Sdavidcs} 2026316485Sdavidcs 2027316485Sdavidcs/* Writes the specified string param to the specified buffer. 2028316485Sdavidcs * Returns the dumped size in dwords. 2029316485Sdavidcs */ 2030316485Sdavidcsstatic u32 ecore_dump_str_param(u32 *dump_buf, 2031316485Sdavidcs bool dump, 2032316485Sdavidcs const char *param_name, 2033316485Sdavidcs const char *param_val) 2034316485Sdavidcs{ 2035337519Sdavidcs char *char_buf = (char *)dump_buf; 2036316485Sdavidcs u32 offset = 0; 2037316485Sdavidcs 2038316485Sdavidcs /* Dump param name */ 2039316485Sdavidcs offset += ecore_dump_str(char_buf + offset, dump, param_name); 2040316485Sdavidcs 2041316485Sdavidcs /* Indicate a string param value */ 2042316485Sdavidcs if (dump) 2043316485Sdavidcs *(char_buf + offset) = 1; 2044316485Sdavidcs offset++; 2045316485Sdavidcs 2046316485Sdavidcs /* Dump param value */ 2047316485Sdavidcs offset += ecore_dump_str(char_buf + offset, dump, param_val); 2048316485Sdavidcs 2049316485Sdavidcs /* Align buffer to next dword */ 2050316485Sdavidcs offset += ecore_dump_align(char_buf + offset, dump, offset); 2051316485Sdavidcs 2052316485Sdavidcs return BYTES_TO_DWORDS(offset); 2053316485Sdavidcs} 2054316485Sdavidcs 2055316485Sdavidcs/* Writes the specified numeric param to the specified buffer. 2056316485Sdavidcs * Returns the dumped size in dwords. 2057316485Sdavidcs */ 2058316485Sdavidcsstatic u32 ecore_dump_num_param(u32 *dump_buf, 2059316485Sdavidcs bool dump, 2060316485Sdavidcs const char *param_name, 2061316485Sdavidcs u32 param_val) 2062316485Sdavidcs{ 2063337519Sdavidcs char *char_buf = (char *)dump_buf; 2064316485Sdavidcs u32 offset = 0; 2065316485Sdavidcs 2066316485Sdavidcs /* Dump param name */ 2067316485Sdavidcs offset += ecore_dump_str(char_buf + offset, dump, param_name); 2068316485Sdavidcs 2069316485Sdavidcs /* Indicate a numeric param value */ 2070316485Sdavidcs if (dump) 2071316485Sdavidcs *(char_buf + offset) = 0; 2072316485Sdavidcs offset++; 2073316485Sdavidcs 2074316485Sdavidcs /* Align buffer to next dword */ 2075316485Sdavidcs offset += ecore_dump_align(char_buf + offset, dump, offset); 2076316485Sdavidcs 2077316485Sdavidcs /* Dump param value (and change offset from bytes to dwords) */ 2078316485Sdavidcs offset = BYTES_TO_DWORDS(offset); 2079316485Sdavidcs if (dump) 2080316485Sdavidcs *(dump_buf + offset) = param_val; 2081316485Sdavidcs offset++; 2082316485Sdavidcs 2083316485Sdavidcs return offset; 2084316485Sdavidcs} 2085316485Sdavidcs 2086316485Sdavidcs/* Reads the FW version and writes it as a param to the specified buffer. 2087316485Sdavidcs * Returns the dumped size in dwords. 2088316485Sdavidcs */ 2089316485Sdavidcsstatic u32 ecore_dump_fw_ver_param(struct ecore_hwfn *p_hwfn, 2090316485Sdavidcs struct ecore_ptt *p_ptt, 2091316485Sdavidcs u32 *dump_buf, 2092316485Sdavidcs bool dump) 2093316485Sdavidcs{ 2094316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2095316485Sdavidcs char fw_ver_str[16] = EMPTY_FW_VERSION_STR; 2096316485Sdavidcs char fw_img_str[16] = EMPTY_FW_IMAGE_STR; 2097316485Sdavidcs struct fw_info fw_info = { { 0 }, { 0 } }; 2098316485Sdavidcs u32 offset = 0; 2099316485Sdavidcs 2100316485Sdavidcs if (dump && !ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_FW_VER)) { 2101316485Sdavidcs /* Read FW image/version from PRAM in a non-reset SEMI */ 2102316485Sdavidcs bool found = false; 2103316485Sdavidcs u8 storm_id; 2104316485Sdavidcs 2105316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS && !found; storm_id++) { 2106316485Sdavidcs struct storm_defs *storm = &s_storm_defs[storm_id]; 2107316485Sdavidcs 2108316485Sdavidcs /* Read FW version/image */ 2109316485Sdavidcs if (dev_data->block_in_reset[storm->block_id]) 2110316485Sdavidcs continue; 2111316485Sdavidcs 2112316485Sdavidcs /* Read FW info for the current Storm */ 2113316485Sdavidcs ecore_read_fw_info(p_hwfn, p_ptt, storm_id, &fw_info); 2114316485Sdavidcs 2115316485Sdavidcs /* Create FW version/image strings */ 2116316485Sdavidcs if (OSAL_SNPRINTF(fw_ver_str, sizeof(fw_ver_str), "%d_%d_%d_%d", fw_info.ver.num.major, fw_info.ver.num.minor, fw_info.ver.num.rev, fw_info.ver.num.eng) < 0) 2117316485Sdavidcs DP_NOTICE(p_hwfn, true, "Unexpected debug error: invalid FW version string\n"); 2118316485Sdavidcs switch (fw_info.ver.image_id) { 2119316485Sdavidcs case FW_IMG_KUKU: OSAL_STRCPY(fw_img_str, "kuku"); break; 2120316485Sdavidcs case FW_IMG_MAIN: OSAL_STRCPY(fw_img_str, "main"); break; 2121316485Sdavidcs case FW_IMG_L2B: OSAL_STRCPY(fw_img_str, "l2b"); break; 2122316485Sdavidcs default: OSAL_STRCPY(fw_img_str, "unknown"); break; 2123316485Sdavidcs } 2124316485Sdavidcs 2125316485Sdavidcs found = true; 2126316485Sdavidcs } 2127316485Sdavidcs } 2128316485Sdavidcs 2129316485Sdavidcs /* Dump FW version, image and timestamp */ 2130316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "fw-version", fw_ver_str); 2131316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "fw-image", fw_img_str); 2132316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "fw-timestamp", fw_info.ver.timestamp); 2133316485Sdavidcs 2134316485Sdavidcs return offset; 2135316485Sdavidcs} 2136316485Sdavidcs 2137316485Sdavidcs/* Reads the MFW version and writes it as a param to the specified buffer. 2138316485Sdavidcs * Returns the dumped size in dwords. 2139316485Sdavidcs */ 2140316485Sdavidcsstatic u32 ecore_dump_mfw_ver_param(struct ecore_hwfn *p_hwfn, 2141316485Sdavidcs struct ecore_ptt *p_ptt, 2142316485Sdavidcs u32 *dump_buf, 2143316485Sdavidcs bool dump) 2144316485Sdavidcs{ 2145316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2146316485Sdavidcs char mfw_ver_str[16] = EMPTY_FW_VERSION_STR; 2147337519Sdavidcs 2148320162Sdavidcs if (dump && dev_data->platform_id == PLATFORM_ASIC && !ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_FW_VER)) { 2149316485Sdavidcs u32 public_data_addr, global_section_offsize_addr, global_section_offsize, global_section_addr, mfw_ver; 2150316485Sdavidcs 2151316485Sdavidcs /* Find MCP public data GRC address. Needs to be ORed with 2152316485Sdavidcs * MCP_REG_SCRATCH due to a HW bug. 2153316485Sdavidcs */ 2154316485Sdavidcs public_data_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR) | MCP_REG_SCRATCH; 2155316485Sdavidcs 2156316485Sdavidcs /* Find MCP public global section offset */ 2157316485Sdavidcs global_section_offsize_addr = public_data_addr + OFFSETOF(struct mcp_public_data, sections) + sizeof(offsize_t) * PUBLIC_GLOBAL; 2158316485Sdavidcs global_section_offsize = ecore_rd(p_hwfn, p_ptt, global_section_offsize_addr); 2159316485Sdavidcs global_section_addr = MCP_REG_SCRATCH + (global_section_offsize & OFFSIZE_OFFSET_MASK) * 4; 2160316485Sdavidcs 2161316485Sdavidcs /* Read MFW version from MCP public global section */ 2162316485Sdavidcs mfw_ver = ecore_rd(p_hwfn, p_ptt, global_section_addr + OFFSETOF(struct public_global, mfw_ver)); 2163316485Sdavidcs 2164316485Sdavidcs /* Dump MFW version param */ 2165316485Sdavidcs if (OSAL_SNPRINTF(mfw_ver_str, sizeof(mfw_ver_str), "%d_%d_%d_%d", (u8)(mfw_ver >> 24), (u8)(mfw_ver >> 16), (u8)(mfw_ver >> 8), (u8)mfw_ver) < 0) 2166316485Sdavidcs DP_NOTICE(p_hwfn, true, "Unexpected debug error: invalid MFW version string\n"); 2167316485Sdavidcs } 2168316485Sdavidcs 2169316485Sdavidcs return ecore_dump_str_param(dump_buf, dump, "mfw-version", mfw_ver_str); 2170316485Sdavidcs} 2171316485Sdavidcs 2172316485Sdavidcs/* Writes a section header to the specified buffer. 2173316485Sdavidcs * Returns the dumped size in dwords. 2174316485Sdavidcs */ 2175316485Sdavidcsstatic u32 ecore_dump_section_hdr(u32 *dump_buf, 2176316485Sdavidcs bool dump, 2177316485Sdavidcs const char *name, 2178316485Sdavidcs u32 num_params) 2179316485Sdavidcs{ 2180316485Sdavidcs return ecore_dump_num_param(dump_buf, dump, name, num_params); 2181316485Sdavidcs} 2182316485Sdavidcs 2183316485Sdavidcs/* Writes the common global params to the specified buffer. 2184316485Sdavidcs * Returns the dumped size in dwords. 2185316485Sdavidcs */ 2186316485Sdavidcsstatic u32 ecore_dump_common_global_params(struct ecore_hwfn *p_hwfn, 2187316485Sdavidcs struct ecore_ptt *p_ptt, 2188316485Sdavidcs u32 *dump_buf, 2189316485Sdavidcs bool dump, 2190316485Sdavidcs u8 num_specific_global_params) 2191316485Sdavidcs{ 2192316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2193316485Sdavidcs u32 offset = 0; 2194316485Sdavidcs u8 num_params; 2195316485Sdavidcs 2196316485Sdavidcs /* Dump global params section header */ 2197316485Sdavidcs num_params = NUM_COMMON_GLOBAL_PARAMS + num_specific_global_params; 2198316485Sdavidcs offset += ecore_dump_section_hdr(dump_buf + offset, dump, "global_params", num_params); 2199316485Sdavidcs 2200316485Sdavidcs /* Store params */ 2201316485Sdavidcs offset += ecore_dump_fw_ver_param(p_hwfn, p_ptt, dump_buf + offset, dump); 2202316485Sdavidcs offset += ecore_dump_mfw_ver_param(p_hwfn, p_ptt, dump_buf + offset, dump); 2203316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "tools-version", TOOLS_VERSION); 2204316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "chip", s_chip_defs[dev_data->chip_id].name); 2205316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "platform", s_platform_defs[dev_data->platform_id].name); 2206316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "pci-func", p_hwfn->abs_pf_id); 2207316485Sdavidcs 2208316485Sdavidcs return offset; 2209316485Sdavidcs} 2210316485Sdavidcs 2211316485Sdavidcs/* Writes the "last" section (including CRC) to the specified buffer at the 2212316485Sdavidcs * given offset. Returns the dumped size in dwords. 2213316485Sdavidcs */ 2214337519Sdavidcsstatic u32 ecore_dump_last_section(u32 *dump_buf, 2215337519Sdavidcs u32 offset, 2216337519Sdavidcs bool dump) 2217316485Sdavidcs{ 2218316485Sdavidcs u32 start_offset = offset; 2219316485Sdavidcs 2220316485Sdavidcs /* Dump CRC section header */ 2221316485Sdavidcs offset += ecore_dump_section_hdr(dump_buf + offset, dump, "last", 0); 2222316485Sdavidcs 2223316485Sdavidcs /* Calculate CRC32 and add it to the dword after the "last" section */ 2224316485Sdavidcs if (dump) 2225337519Sdavidcs *(dump_buf + offset) = ~OSAL_CRC32(0xffffffff, (u8 *)dump_buf, DWORDS_TO_BYTES(offset)); 2226316485Sdavidcs 2227316485Sdavidcs offset++; 2228316485Sdavidcs 2229316485Sdavidcs return offset - start_offset; 2230316485Sdavidcs} 2231316485Sdavidcs 2232316485Sdavidcs/* Update blocks reset state */ 2233316485Sdavidcsstatic void ecore_update_blocks_reset_state(struct ecore_hwfn *p_hwfn, 2234316485Sdavidcs struct ecore_ptt *p_ptt) 2235316485Sdavidcs{ 2236316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2237316485Sdavidcs u32 reg_val[MAX_DBG_RESET_REGS] = { 0 }; 2238316485Sdavidcs u32 i; 2239316485Sdavidcs 2240316485Sdavidcs /* Read reset registers */ 2241316485Sdavidcs for (i = 0; i < MAX_DBG_RESET_REGS; i++) 2242316485Sdavidcs if (s_reset_regs_defs[i].exists[dev_data->chip_id]) 2243316485Sdavidcs reg_val[i] = ecore_rd(p_hwfn, p_ptt, s_reset_regs_defs[i].addr); 2244316485Sdavidcs 2245316485Sdavidcs /* Check if blocks are in reset */ 2246316485Sdavidcs for (i = 0; i < MAX_BLOCK_ID; i++) { 2247316485Sdavidcs struct block_defs *block = s_block_defs[i]; 2248316485Sdavidcs 2249316485Sdavidcs dev_data->block_in_reset[i] = block->has_reset_bit && !(reg_val[block->reset_reg] & (1 << block->reset_bit_offset)); 2250316485Sdavidcs } 2251316485Sdavidcs} 2252316485Sdavidcs 2253316485Sdavidcs/* Enable / disable the Debug block */ 2254316485Sdavidcsstatic void ecore_bus_enable_dbg_block(struct ecore_hwfn *p_hwfn, 2255316485Sdavidcs struct ecore_ptt *p_ptt, 2256316485Sdavidcs bool enable) 2257316485Sdavidcs{ 2258316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON, enable ? 1 : 0); 2259316485Sdavidcs} 2260316485Sdavidcs 2261316485Sdavidcs/* Resets the Debug block */ 2262316485Sdavidcsstatic void ecore_bus_reset_dbg_block(struct ecore_hwfn *p_hwfn, 2263316485Sdavidcs struct ecore_ptt *p_ptt) 2264316485Sdavidcs{ 2265316485Sdavidcs u32 dbg_reset_reg_addr, old_reset_reg_val, new_reset_reg_val; 2266316485Sdavidcs struct block_defs *dbg_block = s_block_defs[BLOCK_DBG]; 2267316485Sdavidcs 2268316485Sdavidcs dbg_reset_reg_addr = s_reset_regs_defs[dbg_block->reset_reg].addr; 2269316485Sdavidcs old_reset_reg_val = ecore_rd(p_hwfn, p_ptt, dbg_reset_reg_addr); 2270316485Sdavidcs new_reset_reg_val = old_reset_reg_val & ~(1 << dbg_block->reset_bit_offset); 2271316485Sdavidcs 2272316485Sdavidcs ecore_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, new_reset_reg_val); 2273316485Sdavidcs ecore_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, old_reset_reg_val); 2274316485Sdavidcs} 2275316485Sdavidcs 2276316485Sdavidcsstatic void ecore_bus_set_framing_mode(struct ecore_hwfn *p_hwfn, 2277316485Sdavidcs struct ecore_ptt *p_ptt, 2278316485Sdavidcs enum dbg_bus_frame_modes mode) 2279316485Sdavidcs{ 2280316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_FRAMING_MODE, (u8)mode); 2281316485Sdavidcs} 2282316485Sdavidcs 2283316485Sdavidcs/* Enable / disable Debug Bus clients according to the specified mask 2284316485Sdavidcs * (1 = enable, 0 = disable). 2285316485Sdavidcs */ 2286316485Sdavidcsstatic void ecore_bus_enable_clients(struct ecore_hwfn *p_hwfn, 2287316485Sdavidcs struct ecore_ptt *p_ptt, 2288316485Sdavidcs u32 client_mask) 2289316485Sdavidcs{ 2290316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_CLIENT_ENABLE, client_mask); 2291316485Sdavidcs} 2292316485Sdavidcs 2293316485Sdavidcs/* Enables the specified Storm for Debug Bus. Assumes a valid Storm ID. */ 2294316485Sdavidcsstatic void ecore_bus_enable_storm(struct ecore_hwfn *p_hwfn, 2295316485Sdavidcs struct ecore_ptt *p_ptt, 2296337519Sdavidcs enum dbg_storms storm_id) 2297316485Sdavidcs{ 2298316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2299337519Sdavidcs u32 base_addr, sem_filter_params = 0; 2300316485Sdavidcs struct dbg_bus_storm_data *storm_bus; 2301316485Sdavidcs struct storm_mode_defs *storm_mode; 2302316485Sdavidcs struct storm_defs *storm; 2303316485Sdavidcs 2304316485Sdavidcs storm = &s_storm_defs[storm_id]; 2305316485Sdavidcs storm_bus = &dev_data->bus.storms[storm_id]; 2306316485Sdavidcs storm_mode = &s_storm_mode_defs[storm_bus->mode]; 2307316485Sdavidcs base_addr = storm->sem_fast_mem_addr; 2308316485Sdavidcs 2309316485Sdavidcs /* Config SEM */ 2310316485Sdavidcs if (storm_mode->is_fast_dbg) { 2311316485Sdavidcs 2312316485Sdavidcs /* Enable fast debug */ 2313316485Sdavidcs ecore_wr(p_hwfn, p_ptt, storm->sem_frame_mode_addr, DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST); 2314316485Sdavidcs ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_DEBUG_MODE, storm_mode->id_in_hw); 2315316485Sdavidcs ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_DEBUG_ACTIVE, 1); 2316316485Sdavidcs 2317337519Sdavidcs /* Enable messages. Must be done after enabling 2318337519Sdavidcs * SEM_FAST_REG_DEBUG_ACTIVE, otherwise messages will 2319316485Sdavidcs * be dropped after the SEMI sync fifo is filled. 2320316485Sdavidcs */ 2321337519Sdavidcs ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_DBG_MODE23_SRC_DISABLE, SEM_FAST_MODE23_SRC_ENABLE_VAL); 2322337519Sdavidcs ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_DBG_MODE4_SRC_DISABLE, SEM_FAST_MODE4_SRC_ENABLE_VAL); 2323337519Sdavidcs ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_DBG_MODE6_SRC_DISABLE, SEM_FAST_MODE6_SRC_ENABLE_VAL); 2324316485Sdavidcs } 2325316485Sdavidcs else { 2326316485Sdavidcs 2327337519Sdavidcs /* Enable slow debug */ 2328316485Sdavidcs ecore_wr(p_hwfn, p_ptt, storm->sem_frame_mode_addr, DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST); 2329316485Sdavidcs ecore_wr(p_hwfn, p_ptt, storm->sem_slow_enable_addr, 1); 2330316485Sdavidcs ecore_wr(p_hwfn, p_ptt, storm->sem_slow_mode_addr, storm_mode->id_in_hw); 2331316485Sdavidcs ecore_wr(p_hwfn, p_ptt, storm->sem_slow_mode1_conf_addr, SEM_SLOW_MODE1_DATA_ENABLE); 2332316485Sdavidcs } 2333316485Sdavidcs 2334316485Sdavidcs /* Config SEM cid filter */ 2335316485Sdavidcs if (storm_bus->cid_filter_en) { 2336316485Sdavidcs ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_FILTER_CID, storm_bus->cid); 2337316485Sdavidcs sem_filter_params |= SEM_FILTER_CID_EN_MASK; 2338316485Sdavidcs } 2339316485Sdavidcs 2340316485Sdavidcs /* Config SEM eid filter */ 2341316485Sdavidcs if (storm_bus->eid_filter_en) { 2342316485Sdavidcs const union dbg_bus_storm_eid_params *eid_filter = &storm_bus->eid_filter_params; 2343316485Sdavidcs 2344316485Sdavidcs if (storm_bus->eid_range_not_mask) { 2345316485Sdavidcs ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_EVENT_ID_RANGE_STRT, eid_filter->range.min); 2346316485Sdavidcs ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_EVENT_ID_RANGE_END, eid_filter->range.max); 2347316485Sdavidcs sem_filter_params |= SEM_FILTER_EID_RANGE_EN_MASK; 2348316485Sdavidcs } 2349316485Sdavidcs else { 2350316485Sdavidcs ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_FILTER_EVENT_ID, eid_filter->mask.val); 2351316485Sdavidcs ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_EVENT_ID_MASK, ~eid_filter->mask.mask); 2352316485Sdavidcs sem_filter_params |= SEM_FILTER_EID_MASK_EN_MASK; 2353316485Sdavidcs } 2354316485Sdavidcs } 2355316485Sdavidcs 2356316485Sdavidcs /* Config accumulaed SEM filter parameters (if any) */ 2357316485Sdavidcs if (sem_filter_params) 2358316485Sdavidcs ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_RECORD_FILTER_ENABLE, sem_filter_params); 2359316485Sdavidcs} 2360316485Sdavidcs 2361316485Sdavidcs/* Disables Debug Bus block inputs */ 2362316485Sdavidcsstatic enum dbg_status ecore_bus_disable_inputs(struct ecore_hwfn *p_hwfn, 2363316485Sdavidcs struct ecore_ptt *p_ptt, 2364316485Sdavidcs bool empty_semi_fifos) 2365316485Sdavidcs{ 2366316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2367316485Sdavidcs u8 storm_id, num_fifos_to_empty = MAX_DBG_STORMS; 2368316485Sdavidcs bool is_fifo_empty[MAX_DBG_STORMS] = { false }; 2369316485Sdavidcs u32 block_id; 2370316485Sdavidcs 2371316485Sdavidcs /* Disable messages output in all Storms */ 2372316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 2373316485Sdavidcs struct storm_defs *storm = &s_storm_defs[storm_id]; 2374316485Sdavidcs 2375337519Sdavidcs if (dev_data->block_in_reset[storm->block_id]) 2376337519Sdavidcs continue; 2377337519Sdavidcs 2378337519Sdavidcs ecore_wr(p_hwfn, p_ptt, storm->sem_fast_mem_addr + SEM_FAST_REG_DBG_MODE23_SRC_DISABLE, SEM_FAST_MODE23_SRC_DISABLE_VAL); 2379337519Sdavidcs ecore_wr(p_hwfn, p_ptt, storm->sem_fast_mem_addr + SEM_FAST_REG_DBG_MODE4_SRC_DISABLE, SEM_FAST_MODE4_SRC_DISABLE_VAL); 2380337519Sdavidcs ecore_wr(p_hwfn, p_ptt, storm->sem_fast_mem_addr + SEM_FAST_REG_DBG_MODE6_SRC_DISABLE, SEM_FAST_MODE6_SRC_DISABLE_VAL); 2381316485Sdavidcs } 2382316485Sdavidcs 2383316485Sdavidcs /* Try to empty the SEMI sync fifo. Must be done after messages output 2384337519Sdavidcs * were disabled in all Storms. 2385316485Sdavidcs */ 2386316485Sdavidcs while (num_fifos_to_empty) { 2387316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 2388316485Sdavidcs struct storm_defs *storm = &s_storm_defs[storm_id]; 2389316485Sdavidcs 2390316485Sdavidcs if (is_fifo_empty[storm_id]) 2391316485Sdavidcs continue; 2392316485Sdavidcs 2393316485Sdavidcs /* Check if sync fifo got empty */ 2394316485Sdavidcs if (dev_data->block_in_reset[storm->block_id] || ecore_rd(p_hwfn, p_ptt, storm->sem_sync_dbg_empty_addr)) { 2395316485Sdavidcs is_fifo_empty[storm_id] = true; 2396316485Sdavidcs num_fifos_to_empty--; 2397316485Sdavidcs } 2398316485Sdavidcs } 2399316485Sdavidcs 2400316485Sdavidcs /* Check if need to continue polling */ 2401316485Sdavidcs if (num_fifos_to_empty) { 2402316485Sdavidcs u32 polling_ms = SEMI_SYNC_FIFO_POLLING_DELAY_MS * s_platform_defs[dev_data->platform_id].delay_factor; 2403316485Sdavidcs u32 polling_count = 0; 2404316485Sdavidcs 2405316485Sdavidcs if (empty_semi_fifos && polling_count < SEMI_SYNC_FIFO_POLLING_COUNT) { 2406316485Sdavidcs OSAL_MSLEEP(polling_ms); 2407316485Sdavidcs polling_count++; 2408316485Sdavidcs } 2409316485Sdavidcs else { 2410316485Sdavidcs DP_NOTICE(p_hwfn, false, "Warning: failed to empty the SEMI sync FIFO. It means that the last few messages from the SEMI could not be sent to the DBG block. This can happen when the DBG block is blocked (e.g. due to a PCI problem).\n"); 2411316485Sdavidcs break; 2412316485Sdavidcs } 2413316485Sdavidcs } 2414316485Sdavidcs } 2415316485Sdavidcs 2416316485Sdavidcs /* Disable debug in all Storms */ 2417316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 2418316485Sdavidcs struct storm_defs *storm = &s_storm_defs[storm_id]; 2419316485Sdavidcs u32 base_addr = storm->sem_fast_mem_addr; 2420316485Sdavidcs 2421316485Sdavidcs if (dev_data->block_in_reset[storm->block_id]) 2422316485Sdavidcs continue; 2423316485Sdavidcs 2424316485Sdavidcs ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_DEBUG_ACTIVE, 0); 2425316485Sdavidcs ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_RECORD_FILTER_ENABLE, DBG_BUS_FILTER_TYPE_OFF); 2426316485Sdavidcs ecore_wr(p_hwfn, p_ptt, storm->sem_frame_mode_addr, DBG_BUS_FRAME_MODE_4HW_0ST); 2427316485Sdavidcs ecore_wr(p_hwfn, p_ptt, storm->sem_slow_enable_addr, 0); 2428316485Sdavidcs } 2429316485Sdavidcs 2430316485Sdavidcs /* Disable all clients */ 2431316485Sdavidcs ecore_bus_enable_clients(p_hwfn, p_ptt, 0); 2432316485Sdavidcs 2433316485Sdavidcs /* Disable all blocks */ 2434316485Sdavidcs for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 2435316485Sdavidcs struct block_defs *block = s_block_defs[block_id]; 2436316485Sdavidcs 2437320162Sdavidcs if (block->dbg_client_id[dev_data->chip_id] != MAX_DBG_BUS_CLIENTS && !dev_data->block_in_reset[block_id]) 2438316485Sdavidcs ecore_wr(p_hwfn, p_ptt, block->dbg_enable_addr, 0); 2439316485Sdavidcs } 2440316485Sdavidcs 2441316485Sdavidcs /* Disable timestamp */ 2442316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_TIMESTAMP_VALID_EN, 0); 2443316485Sdavidcs 2444316485Sdavidcs /* Disable filters and triggers */ 2445316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_FILTER_ENABLE, DBG_BUS_FILTER_TYPE_OFF); 2446316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_TRIGGER_ENABLE, 0); 2447316485Sdavidcs 2448316485Sdavidcs return DBG_STATUS_OK; 2449316485Sdavidcs} 2450316485Sdavidcs 2451316485Sdavidcs/* Sets a Debug Bus trigger/filter constraint */ 2452316485Sdavidcsstatic void ecore_bus_set_constraint(struct ecore_hwfn *p_hwfn, 2453316485Sdavidcs struct ecore_ptt *p_ptt, 2454316485Sdavidcs bool is_filter, 2455316485Sdavidcs u8 constraint_id, 2456316485Sdavidcs u8 hw_op_val, 2457316485Sdavidcs u32 data_val, 2458316485Sdavidcs u32 data_mask, 2459316485Sdavidcs u8 frame_bit, 2460316485Sdavidcs u8 frame_mask, 2461316485Sdavidcs u16 dword_offset, 2462316485Sdavidcs u16 range, 2463316485Sdavidcs u8 cyclic_bit, 2464316485Sdavidcs u8 must_bit) 2465316485Sdavidcs{ 2466316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2467316485Sdavidcs u32 reg_offset = constraint_id * BYTES_IN_DWORD; 2468316485Sdavidcs u8 curr_trigger_state; 2469316485Sdavidcs 2470316485Sdavidcs /* For trigger only - set register offset according to state */ 2471316485Sdavidcs if (!is_filter) { 2472316485Sdavidcs curr_trigger_state = dev_data->bus.next_trigger_state - 1; 2473316485Sdavidcs reg_offset += curr_trigger_state * TRIGGER_SETS_PER_STATE * MAX_CONSTRAINTS * BYTES_IN_DWORD; 2474316485Sdavidcs } 2475316485Sdavidcs 2476316485Sdavidcs ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_OPRTN_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_0) + reg_offset, hw_op_val); 2477316485Sdavidcs ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_DATA_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_0) + reg_offset, data_val); 2478316485Sdavidcs ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_DATA_MASK_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_0) + reg_offset, data_mask); 2479316485Sdavidcs ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_FRAME_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_0) + reg_offset, frame_bit); 2480316485Sdavidcs ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_FRAME_MASK_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0) + reg_offset, frame_mask); 2481316485Sdavidcs ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_OFFSET_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0) + reg_offset, dword_offset); 2482316485Sdavidcs ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_RANGE_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0) + reg_offset, range); 2483316485Sdavidcs ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_CYCLIC_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_0) + reg_offset, cyclic_bit); 2484316485Sdavidcs ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_MUST_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_0) + reg_offset, must_bit); 2485316485Sdavidcs} 2486316485Sdavidcs 2487316485Sdavidcs/* Reads the specified DBG Bus internal buffer range and copy it to the 2488316485Sdavidcs * specified buffer. Returns the dumped size in dwords. 2489316485Sdavidcs */ 2490316485Sdavidcsstatic u32 ecore_bus_dump_int_buf_range(struct ecore_hwfn *p_hwfn, 2491316485Sdavidcs struct ecore_ptt *p_ptt, 2492316485Sdavidcs u32 *dump_buf, 2493316485Sdavidcs bool dump, 2494316485Sdavidcs u32 start_line, 2495316485Sdavidcs u32 end_line) 2496316485Sdavidcs{ 2497316485Sdavidcs u32 line, reg_addr, i, offset = 0; 2498316485Sdavidcs 2499316485Sdavidcs if (!dump) 2500316485Sdavidcs return (end_line - start_line + 1) * INT_BUF_LINE_SIZE_IN_DWORDS; 2501316485Sdavidcs 2502316485Sdavidcs for (line = start_line, reg_addr = DBG_REG_INTR_BUFFER + DWORDS_TO_BYTES(start_line * INT_BUF_LINE_SIZE_IN_DWORDS); 2503316485Sdavidcs line <= end_line; 2504316485Sdavidcs line++, offset += INT_BUF_LINE_SIZE_IN_DWORDS) 2505316485Sdavidcs for (i = 0; i < INT_BUF_LINE_SIZE_IN_DWORDS; i++, reg_addr += BYTES_IN_DWORD) 2506316485Sdavidcs dump_buf[offset + INT_BUF_LINE_SIZE_IN_DWORDS - 1 - i] = ecore_rd(p_hwfn, p_ptt, reg_addr); 2507316485Sdavidcs 2508316485Sdavidcs return offset; 2509316485Sdavidcs} 2510316485Sdavidcs 2511316485Sdavidcs/* Reads the DBG Bus internal buffer and copy its contents to a buffer. 2512316485Sdavidcs * Returns the dumped size in dwords. 2513316485Sdavidcs */ 2514316485Sdavidcsstatic u32 ecore_bus_dump_int_buf(struct ecore_hwfn *p_hwfn, 2515316485Sdavidcs struct ecore_ptt *p_ptt, 2516316485Sdavidcs u32 *dump_buf, 2517316485Sdavidcs bool dump) 2518316485Sdavidcs{ 2519316485Sdavidcs u32 last_written_line, offset = 0; 2520316485Sdavidcs 2521316485Sdavidcs last_written_line = ecore_rd(p_hwfn, p_ptt, DBG_REG_INTR_BUFFER_WR_PTR); 2522316485Sdavidcs 2523316485Sdavidcs if (ecore_rd(p_hwfn, p_ptt, DBG_REG_WRAP_ON_INT_BUFFER)) { 2524316485Sdavidcs 2525316485Sdavidcs /* Internal buffer was wrapped: first dump from write pointer 2526316485Sdavidcs * to buffer end, then dump from buffer start to write pointer. 2527316485Sdavidcs */ 2528316485Sdavidcs if (last_written_line < INT_BUF_NUM_OF_LINES - 1) 2529316485Sdavidcs offset += ecore_bus_dump_int_buf_range(p_hwfn, p_ptt, dump_buf + offset, dump, last_written_line + 1, INT_BUF_NUM_OF_LINES - 1); 2530316485Sdavidcs offset += ecore_bus_dump_int_buf_range(p_hwfn, p_ptt, dump_buf + offset, dump, 0, last_written_line); 2531316485Sdavidcs } 2532316485Sdavidcs else if (last_written_line) { 2533316485Sdavidcs 2534316485Sdavidcs /* Internal buffer wasn't wrapped: dump from buffer start until 2535316485Sdavidcs * write pointer. 2536316485Sdavidcs */ 2537316485Sdavidcs if (!ecore_rd(p_hwfn, p_ptt, DBG_REG_INTR_BUFFER_RD_PTR)) 2538316485Sdavidcs offset += ecore_bus_dump_int_buf_range(p_hwfn, p_ptt, dump_buf + offset, dump, 0, last_written_line); 2539316485Sdavidcs else 2540316485Sdavidcs DP_NOTICE(p_hwfn, true, "Unexpected Debug Bus error: internal buffer read pointer is not zero\n"); 2541316485Sdavidcs } 2542316485Sdavidcs 2543316485Sdavidcs return offset; 2544316485Sdavidcs} 2545316485Sdavidcs 2546316485Sdavidcs/* Reads the specified DBG Bus PCI buffer range and copy it to the specified 2547316485Sdavidcs * buffer. Returns the dumped size in dwords. 2548316485Sdavidcs */ 2549316485Sdavidcsstatic u32 ecore_bus_dump_pci_buf_range(struct ecore_hwfn *p_hwfn, 2550316485Sdavidcs u32 *dump_buf, 2551316485Sdavidcs bool dump, 2552316485Sdavidcs u32 start_line, 2553316485Sdavidcs u32 end_line) 2554316485Sdavidcs{ 2555316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2556316485Sdavidcs u32 offset = 0; 2557316485Sdavidcs 2558316485Sdavidcs /* Extract PCI buffer pointer from virtual address */ 2559316485Sdavidcs void *virt_addr_lo = &dev_data->bus.pci_buf.virt_addr.lo; 2560337519Sdavidcs u32 *pci_buf_start = (u32 *)(osal_uintptr_t)*((u64 *)virt_addr_lo); 2561316485Sdavidcs u32 *pci_buf, line, i; 2562316485Sdavidcs 2563316485Sdavidcs if (!dump) 2564316485Sdavidcs return (end_line - start_line + 1) * PCI_BUF_LINE_SIZE_IN_DWORDS; 2565316485Sdavidcs 2566316485Sdavidcs for (line = start_line, pci_buf = pci_buf_start + start_line * PCI_BUF_LINE_SIZE_IN_DWORDS; 2567316485Sdavidcs line <= end_line; 2568316485Sdavidcs line++, offset += PCI_BUF_LINE_SIZE_IN_DWORDS) 2569316485Sdavidcs for (i = 0; i < PCI_BUF_LINE_SIZE_IN_DWORDS; i++, pci_buf++) 2570316485Sdavidcs dump_buf[offset + s_pci_buf_line_ind[i]] = *pci_buf; 2571316485Sdavidcs 2572316485Sdavidcs return offset; 2573316485Sdavidcs} 2574316485Sdavidcs 2575316485Sdavidcs/* Copies the DBG Bus PCI buffer to the specified buffer. 2576316485Sdavidcs * Returns the dumped size in dwords. 2577316485Sdavidcs */ 2578316485Sdavidcsstatic u32 ecore_bus_dump_pci_buf(struct ecore_hwfn *p_hwfn, 2579316485Sdavidcs struct ecore_ptt *p_ptt, 2580316485Sdavidcs u32 *dump_buf, 2581316485Sdavidcs bool dump) 2582316485Sdavidcs{ 2583316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2584316485Sdavidcs u32 next_wr_byte_offset, next_wr_line_offset; 2585316485Sdavidcs struct dbg_bus_mem_addr next_wr_phys_addr; 2586316485Sdavidcs u32 pci_buf_size_in_lines, offset = 0; 2587316485Sdavidcs 2588316485Sdavidcs pci_buf_size_in_lines = dev_data->bus.pci_buf.size / PCI_BUF_LINE_SIZE_IN_BYTES; 2589316485Sdavidcs 2590316485Sdavidcs /* Extract write pointer (physical address) */ 2591316485Sdavidcs next_wr_phys_addr.lo = ecore_rd(p_hwfn, p_ptt, DBG_REG_EXT_BUFFER_WR_PTR); 2592316485Sdavidcs next_wr_phys_addr.hi = ecore_rd(p_hwfn, p_ptt, DBG_REG_EXT_BUFFER_WR_PTR + BYTES_IN_DWORD); 2593316485Sdavidcs 2594316485Sdavidcs /* Convert write pointer to offset */ 2595316485Sdavidcs next_wr_byte_offset = ecore_phys_addr_diff(&next_wr_phys_addr, &dev_data->bus.pci_buf.phys_addr); 2596316485Sdavidcs if ((next_wr_byte_offset % PCI_BUF_LINE_SIZE_IN_BYTES) || next_wr_byte_offset > dev_data->bus.pci_buf.size) 2597316485Sdavidcs return 0; 2598316485Sdavidcs next_wr_line_offset = next_wr_byte_offset / PCI_BUF_LINE_SIZE_IN_BYTES; 2599316485Sdavidcs 2600316485Sdavidcs /* PCI buffer wrapped: first dump from write pointer to buffer end. */ 2601316485Sdavidcs if (ecore_rd(p_hwfn, p_ptt, DBG_REG_WRAP_ON_EXT_BUFFER)) 2602316485Sdavidcs offset += ecore_bus_dump_pci_buf_range(p_hwfn, dump_buf + offset, dump, next_wr_line_offset, pci_buf_size_in_lines - 1); 2603316485Sdavidcs 2604316485Sdavidcs /* Dump from buffer start until write pointer */ 2605316485Sdavidcs if (next_wr_line_offset) 2606316485Sdavidcs offset += ecore_bus_dump_pci_buf_range(p_hwfn, dump_buf + offset, dump, 0, next_wr_line_offset - 1); 2607316485Sdavidcs 2608316485Sdavidcs return offset; 2609316485Sdavidcs} 2610316485Sdavidcs 2611316485Sdavidcs/* Copies the DBG Bus recorded data to the specified buffer. 2612316485Sdavidcs * Returns the dumped size in dwords. 2613316485Sdavidcs */ 2614316485Sdavidcsstatic u32 ecore_bus_dump_data(struct ecore_hwfn *p_hwfn, 2615316485Sdavidcs struct ecore_ptt *p_ptt, 2616316485Sdavidcs u32 *dump_buf, 2617316485Sdavidcs bool dump) 2618316485Sdavidcs{ 2619316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2620316485Sdavidcs 2621316485Sdavidcs switch (dev_data->bus.target) { 2622316485Sdavidcs case DBG_BUS_TARGET_ID_INT_BUF: 2623316485Sdavidcs return ecore_bus_dump_int_buf(p_hwfn, p_ptt, dump_buf, dump); 2624316485Sdavidcs case DBG_BUS_TARGET_ID_PCI: 2625316485Sdavidcs return ecore_bus_dump_pci_buf(p_hwfn, p_ptt, dump_buf, dump); 2626316485Sdavidcs default: 2627316485Sdavidcs break; 2628316485Sdavidcs } 2629316485Sdavidcs 2630316485Sdavidcs return 0; 2631316485Sdavidcs} 2632316485Sdavidcs 2633316485Sdavidcs/* Frees the Debug Bus PCI buffer */ 2634316485Sdavidcsstatic void ecore_bus_free_pci_buf(struct ecore_hwfn *p_hwfn) 2635316485Sdavidcs{ 2636316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2637316485Sdavidcs dma_addr_t pci_buf_phys_addr; 2638316485Sdavidcs void *virt_addr_lo; 2639316485Sdavidcs u32 *pci_buf; 2640316485Sdavidcs 2641316485Sdavidcs /* Extract PCI buffer pointer from virtual address */ 2642316485Sdavidcs virt_addr_lo = &dev_data->bus.pci_buf.virt_addr.lo; 2643337519Sdavidcs pci_buf = (u32 *)(osal_uintptr_t)*((u64 *)virt_addr_lo); 2644316485Sdavidcs 2645316485Sdavidcs if (!dev_data->bus.pci_buf.size) 2646316485Sdavidcs return; 2647316485Sdavidcs 2648316485Sdavidcs OSAL_MEMCPY(&pci_buf_phys_addr, &dev_data->bus.pci_buf.phys_addr, sizeof(pci_buf_phys_addr)); 2649316485Sdavidcs 2650316485Sdavidcs OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, pci_buf, pci_buf_phys_addr, dev_data->bus.pci_buf.size); 2651316485Sdavidcs 2652316485Sdavidcs dev_data->bus.pci_buf.size = 0; 2653316485Sdavidcs} 2654316485Sdavidcs 2655316485Sdavidcs/* Dumps the list of DBG Bus inputs (blocks/Storms) to the specified buffer. 2656316485Sdavidcs * Returns the dumped size in dwords. 2657316485Sdavidcs */ 2658316485Sdavidcsstatic u32 ecore_bus_dump_inputs(struct ecore_hwfn *p_hwfn, 2659316485Sdavidcs u32 *dump_buf, 2660316485Sdavidcs bool dump) 2661316485Sdavidcs{ 2662316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2663316485Sdavidcs char storm_name[8] = "?storm"; 2664316485Sdavidcs u32 block_id, offset = 0; 2665316485Sdavidcs u8 storm_id; 2666316485Sdavidcs 2667316485Sdavidcs /* Store storms */ 2668316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 2669316485Sdavidcs struct dbg_bus_storm_data *storm_bus = &dev_data->bus.storms[storm_id]; 2670316485Sdavidcs struct storm_defs *storm = &s_storm_defs[storm_id]; 2671316485Sdavidcs 2672316485Sdavidcs if (!dev_data->bus.storms[storm_id].enabled) 2673316485Sdavidcs continue; 2674316485Sdavidcs 2675316485Sdavidcs /* Dump section header */ 2676316485Sdavidcs storm_name[0] = storm->letter; 2677316485Sdavidcs offset += ecore_dump_section_hdr(dump_buf + offset, dump, "bus_input", 3); 2678316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "name", storm_name); 2679316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "id", storm_bus->hw_id); 2680316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "mode", s_storm_mode_defs[storm_bus->mode].name); 2681316485Sdavidcs } 2682316485Sdavidcs 2683316485Sdavidcs /* Store blocks */ 2684316485Sdavidcs for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 2685316485Sdavidcs struct dbg_bus_block_data *block_bus = &dev_data->bus.blocks[block_id]; 2686316485Sdavidcs struct block_defs *block = s_block_defs[block_id]; 2687316485Sdavidcs 2688316485Sdavidcs if (!GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_ENABLE_MASK)) 2689316485Sdavidcs continue; 2690316485Sdavidcs 2691316485Sdavidcs /* Dump section header */ 2692316485Sdavidcs offset += ecore_dump_section_hdr(dump_buf + offset, dump, "bus_input", 4); 2693316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "name", block->name); 2694316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "line", block_bus->line_num); 2695316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "en", GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_ENABLE_MASK)); 2696316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "shr", GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_RIGHT_SHIFT)); 2697316485Sdavidcs } 2698316485Sdavidcs 2699316485Sdavidcs return offset; 2700316485Sdavidcs} 2701316485Sdavidcs 2702316485Sdavidcs/* Dumps the Debug Bus header (params, inputs, data header) to the specified 2703316485Sdavidcs * buffer. Returns the dumped size in dwords. 2704316485Sdavidcs */ 2705316485Sdavidcsstatic u32 ecore_bus_dump_hdr(struct ecore_hwfn *p_hwfn, 2706316485Sdavidcs struct ecore_ptt *p_ptt, 2707316485Sdavidcs u32 *dump_buf, 2708316485Sdavidcs bool dump) 2709316485Sdavidcs{ 2710316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2711316485Sdavidcs char hw_id_mask_str[16]; 2712316485Sdavidcs u32 offset = 0; 2713316485Sdavidcs 2714316485Sdavidcs if (OSAL_SNPRINTF(hw_id_mask_str, sizeof(hw_id_mask_str), "0x%x", dev_data->bus.hw_id_mask) < 0) 2715316485Sdavidcs DP_NOTICE(p_hwfn, true, "Unexpected debug error: invalid HW ID mask\n"); 2716316485Sdavidcs 2717316485Sdavidcs /* Dump global params */ 2718316485Sdavidcs offset += ecore_dump_common_global_params(p_hwfn, p_ptt, dump_buf + offset, dump, 5); 2719316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "dump-type", "debug-bus"); 2720316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "wrap-mode", dev_data->bus.one_shot_en ? "one-shot" : "wrap-around"); 2721316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "hw-dwords", dev_data->bus.hw_dwords); 2722316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "hw-id-mask", hw_id_mask_str); 2723316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "target", s_dbg_target_names[dev_data->bus.target]); 2724316485Sdavidcs 2725316485Sdavidcs offset += ecore_bus_dump_inputs(p_hwfn, dump_buf + offset, dump); 2726316485Sdavidcs 2727316485Sdavidcs if (dev_data->bus.target != DBG_BUS_TARGET_ID_NIG) { 2728316485Sdavidcs u32 recorded_dwords = 0; 2729316485Sdavidcs 2730316485Sdavidcs if (dump) 2731316485Sdavidcs recorded_dwords = ecore_bus_dump_data(p_hwfn, p_ptt, OSAL_NULL, false); 2732316485Sdavidcs 2733316485Sdavidcs offset += ecore_dump_section_hdr(dump_buf + offset, dump, "bus_data", 1); 2734316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "size", recorded_dwords); 2735316485Sdavidcs } 2736316485Sdavidcs 2737316485Sdavidcs return offset; 2738316485Sdavidcs} 2739316485Sdavidcs 2740337519Sdavidcsstatic bool ecore_is_mode_match(struct ecore_hwfn *p_hwfn, 2741316485Sdavidcs u16 *modes_buf_offset) 2742316485Sdavidcs{ 2743316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2744316485Sdavidcs bool arg1, arg2; 2745316485Sdavidcs u8 tree_val; 2746316485Sdavidcs 2747316485Sdavidcs /* Get next element from modes tree buffer */ 2748337519Sdavidcs tree_val = ((u8 *)s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr)[(*modes_buf_offset)++]; 2749316485Sdavidcs 2750316485Sdavidcs switch (tree_val) { 2751316485Sdavidcs case INIT_MODE_OP_NOT: 2752316485Sdavidcs return !ecore_is_mode_match(p_hwfn, modes_buf_offset); 2753316485Sdavidcs case INIT_MODE_OP_OR: 2754316485Sdavidcs case INIT_MODE_OP_AND: 2755316485Sdavidcs arg1 = ecore_is_mode_match(p_hwfn, modes_buf_offset); 2756316485Sdavidcs arg2 = ecore_is_mode_match(p_hwfn, modes_buf_offset); 2757316485Sdavidcs return (tree_val == INIT_MODE_OP_OR) ? (arg1 || arg2) : (arg1 && arg2); 2758316485Sdavidcs default: return dev_data->mode_enable[tree_val - MAX_INIT_MODE_OPS] > 0; 2759316485Sdavidcs } 2760316485Sdavidcs} 2761316485Sdavidcs 2762316485Sdavidcs/* Returns true if the specified entity (indicated by GRC param) should be 2763316485Sdavidcs * included in the dump, false otherwise. 2764316485Sdavidcs */ 2765316485Sdavidcsstatic bool ecore_grc_is_included(struct ecore_hwfn *p_hwfn, 2766316485Sdavidcs enum dbg_grc_params grc_param) 2767316485Sdavidcs{ 2768316485Sdavidcs return ecore_grc_get_param(p_hwfn, grc_param) > 0; 2769316485Sdavidcs} 2770316485Sdavidcs 2771316485Sdavidcs/* Returns true of the specified Storm should be included in the dump, false 2772316485Sdavidcs * otherwise. 2773316485Sdavidcs */ 2774316485Sdavidcsstatic bool ecore_grc_is_storm_included(struct ecore_hwfn *p_hwfn, 2775316485Sdavidcs enum dbg_storms storm) 2776316485Sdavidcs{ 2777316485Sdavidcs return ecore_grc_get_param(p_hwfn, (enum dbg_grc_params)storm) > 0; 2778316485Sdavidcs} 2779316485Sdavidcs 2780316485Sdavidcs/* Returns true if the specified memory should be included in the dump, false 2781316485Sdavidcs * otherwise. 2782316485Sdavidcs */ 2783316485Sdavidcsstatic bool ecore_grc_is_mem_included(struct ecore_hwfn *p_hwfn, 2784316485Sdavidcs enum block_id block_id, 2785316485Sdavidcs u8 mem_group_id) 2786316485Sdavidcs{ 2787316485Sdavidcs struct block_defs *block = s_block_defs[block_id]; 2788316485Sdavidcs u8 i; 2789316485Sdavidcs 2790316485Sdavidcs /* Check Storm match */ 2791316485Sdavidcs if (block->associated_to_storm && 2792316485Sdavidcs !ecore_grc_is_storm_included(p_hwfn, (enum dbg_storms)block->storm_id)) 2793316485Sdavidcs return false; 2794316485Sdavidcs 2795316485Sdavidcs for (i = 0; i < NUM_BIG_RAM_TYPES; i++) { 2796316485Sdavidcs struct big_ram_defs *big_ram = &s_big_ram_defs[i]; 2797316485Sdavidcs 2798316485Sdavidcs if (mem_group_id == big_ram->mem_group_id || mem_group_id == big_ram->ram_mem_group_id) 2799316485Sdavidcs return ecore_grc_is_included(p_hwfn, big_ram->grc_param); 2800316485Sdavidcs } 2801316485Sdavidcs 2802316485Sdavidcs switch (mem_group_id) { 2803316485Sdavidcs case MEM_GROUP_PXP_ILT: 2804316485Sdavidcs case MEM_GROUP_PXP_MEM: 2805316485Sdavidcs return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PXP); 2806316485Sdavidcs case MEM_GROUP_RAM: 2807316485Sdavidcs return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_RAM); 2808316485Sdavidcs case MEM_GROUP_PBUF: 2809316485Sdavidcs return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PBUF); 2810316485Sdavidcs case MEM_GROUP_CAU_MEM: 2811316485Sdavidcs case MEM_GROUP_CAU_SB: 2812316485Sdavidcs case MEM_GROUP_CAU_PI: 2813316485Sdavidcs return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CAU); 2814316485Sdavidcs case MEM_GROUP_QM_MEM: 2815316485Sdavidcs return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_QM); 2816316485Sdavidcs case MEM_GROUP_CFC_MEM: 2817316485Sdavidcs case MEM_GROUP_CONN_CFC_MEM: 2818316485Sdavidcs case MEM_GROUP_TASK_CFC_MEM: 2819320162Sdavidcs return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CFC) || ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM_CTX); 2820316485Sdavidcs case MEM_GROUP_IGU_MEM: 2821316485Sdavidcs case MEM_GROUP_IGU_MSIX: 2822316485Sdavidcs return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IGU); 2823316485Sdavidcs case MEM_GROUP_MULD_MEM: 2824316485Sdavidcs return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MULD); 2825316485Sdavidcs case MEM_GROUP_PRS_MEM: 2826316485Sdavidcs return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PRS); 2827316485Sdavidcs case MEM_GROUP_DMAE_MEM: 2828316485Sdavidcs return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_DMAE); 2829316485Sdavidcs case MEM_GROUP_TM_MEM: 2830316485Sdavidcs return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_TM); 2831316485Sdavidcs case MEM_GROUP_SDM_MEM: 2832316485Sdavidcs return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_SDM); 2833316485Sdavidcs case MEM_GROUP_TDIF_CTX: 2834316485Sdavidcs case MEM_GROUP_RDIF_CTX: 2835316485Sdavidcs return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_DIF); 2836316485Sdavidcs case MEM_GROUP_CM_MEM: 2837316485Sdavidcs return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM); 2838316485Sdavidcs case MEM_GROUP_IOR: 2839316485Sdavidcs return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IOR); 2840316485Sdavidcs default: 2841316485Sdavidcs return true; 2842316485Sdavidcs } 2843316485Sdavidcs} 2844316485Sdavidcs 2845316485Sdavidcs/* Stalls all Storms */ 2846316485Sdavidcsstatic void ecore_grc_stall_storms(struct ecore_hwfn *p_hwfn, 2847316485Sdavidcs struct ecore_ptt *p_ptt, 2848316485Sdavidcs bool stall) 2849316485Sdavidcs{ 2850316485Sdavidcs u32 reg_addr; 2851316485Sdavidcs u8 storm_id; 2852316485Sdavidcs 2853316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 2854316485Sdavidcs if (!ecore_grc_is_storm_included(p_hwfn, (enum dbg_storms)storm_id)) 2855316485Sdavidcs continue; 2856316485Sdavidcs 2857316485Sdavidcs reg_addr = s_storm_defs[storm_id].sem_fast_mem_addr + SEM_FAST_REG_STALL_0_BB_K2; 2858316485Sdavidcs ecore_wr(p_hwfn, p_ptt, reg_addr, stall ? 1 : 0); 2859316485Sdavidcs } 2860316485Sdavidcs 2861316485Sdavidcs OSAL_MSLEEP(STALL_DELAY_MS); 2862316485Sdavidcs} 2863316485Sdavidcs 2864316485Sdavidcs/* Takes all blocks out of reset */ 2865316485Sdavidcsstatic void ecore_grc_unreset_blocks(struct ecore_hwfn *p_hwfn, 2866316485Sdavidcs struct ecore_ptt *p_ptt) 2867316485Sdavidcs{ 2868316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2869316485Sdavidcs u32 reg_val[MAX_DBG_RESET_REGS] = { 0 }; 2870316485Sdavidcs u32 block_id, i; 2871316485Sdavidcs 2872316485Sdavidcs /* Fill reset regs values */ 2873316485Sdavidcs for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 2874316485Sdavidcs struct block_defs *block = s_block_defs[block_id]; 2875316485Sdavidcs 2876320162Sdavidcs if (block->exists[dev_data->chip_id] && block->has_reset_bit && block->unreset) 2877316485Sdavidcs reg_val[block->reset_reg] |= (1 << block->reset_bit_offset); 2878316485Sdavidcs } 2879316485Sdavidcs 2880316485Sdavidcs /* Write reset registers */ 2881316485Sdavidcs for (i = 0; i < MAX_DBG_RESET_REGS; i++) { 2882316485Sdavidcs if (!s_reset_regs_defs[i].exists[dev_data->chip_id]) 2883316485Sdavidcs continue; 2884316485Sdavidcs 2885320162Sdavidcs reg_val[i] |= s_reset_regs_defs[i].unreset_val[dev_data->chip_id]; 2886316485Sdavidcs 2887316485Sdavidcs if (reg_val[i]) 2888316485Sdavidcs ecore_wr(p_hwfn, p_ptt, s_reset_regs_defs[i].addr + RESET_REG_UNRESET_OFFSET, reg_val[i]); 2889316485Sdavidcs } 2890316485Sdavidcs} 2891316485Sdavidcs 2892316485Sdavidcs/* Returns the attention block data of the specified block */ 2893316485Sdavidcsstatic const struct dbg_attn_block_type_data* ecore_get_block_attn_data(enum block_id block_id, 2894316485Sdavidcs enum dbg_attn_type attn_type) 2895316485Sdavidcs{ 2896337519Sdavidcs const struct dbg_attn_block *base_attn_block_arr = (const struct dbg_attn_block *)s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr; 2897316485Sdavidcs 2898316485Sdavidcs return &base_attn_block_arr[block_id].per_type_data[attn_type]; 2899316485Sdavidcs} 2900316485Sdavidcs 2901316485Sdavidcs/* Returns the attention registers of the specified block */ 2902316485Sdavidcsstatic const struct dbg_attn_reg* ecore_get_block_attn_regs(enum block_id block_id, 2903316485Sdavidcs enum dbg_attn_type attn_type, 2904316485Sdavidcs u8 *num_attn_regs) 2905316485Sdavidcs{ 2906316485Sdavidcs const struct dbg_attn_block_type_data *block_type_data = ecore_get_block_attn_data(block_id, attn_type); 2907316485Sdavidcs 2908316485Sdavidcs *num_attn_regs = block_type_data->num_regs; 2909316485Sdavidcs 2910337519Sdavidcs return &((const struct dbg_attn_reg *)s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)[block_type_data->regs_offset]; 2911316485Sdavidcs} 2912316485Sdavidcs 2913316485Sdavidcs/* For each block, clear the status of all parities */ 2914316485Sdavidcsstatic void ecore_grc_clear_all_prty(struct ecore_hwfn *p_hwfn, 2915316485Sdavidcs struct ecore_ptt *p_ptt) 2916316485Sdavidcs{ 2917316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2918316485Sdavidcs const struct dbg_attn_reg *attn_reg_arr; 2919316485Sdavidcs u8 reg_idx, num_attn_regs; 2920316485Sdavidcs u32 block_id; 2921316485Sdavidcs 2922316485Sdavidcs for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 2923316485Sdavidcs if (dev_data->block_in_reset[block_id]) 2924316485Sdavidcs continue; 2925316485Sdavidcs 2926316485Sdavidcs attn_reg_arr = ecore_get_block_attn_regs((enum block_id)block_id, ATTN_TYPE_PARITY, &num_attn_regs); 2927316485Sdavidcs 2928316485Sdavidcs for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) { 2929316485Sdavidcs const struct dbg_attn_reg *reg_data = &attn_reg_arr[reg_idx]; 2930316485Sdavidcs u16 modes_buf_offset; 2931316485Sdavidcs bool eval_mode; 2932316485Sdavidcs 2933316485Sdavidcs /* Check mode */ 2934316485Sdavidcs eval_mode = GET_FIELD(reg_data->mode.data, DBG_MODE_HDR_EVAL_MODE) > 0; 2935316485Sdavidcs modes_buf_offset = GET_FIELD(reg_data->mode.data, DBG_MODE_HDR_MODES_BUF_OFFSET); 2936316485Sdavidcs 2937316485Sdavidcs /* If Mode match: clear parity status */ 2938316485Sdavidcs if (!eval_mode || ecore_is_mode_match(p_hwfn, &modes_buf_offset)) 2939316485Sdavidcs ecore_rd(p_hwfn, p_ptt, DWORDS_TO_BYTES(reg_data->sts_clr_address)); 2940316485Sdavidcs } 2941316485Sdavidcs } 2942316485Sdavidcs} 2943316485Sdavidcs 2944316485Sdavidcs/* Dumps GRC registers section header. Returns the dumped size in dwords. 2945316485Sdavidcs * the following parameters are dumped: 2946316485Sdavidcs * - count: no. of dumped entries 2947316485Sdavidcs * - split: split type 2948316485Sdavidcs * - id: split ID (dumped only if split_id >= 0) 2949316485Sdavidcs * - param_name: user parameter value (dumped only if param_name != OSAL_NULL 2950316485Sdavidcs * and param_val != OSAL_NULL). 2951316485Sdavidcs */ 2952316485Sdavidcsstatic u32 ecore_grc_dump_regs_hdr(u32 *dump_buf, 2953316485Sdavidcs bool dump, 2954316485Sdavidcs u32 num_reg_entries, 2955316485Sdavidcs const char *split_type, 2956316485Sdavidcs int split_id, 2957316485Sdavidcs const char *param_name, 2958316485Sdavidcs const char *param_val) 2959316485Sdavidcs{ 2960316485Sdavidcs u8 num_params = 2 + (split_id >= 0 ? 1 : 0) + (param_name ? 1 : 0); 2961316485Sdavidcs u32 offset = 0; 2962316485Sdavidcs 2963316485Sdavidcs offset += ecore_dump_section_hdr(dump_buf + offset, dump, "grc_regs", num_params); 2964316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "count", num_reg_entries); 2965316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "split", split_type); 2966316485Sdavidcs if (split_id >= 0) 2967316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "id", split_id); 2968316485Sdavidcs if (param_name && param_val) 2969316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, param_name, param_val); 2970316485Sdavidcs 2971316485Sdavidcs return offset; 2972316485Sdavidcs} 2973316485Sdavidcs 2974337519Sdavidcs/* Reads the specified registers into the specified buffer. 2975337519Sdavidcs * The addr and len arguments are specified in dwords. 2976337519Sdavidcs */ 2977337519Sdavidcsvoid ecore_read_regs(struct ecore_hwfn *p_hwfn, 2978337519Sdavidcs struct ecore_ptt *p_ptt, 2979337519Sdavidcs u32 *buf, 2980337519Sdavidcs u32 addr, 2981337519Sdavidcs u32 len) 2982337519Sdavidcs{ 2983337519Sdavidcs u32 i; 2984337519Sdavidcs 2985337519Sdavidcs for (i = 0; i < len; i++) 2986337519Sdavidcs buf[i] = ecore_rd(p_hwfn, p_ptt, DWORDS_TO_BYTES(addr + i)); 2987337519Sdavidcs} 2988337519Sdavidcs 2989316485Sdavidcs/* Dumps the GRC registers in the specified address range. 2990316485Sdavidcs * Returns the dumped size in dwords. 2991316485Sdavidcs * The addr and len arguments are specified in dwords. 2992316485Sdavidcs */ 2993316485Sdavidcsstatic u32 ecore_grc_dump_addr_range(struct ecore_hwfn *p_hwfn, 2994337519Sdavidcs struct ecore_ptt *p_ptt, 2995337519Sdavidcs u32 *dump_buf, 2996337519Sdavidcs bool dump, 2997337519Sdavidcs u32 addr, 2998337519Sdavidcs u32 len, 2999337519Sdavidcs bool wide_bus) 3000316485Sdavidcs{ 3001337519Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3002316485Sdavidcs 3003316485Sdavidcs if (!dump) 3004316485Sdavidcs return len; 3005316485Sdavidcs 3006337519Sdavidcs /* Print log if needed */ 3007337519Sdavidcs dev_data->num_regs_read += len; 3008337519Sdavidcs if (dev_data->num_regs_read >= s_platform_defs[dev_data->platform_id].log_thresh) { 3009337519Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "Dumping %d registers...\n", dev_data->num_regs_read); 3010337519Sdavidcs dev_data->num_regs_read = 0; 3011337519Sdavidcs } 3012316485Sdavidcs 3013337519Sdavidcs /* Try reading using DMAE */ 3014337519Sdavidcs if (dev_data->use_dmae && (len >= s_platform_defs[dev_data->platform_id].dmae_thresh || (PROTECT_WIDE_BUS && wide_bus))) { 3015337519Sdavidcs if (!ecore_dmae_grc2host(p_hwfn, p_ptt, DWORDS_TO_BYTES(addr), (u64)(osal_uintptr_t)(dump_buf), len, OSAL_NULL)) 3016337519Sdavidcs return len; 3017337519Sdavidcs dev_data->use_dmae = 0; 3018337519Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "Failed reading from chip using DMAE, using GRC instead\n"); 3019337519Sdavidcs } 3020337519Sdavidcs 3021337519Sdavidcs /* Read registers */ 3022337519Sdavidcs ecore_read_regs(p_hwfn, p_ptt, dump_buf, addr, len); 3023337519Sdavidcs 3024337519Sdavidcs return len; 3025316485Sdavidcs} 3026316485Sdavidcs 3027316485Sdavidcs/* Dumps GRC registers sequence header. Returns the dumped size in dwords. 3028316485Sdavidcs * The addr and len arguments are specified in dwords. 3029316485Sdavidcs */ 3030316485Sdavidcsstatic u32 ecore_grc_dump_reg_entry_hdr(u32 *dump_buf, 3031316485Sdavidcs bool dump, 3032316485Sdavidcs u32 addr, 3033316485Sdavidcs u32 len) 3034316485Sdavidcs{ 3035316485Sdavidcs if (dump) 3036316485Sdavidcs *dump_buf = addr | (len << REG_DUMP_LEN_SHIFT); 3037316485Sdavidcs 3038316485Sdavidcs return 1; 3039316485Sdavidcs} 3040316485Sdavidcs 3041316485Sdavidcs/* Dumps GRC registers sequence. Returns the dumped size in dwords. 3042316485Sdavidcs * The addr and len arguments are specified in dwords. 3043316485Sdavidcs */ 3044316485Sdavidcsstatic u32 ecore_grc_dump_reg_entry(struct ecore_hwfn *p_hwfn, 3045337519Sdavidcs struct ecore_ptt *p_ptt, 3046337519Sdavidcs u32 *dump_buf, 3047337519Sdavidcs bool dump, 3048337519Sdavidcs u32 addr, 3049337519Sdavidcs u32 len, 3050337519Sdavidcs bool wide_bus) 3051316485Sdavidcs{ 3052316485Sdavidcs u32 offset = 0; 3053316485Sdavidcs 3054316485Sdavidcs offset += ecore_grc_dump_reg_entry_hdr(dump_buf, dump, addr, len); 3055316485Sdavidcs offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, dump, addr, len, wide_bus); 3056316485Sdavidcs 3057316485Sdavidcs return offset; 3058316485Sdavidcs} 3059316485Sdavidcs 3060316485Sdavidcs/* Dumps GRC registers sequence with skip cycle. 3061316485Sdavidcs * Returns the dumped size in dwords. 3062316485Sdavidcs * - addr: start GRC address in dwords 3063316485Sdavidcs * - total_len: total no. of dwords to dump 3064337519Sdavidcs * - read_len: no. consecutive dwords to read 3065316485Sdavidcs * - skip_len: no. of dwords to skip (and fill with zeros) 3066316485Sdavidcs */ 3067316485Sdavidcsstatic u32 ecore_grc_dump_reg_entry_skip(struct ecore_hwfn *p_hwfn, 3068316485Sdavidcs struct ecore_ptt *p_ptt, 3069316485Sdavidcs u32 *dump_buf, 3070316485Sdavidcs bool dump, 3071316485Sdavidcs u32 addr, 3072316485Sdavidcs u32 total_len, 3073316485Sdavidcs u32 read_len, 3074316485Sdavidcs u32 skip_len) 3075316485Sdavidcs{ 3076316485Sdavidcs u32 offset = 0, reg_offset = 0; 3077316485Sdavidcs 3078316485Sdavidcs offset += ecore_grc_dump_reg_entry_hdr(dump_buf, dump, addr, total_len); 3079316485Sdavidcs 3080316485Sdavidcs if (!dump) 3081316485Sdavidcs return offset + total_len; 3082316485Sdavidcs 3083316485Sdavidcs while (reg_offset < total_len) { 3084316485Sdavidcs u32 curr_len = OSAL_MIN_T(u32, read_len, total_len - reg_offset); 3085316485Sdavidcs 3086316485Sdavidcs offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, dump, addr, curr_len, false); 3087316485Sdavidcs reg_offset += curr_len; 3088316485Sdavidcs addr += curr_len; 3089316485Sdavidcs 3090316485Sdavidcs if (reg_offset < total_len) { 3091316485Sdavidcs curr_len = OSAL_MIN_T(u32, skip_len, total_len - skip_len); 3092316485Sdavidcs OSAL_MEMSET(dump_buf + offset, 0, DWORDS_TO_BYTES(curr_len)); 3093316485Sdavidcs offset += curr_len; 3094316485Sdavidcs reg_offset += curr_len; 3095316485Sdavidcs addr += curr_len; 3096316485Sdavidcs } 3097316485Sdavidcs } 3098316485Sdavidcs 3099316485Sdavidcs return offset; 3100316485Sdavidcs} 3101316485Sdavidcs 3102316485Sdavidcs/* Dumps GRC registers entries. Returns the dumped size in dwords. */ 3103316485Sdavidcsstatic u32 ecore_grc_dump_regs_entries(struct ecore_hwfn *p_hwfn, 3104316485Sdavidcs struct ecore_ptt *p_ptt, 3105316485Sdavidcs struct dbg_array input_regs_arr, 3106316485Sdavidcs u32 *dump_buf, 3107316485Sdavidcs bool dump, 3108316485Sdavidcs bool block_enable[MAX_BLOCK_ID], 3109316485Sdavidcs u32 *num_dumped_reg_entries) 3110316485Sdavidcs{ 3111316485Sdavidcs u32 i, offset = 0, input_offset = 0; 3112316485Sdavidcs bool mode_match = true; 3113337519Sdavidcs 3114316485Sdavidcs *num_dumped_reg_entries = 0; 3115316485Sdavidcs 3116316485Sdavidcs while (input_offset < input_regs_arr.size_in_dwords) { 3117337519Sdavidcs const struct dbg_dump_cond_hdr *cond_hdr = (const struct dbg_dump_cond_hdr *)&input_regs_arr.ptr[input_offset++]; 3118316485Sdavidcs u16 modes_buf_offset; 3119316485Sdavidcs bool eval_mode; 3120316485Sdavidcs 3121316485Sdavidcs /* Check mode/block */ 3122316485Sdavidcs eval_mode = GET_FIELD(cond_hdr->mode.data, DBG_MODE_HDR_EVAL_MODE) > 0; 3123316485Sdavidcs if (eval_mode) { 3124316485Sdavidcs modes_buf_offset = GET_FIELD(cond_hdr->mode.data, DBG_MODE_HDR_MODES_BUF_OFFSET); 3125316485Sdavidcs mode_match = ecore_is_mode_match(p_hwfn, &modes_buf_offset); 3126316485Sdavidcs } 3127316485Sdavidcs 3128316485Sdavidcs if (!mode_match || !block_enable[cond_hdr->block_id]) { 3129316485Sdavidcs input_offset += cond_hdr->data_size; 3130316485Sdavidcs continue; 3131316485Sdavidcs } 3132316485Sdavidcs 3133316485Sdavidcs for (i = 0; i < cond_hdr->data_size; i++, input_offset++) { 3134337519Sdavidcs const struct dbg_dump_reg *reg = (const struct dbg_dump_reg *)&input_regs_arr.ptr[input_offset]; 3135316485Sdavidcs 3136316485Sdavidcs offset += ecore_grc_dump_reg_entry(p_hwfn, p_ptt, dump_buf + offset, dump, 3137337519Sdavidcs GET_FIELD(reg->data, DBG_DUMP_REG_ADDRESS), 3138337519Sdavidcs GET_FIELD(reg->data, DBG_DUMP_REG_LENGTH), 3139337519Sdavidcs GET_FIELD(reg->data, DBG_DUMP_REG_WIDE_BUS)); 3140316485Sdavidcs (*num_dumped_reg_entries)++; 3141316485Sdavidcs } 3142316485Sdavidcs } 3143316485Sdavidcs 3144316485Sdavidcs return offset; 3145316485Sdavidcs} 3146316485Sdavidcs 3147316485Sdavidcs/* Dumps GRC registers entries. Returns the dumped size in dwords. */ 3148316485Sdavidcsstatic u32 ecore_grc_dump_split_data(struct ecore_hwfn *p_hwfn, 3149316485Sdavidcs struct ecore_ptt *p_ptt, 3150316485Sdavidcs struct dbg_array input_regs_arr, 3151316485Sdavidcs u32 *dump_buf, 3152316485Sdavidcs bool dump, 3153316485Sdavidcs bool block_enable[MAX_BLOCK_ID], 3154316485Sdavidcs const char *split_type_name, 3155316485Sdavidcs u32 split_id, 3156316485Sdavidcs const char *param_name, 3157316485Sdavidcs const char *param_val) 3158316485Sdavidcs{ 3159316485Sdavidcs u32 num_dumped_reg_entries, offset; 3160316485Sdavidcs 3161316485Sdavidcs /* Calculate register dump header size (and skip it for now) */ 3162316485Sdavidcs offset = ecore_grc_dump_regs_hdr(dump_buf, false, 0, split_type_name, split_id, param_name, param_val); 3163316485Sdavidcs 3164316485Sdavidcs /* Dump registers */ 3165316485Sdavidcs offset += ecore_grc_dump_regs_entries(p_hwfn, p_ptt, input_regs_arr, dump_buf + offset, dump, block_enable, &num_dumped_reg_entries); 3166316485Sdavidcs 3167316485Sdavidcs /* Write register dump header */ 3168316485Sdavidcs if (dump && num_dumped_reg_entries > 0) 3169316485Sdavidcs ecore_grc_dump_regs_hdr(dump_buf, dump, num_dumped_reg_entries, split_type_name, split_id, param_name, param_val); 3170316485Sdavidcs 3171316485Sdavidcs return num_dumped_reg_entries > 0 ? offset : 0; 3172316485Sdavidcs} 3173316485Sdavidcs 3174316485Sdavidcs/* Dumps registers according to the input registers array. Returns the dumped 3175316485Sdavidcs * size in dwords. 3176316485Sdavidcs */ 3177316485Sdavidcsstatic u32 ecore_grc_dump_registers(struct ecore_hwfn *p_hwfn, 3178316485Sdavidcs struct ecore_ptt *p_ptt, 3179316485Sdavidcs u32 *dump_buf, 3180316485Sdavidcs bool dump, 3181316485Sdavidcs bool block_enable[MAX_BLOCK_ID], 3182316485Sdavidcs const char *param_name, 3183316485Sdavidcs const char *param_val) 3184316485Sdavidcs{ 3185316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3186316485Sdavidcs struct chip_platform_defs *chip_platform; 3187316485Sdavidcs u32 offset = 0, input_offset = 0; 3188316485Sdavidcs u8 port_id, pf_id, vf_id; 3189316485Sdavidcs 3190316485Sdavidcs chip_platform = &s_chip_defs[dev_data->chip_id].per_platform[dev_data->platform_id]; 3191316485Sdavidcs 3192316485Sdavidcs while (input_offset < s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].size_in_dwords) { 3193316485Sdavidcs const struct dbg_dump_split_hdr *split_hdr; 3194316485Sdavidcs struct dbg_array curr_input_regs_arr; 3195316485Sdavidcs u32 split_data_size; 3196316485Sdavidcs u8 split_type_id; 3197316485Sdavidcs 3198337519Sdavidcs split_hdr = (const struct dbg_dump_split_hdr *)&s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset++]; 3199316485Sdavidcs split_type_id = GET_FIELD(split_hdr->hdr, DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID); 3200316485Sdavidcs split_data_size = GET_FIELD(split_hdr->hdr, DBG_DUMP_SPLIT_HDR_DATA_SIZE); 3201316485Sdavidcs curr_input_regs_arr.ptr = &s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset]; 3202316485Sdavidcs curr_input_regs_arr.size_in_dwords = split_data_size; 3203316485Sdavidcs 3204316485Sdavidcs switch(split_type_id) { 3205316485Sdavidcs case SPLIT_TYPE_NONE: 3206316485Sdavidcs offset += ecore_grc_dump_split_data(p_hwfn, p_ptt, curr_input_regs_arr, dump_buf + offset, dump, block_enable, "eng", (u32)(-1), param_name, param_val); 3207316485Sdavidcs break; 3208316485Sdavidcs 3209316485Sdavidcs case SPLIT_TYPE_PORT: 3210316485Sdavidcs for (port_id = 0; port_id < chip_platform->num_ports; port_id++) { 3211316485Sdavidcs if (dump) 3212316485Sdavidcs ecore_port_pretend(p_hwfn, p_ptt, port_id); 3213316485Sdavidcs offset += ecore_grc_dump_split_data(p_hwfn, p_ptt, curr_input_regs_arr, dump_buf + offset, dump, block_enable, "port", port_id, param_name, param_val); 3214316485Sdavidcs } 3215316485Sdavidcs break; 3216316485Sdavidcs 3217316485Sdavidcs case SPLIT_TYPE_PF: 3218316485Sdavidcs case SPLIT_TYPE_PORT_PF: 3219316485Sdavidcs for (pf_id = 0; pf_id < chip_platform->num_pfs; pf_id++) { 3220316485Sdavidcs if (dump) 3221316485Sdavidcs ecore_fid_pretend(p_hwfn, p_ptt, (pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT)); 3222316485Sdavidcs offset += ecore_grc_dump_split_data(p_hwfn, p_ptt, curr_input_regs_arr, dump_buf + offset, dump, block_enable, "pf", pf_id, param_name, param_val); 3223316485Sdavidcs } 3224316485Sdavidcs break; 3225316485Sdavidcs 3226316485Sdavidcs case SPLIT_TYPE_VF: 3227316485Sdavidcs for (vf_id = 0; vf_id < chip_platform->num_vfs; vf_id++) { 3228316485Sdavidcs if (dump) 3229316485Sdavidcs ecore_fid_pretend(p_hwfn, p_ptt, (1 << PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT) | (vf_id << PXP_PRETEND_CONCRETE_FID_VFID_SHIFT)); 3230316485Sdavidcs offset += ecore_grc_dump_split_data(p_hwfn, p_ptt, curr_input_regs_arr, dump_buf + offset, dump, block_enable, "vf", vf_id, param_name, param_val); 3231316485Sdavidcs } 3232316485Sdavidcs break; 3233316485Sdavidcs 3234316485Sdavidcs default: 3235316485Sdavidcs break; 3236316485Sdavidcs } 3237316485Sdavidcs 3238316485Sdavidcs input_offset += split_data_size; 3239316485Sdavidcs } 3240316485Sdavidcs 3241316485Sdavidcs /* Pretend to original PF */ 3242316485Sdavidcs if (dump) 3243316485Sdavidcs ecore_fid_pretend(p_hwfn, p_ptt, (p_hwfn->rel_pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT)); 3244316485Sdavidcs 3245316485Sdavidcs return offset; 3246316485Sdavidcs} 3247316485Sdavidcs 3248316485Sdavidcs/* Dump reset registers. Returns the dumped size in dwords. */ 3249316485Sdavidcsstatic u32 ecore_grc_dump_reset_regs(struct ecore_hwfn *p_hwfn, 3250316485Sdavidcs struct ecore_ptt *p_ptt, 3251316485Sdavidcs u32 *dump_buf, 3252316485Sdavidcs bool dump) 3253316485Sdavidcs{ 3254316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3255316485Sdavidcs u32 i, offset = 0, num_regs = 0; 3256316485Sdavidcs 3257316485Sdavidcs /* Calculate header size */ 3258316485Sdavidcs offset += ecore_grc_dump_regs_hdr(dump_buf, false, 0, "eng", -1, OSAL_NULL, OSAL_NULL); 3259316485Sdavidcs 3260316485Sdavidcs /* Write reset registers */ 3261316485Sdavidcs for (i = 0; i < MAX_DBG_RESET_REGS; i++) { 3262316485Sdavidcs if (!s_reset_regs_defs[i].exists[dev_data->chip_id]) 3263316485Sdavidcs continue; 3264316485Sdavidcs 3265316485Sdavidcs offset += ecore_grc_dump_reg_entry(p_hwfn, p_ptt, dump_buf + offset, dump, BYTES_TO_DWORDS(s_reset_regs_defs[i].addr), 1, false); 3266316485Sdavidcs num_regs++; 3267316485Sdavidcs } 3268316485Sdavidcs 3269316485Sdavidcs /* Write header */ 3270316485Sdavidcs if (dump) 3271316485Sdavidcs ecore_grc_dump_regs_hdr(dump_buf, true, num_regs, "eng", -1, OSAL_NULL, OSAL_NULL); 3272316485Sdavidcs 3273316485Sdavidcs return offset; 3274316485Sdavidcs} 3275316485Sdavidcs 3276316485Sdavidcs/* Dump registers that are modified during GRC Dump and therefore must be 3277316485Sdavidcs * dumped first. Returns the dumped size in dwords. 3278316485Sdavidcs */ 3279316485Sdavidcsstatic u32 ecore_grc_dump_modified_regs(struct ecore_hwfn *p_hwfn, 3280316485Sdavidcs struct ecore_ptt *p_ptt, 3281316485Sdavidcs u32 *dump_buf, 3282316485Sdavidcs bool dump) 3283316485Sdavidcs{ 3284316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3285316485Sdavidcs u32 block_id, offset = 0, num_reg_entries = 0; 3286316485Sdavidcs const struct dbg_attn_reg *attn_reg_arr; 3287316485Sdavidcs u8 storm_id, reg_idx, num_attn_regs; 3288316485Sdavidcs 3289316485Sdavidcs /* Calculate header size */ 3290316485Sdavidcs offset += ecore_grc_dump_regs_hdr(dump_buf, false, 0, "eng", -1, OSAL_NULL, OSAL_NULL); 3291316485Sdavidcs 3292316485Sdavidcs /* Write parity registers */ 3293316485Sdavidcs for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 3294316485Sdavidcs if (dev_data->block_in_reset[block_id] && dump) 3295316485Sdavidcs continue; 3296316485Sdavidcs 3297316485Sdavidcs attn_reg_arr = ecore_get_block_attn_regs((enum block_id)block_id, ATTN_TYPE_PARITY, &num_attn_regs); 3298316485Sdavidcs 3299316485Sdavidcs for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) { 3300316485Sdavidcs const struct dbg_attn_reg *reg_data = &attn_reg_arr[reg_idx]; 3301316485Sdavidcs u16 modes_buf_offset; 3302316485Sdavidcs bool eval_mode; 3303316485Sdavidcs 3304316485Sdavidcs /* Check mode */ 3305316485Sdavidcs eval_mode = GET_FIELD(reg_data->mode.data, DBG_MODE_HDR_EVAL_MODE) > 0; 3306316485Sdavidcs modes_buf_offset = GET_FIELD(reg_data->mode.data, DBG_MODE_HDR_MODES_BUF_OFFSET); 3307316485Sdavidcs if (eval_mode && !ecore_is_mode_match(p_hwfn, &modes_buf_offset)) 3308316485Sdavidcs continue; 3309316485Sdavidcs 3310316485Sdavidcs /* Mode match: read & dump registers */ 3311316485Sdavidcs offset += ecore_grc_dump_reg_entry(p_hwfn, p_ptt, dump_buf + offset, dump, reg_data->mask_address, 1, false); 3312316485Sdavidcs offset += ecore_grc_dump_reg_entry(p_hwfn, p_ptt, dump_buf + offset, dump, GET_FIELD(reg_data->data, DBG_ATTN_REG_STS_ADDRESS), 1, false); 3313316485Sdavidcs num_reg_entries += 2; 3314316485Sdavidcs } 3315316485Sdavidcs } 3316316485Sdavidcs 3317316485Sdavidcs /* Write Storm stall status registers */ 3318316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 3319316485Sdavidcs struct storm_defs *storm = &s_storm_defs[storm_id]; 3320316485Sdavidcs 3321316485Sdavidcs if (dev_data->block_in_reset[storm->block_id] && dump) 3322316485Sdavidcs continue; 3323316485Sdavidcs 3324316485Sdavidcs offset += ecore_grc_dump_reg_entry(p_hwfn, p_ptt, dump_buf + offset, dump, 3325316485Sdavidcs BYTES_TO_DWORDS(storm->sem_fast_mem_addr + SEM_FAST_REG_STALLED), 1, false); 3326316485Sdavidcs num_reg_entries++; 3327316485Sdavidcs } 3328316485Sdavidcs 3329316485Sdavidcs /* Write header */ 3330316485Sdavidcs if (dump) 3331316485Sdavidcs ecore_grc_dump_regs_hdr(dump_buf, true, num_reg_entries, "eng", -1, OSAL_NULL, OSAL_NULL); 3332316485Sdavidcs 3333316485Sdavidcs return offset; 3334316485Sdavidcs} 3335316485Sdavidcs 3336316485Sdavidcs/* Dumps registers that can't be represented in the debug arrays */ 3337316485Sdavidcsstatic u32 ecore_grc_dump_special_regs(struct ecore_hwfn *p_hwfn, 3338316485Sdavidcs struct ecore_ptt *p_ptt, 3339316485Sdavidcs u32 *dump_buf, 3340316485Sdavidcs bool dump) 3341316485Sdavidcs{ 3342316485Sdavidcs u32 offset = 0; 3343316485Sdavidcs 3344316485Sdavidcs offset += ecore_grc_dump_regs_hdr(dump_buf, dump, 2, "eng", -1, OSAL_NULL, OSAL_NULL); 3345316485Sdavidcs 3346316485Sdavidcs /* Dump R/TDIF_REG_DEBUG_ERROR_INFO_SIZE (every 8'th register should be 3347316485Sdavidcs * skipped). 3348316485Sdavidcs */ 3349316485Sdavidcs offset += ecore_grc_dump_reg_entry_skip(p_hwfn, p_ptt, dump_buf + offset, dump, BYTES_TO_DWORDS(RDIF_REG_DEBUG_ERROR_INFO), RDIF_REG_DEBUG_ERROR_INFO_SIZE, 7, 1); 3350316485Sdavidcs offset += ecore_grc_dump_reg_entry_skip(p_hwfn, p_ptt, dump_buf + offset, dump, BYTES_TO_DWORDS(TDIF_REG_DEBUG_ERROR_INFO), TDIF_REG_DEBUG_ERROR_INFO_SIZE, 7, 1); 3351316485Sdavidcs 3352316485Sdavidcs return offset; 3353316485Sdavidcs} 3354316485Sdavidcs 3355316485Sdavidcs/* Dumps a GRC memory header (section and params). Returns the dumped size in 3356316485Sdavidcs * dwords. The following parameters are dumped: 3357316485Sdavidcs * - name: dumped only if it's not OSAL_NULL. 3358316485Sdavidcs * - addr: in dwords, dumped only if name is OSAL_NULL. 3359316485Sdavidcs * - len: in dwords, always dumped. 3360316485Sdavidcs * - width: dumped if it's not zero. 3361316485Sdavidcs * - packed: dumped only if it's not false. 3362316485Sdavidcs * - mem_group: always dumped. 3363316485Sdavidcs * - is_storm: true only if the memory is related to a Storm. 3364316485Sdavidcs * - storm_letter: valid only if is_storm is true. 3365316485Sdavidcs * 3366316485Sdavidcs */ 3367316485Sdavidcsstatic u32 ecore_grc_dump_mem_hdr(struct ecore_hwfn *p_hwfn, 3368316485Sdavidcs u32 *dump_buf, 3369316485Sdavidcs bool dump, 3370316485Sdavidcs const char *name, 3371316485Sdavidcs u32 addr, 3372316485Sdavidcs u32 len, 3373316485Sdavidcs u32 bit_width, 3374316485Sdavidcs bool packed, 3375316485Sdavidcs const char *mem_group, 3376316485Sdavidcs bool is_storm, 3377316485Sdavidcs char storm_letter) 3378316485Sdavidcs{ 3379316485Sdavidcs u8 num_params = 3; 3380316485Sdavidcs u32 offset = 0; 3381316485Sdavidcs char buf[64]; 3382316485Sdavidcs 3383316485Sdavidcs if (!len) 3384316485Sdavidcs DP_NOTICE(p_hwfn, true, "Unexpected GRC Dump error: dumped memory size must be non-zero\n"); 3385316485Sdavidcs 3386316485Sdavidcs if (bit_width) 3387316485Sdavidcs num_params++; 3388316485Sdavidcs if (packed) 3389316485Sdavidcs num_params++; 3390316485Sdavidcs 3391316485Sdavidcs /* Dump section header */ 3392316485Sdavidcs offset += ecore_dump_section_hdr(dump_buf + offset, dump, "grc_mem", num_params); 3393316485Sdavidcs 3394316485Sdavidcs if (name) { 3395316485Sdavidcs 3396316485Sdavidcs /* Dump name */ 3397316485Sdavidcs if (is_storm) { 3398316485Sdavidcs OSAL_STRCPY(buf, "?STORM_"); 3399316485Sdavidcs buf[0] = storm_letter; 3400316485Sdavidcs OSAL_STRCPY(buf + OSAL_STRLEN(buf), name); 3401316485Sdavidcs } 3402316485Sdavidcs else { 3403316485Sdavidcs OSAL_STRCPY(buf, name); 3404316485Sdavidcs } 3405316485Sdavidcs 3406316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "name", buf); 3407316485Sdavidcs } 3408316485Sdavidcs else { 3409316485Sdavidcs 3410316485Sdavidcs /* Dump address */ 3411316485Sdavidcs u32 addr_in_bytes = DWORDS_TO_BYTES(addr); 3412316485Sdavidcs 3413316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "addr", addr_in_bytes); 3414316485Sdavidcs } 3415316485Sdavidcs 3416316485Sdavidcs /* Dump len */ 3417316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "len", len); 3418316485Sdavidcs 3419316485Sdavidcs /* Dump bit width */ 3420316485Sdavidcs if (bit_width) 3421316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "width", bit_width); 3422316485Sdavidcs 3423316485Sdavidcs /* Dump packed */ 3424316485Sdavidcs if (packed) 3425316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "packed", 1); 3426316485Sdavidcs 3427316485Sdavidcs /* Dump reg type */ 3428316485Sdavidcs if (is_storm) { 3429316485Sdavidcs OSAL_STRCPY(buf, "?STORM_"); 3430316485Sdavidcs buf[0] = storm_letter; 3431316485Sdavidcs OSAL_STRCPY(buf + OSAL_STRLEN(buf), mem_group); 3432316485Sdavidcs } 3433316485Sdavidcs else { 3434316485Sdavidcs OSAL_STRCPY(buf, mem_group); 3435316485Sdavidcs } 3436316485Sdavidcs 3437316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "type", buf); 3438316485Sdavidcs 3439316485Sdavidcs return offset; 3440316485Sdavidcs} 3441316485Sdavidcs 3442316485Sdavidcs/* Dumps a single GRC memory. If name is OSAL_NULL, the memory is stored by address. 3443316485Sdavidcs * Returns the dumped size in dwords. 3444316485Sdavidcs * The addr and len arguments are specified in dwords. 3445316485Sdavidcs */ 3446316485Sdavidcsstatic u32 ecore_grc_dump_mem(struct ecore_hwfn *p_hwfn, 3447337519Sdavidcs struct ecore_ptt *p_ptt, 3448337519Sdavidcs u32 *dump_buf, 3449337519Sdavidcs bool dump, 3450337519Sdavidcs const char *name, 3451337519Sdavidcs u32 addr, 3452337519Sdavidcs u32 len, 3453337519Sdavidcs bool wide_bus, 3454337519Sdavidcs u32 bit_width, 3455337519Sdavidcs bool packed, 3456337519Sdavidcs const char *mem_group, 3457337519Sdavidcs bool is_storm, 3458337519Sdavidcs char storm_letter) 3459316485Sdavidcs{ 3460316485Sdavidcs u32 offset = 0; 3461316485Sdavidcs 3462316485Sdavidcs offset += ecore_grc_dump_mem_hdr(p_hwfn, dump_buf + offset, dump, name, addr, len, bit_width, packed, mem_group, is_storm, storm_letter); 3463316485Sdavidcs offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, dump, addr, len, wide_bus); 3464316485Sdavidcs 3465316485Sdavidcs return offset; 3466316485Sdavidcs} 3467316485Sdavidcs 3468316485Sdavidcs/* Dumps GRC memories entries. Returns the dumped size in dwords. */ 3469316485Sdavidcsstatic u32 ecore_grc_dump_mem_entries(struct ecore_hwfn *p_hwfn, 3470316485Sdavidcs struct ecore_ptt *p_ptt, 3471316485Sdavidcs struct dbg_array input_mems_arr, 3472316485Sdavidcs u32 *dump_buf, 3473316485Sdavidcs bool dump) 3474316485Sdavidcs{ 3475316485Sdavidcs u32 i, offset = 0, input_offset = 0; 3476316485Sdavidcs bool mode_match = true; 3477316485Sdavidcs 3478316485Sdavidcs while (input_offset < input_mems_arr.size_in_dwords) { 3479337519Sdavidcs const struct dbg_dump_cond_hdr *cond_hdr; 3480316485Sdavidcs u16 modes_buf_offset; 3481316485Sdavidcs u32 num_entries; 3482316485Sdavidcs bool eval_mode; 3483316485Sdavidcs 3484337519Sdavidcs cond_hdr = (const struct dbg_dump_cond_hdr *)&input_mems_arr.ptr[input_offset++]; 3485316485Sdavidcs num_entries = cond_hdr->data_size / MEM_DUMP_ENTRY_SIZE_DWORDS; 3486316485Sdavidcs 3487316485Sdavidcs /* Check required mode */ 3488316485Sdavidcs eval_mode = GET_FIELD(cond_hdr->mode.data, DBG_MODE_HDR_EVAL_MODE) > 0; 3489316485Sdavidcs if (eval_mode) { 3490316485Sdavidcs modes_buf_offset = GET_FIELD(cond_hdr->mode.data, DBG_MODE_HDR_MODES_BUF_OFFSET); 3491316485Sdavidcs mode_match = ecore_is_mode_match(p_hwfn, &modes_buf_offset); 3492316485Sdavidcs } 3493316485Sdavidcs 3494316485Sdavidcs if (!mode_match) { 3495316485Sdavidcs input_offset += cond_hdr->data_size; 3496316485Sdavidcs continue; 3497316485Sdavidcs } 3498316485Sdavidcs 3499316485Sdavidcs for (i = 0; i < num_entries; i++, input_offset += MEM_DUMP_ENTRY_SIZE_DWORDS) { 3500337519Sdavidcs const struct dbg_dump_mem *mem = (const struct dbg_dump_mem *)&input_mems_arr.ptr[input_offset]; 3501316485Sdavidcs u8 mem_group_id = GET_FIELD(mem->dword0, DBG_DUMP_MEM_MEM_GROUP_ID); 3502316485Sdavidcs bool is_storm = false, mem_wide_bus; 3503316485Sdavidcs char storm_letter = 'a'; 3504316485Sdavidcs u32 mem_addr, mem_len; 3505316485Sdavidcs 3506316485Sdavidcs if (mem_group_id >= MEM_GROUPS_NUM) { 3507316485Sdavidcs DP_NOTICE(p_hwfn, true, "Invalid mem_group_id\n"); 3508316485Sdavidcs return 0; 3509316485Sdavidcs } 3510316485Sdavidcs 3511316485Sdavidcs if (!ecore_grc_is_mem_included(p_hwfn, (enum block_id)cond_hdr->block_id, mem_group_id)) 3512316485Sdavidcs continue; 3513316485Sdavidcs 3514316485Sdavidcs mem_addr = GET_FIELD(mem->dword0, DBG_DUMP_MEM_ADDRESS); 3515316485Sdavidcs mem_len = GET_FIELD(mem->dword1, DBG_DUMP_MEM_LENGTH); 3516316485Sdavidcs mem_wide_bus = GET_FIELD(mem->dword1, DBG_DUMP_MEM_WIDE_BUS); 3517316485Sdavidcs 3518316485Sdavidcs /* Update memory length for CCFC/TCFC memories 3519316485Sdavidcs * according to number of LCIDs/LTIDs. 3520316485Sdavidcs */ 3521316485Sdavidcs if (mem_group_id == MEM_GROUP_CONN_CFC_MEM) { 3522316485Sdavidcs if (mem_len % MAX_LCIDS) { 3523316485Sdavidcs DP_NOTICE(p_hwfn, true, "Invalid CCFC connection memory size\n"); 3524316485Sdavidcs return 0; 3525316485Sdavidcs } 3526316485Sdavidcs 3527316485Sdavidcs mem_len = ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NUM_LCIDS) * (mem_len / MAX_LCIDS); 3528316485Sdavidcs } 3529316485Sdavidcs else if (mem_group_id == MEM_GROUP_TASK_CFC_MEM) { 3530316485Sdavidcs if (mem_len % MAX_LTIDS) { 3531316485Sdavidcs DP_NOTICE(p_hwfn, true, "Invalid TCFC task memory size\n"); 3532316485Sdavidcs return 0; 3533316485Sdavidcs } 3534316485Sdavidcs 3535316485Sdavidcs mem_len = ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NUM_LTIDS) * (mem_len / MAX_LTIDS); 3536316485Sdavidcs } 3537316485Sdavidcs 3538316485Sdavidcs /* If memory is associated with Storm, udpate Storm 3539316485Sdavidcs * details. 3540316485Sdavidcs */ 3541316485Sdavidcs if (s_block_defs[cond_hdr->block_id]->associated_to_storm) { 3542316485Sdavidcs is_storm = true; 3543316485Sdavidcs storm_letter = s_storm_defs[s_block_defs[cond_hdr->block_id]->storm_id].letter; 3544316485Sdavidcs } 3545316485Sdavidcs 3546316485Sdavidcs /* Dump memory */ 3547316485Sdavidcs offset += ecore_grc_dump_mem(p_hwfn, p_ptt, dump_buf + offset, dump, OSAL_NULL, mem_addr, mem_len, mem_wide_bus, 3548337519Sdavidcs 0, false, s_mem_group_names[mem_group_id], is_storm, storm_letter); 3549316485Sdavidcs } 3550316485Sdavidcs } 3551316485Sdavidcs 3552316485Sdavidcs return offset; 3553316485Sdavidcs} 3554316485Sdavidcs 3555316485Sdavidcs/* Dumps GRC memories according to the input array dump_mem. 3556316485Sdavidcs * Returns the dumped size in dwords. 3557316485Sdavidcs */ 3558316485Sdavidcsstatic u32 ecore_grc_dump_memories(struct ecore_hwfn *p_hwfn, 3559316485Sdavidcs struct ecore_ptt *p_ptt, 3560316485Sdavidcs u32 *dump_buf, 3561316485Sdavidcs bool dump) 3562316485Sdavidcs{ 3563316485Sdavidcs u32 offset = 0, input_offset = 0; 3564316485Sdavidcs 3565316485Sdavidcs while (input_offset < s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].size_in_dwords) { 3566316485Sdavidcs const struct dbg_dump_split_hdr *split_hdr; 3567316485Sdavidcs struct dbg_array curr_input_mems_arr; 3568316485Sdavidcs u32 split_data_size; 3569316485Sdavidcs u8 split_type_id; 3570316485Sdavidcs 3571337519Sdavidcs split_hdr = (const struct dbg_dump_split_hdr *)&s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr[input_offset++]; 3572316485Sdavidcs split_type_id = GET_FIELD(split_hdr->hdr, DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID); 3573316485Sdavidcs split_data_size = GET_FIELD(split_hdr->hdr, DBG_DUMP_SPLIT_HDR_DATA_SIZE); 3574316485Sdavidcs curr_input_mems_arr.ptr = &s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr[input_offset]; 3575316485Sdavidcs curr_input_mems_arr.size_in_dwords = split_data_size; 3576316485Sdavidcs 3577316485Sdavidcs switch (split_type_id) { 3578316485Sdavidcs case SPLIT_TYPE_NONE: 3579316485Sdavidcs offset += ecore_grc_dump_mem_entries(p_hwfn, p_ptt, curr_input_mems_arr, dump_buf + offset, dump); 3580316485Sdavidcs break; 3581316485Sdavidcs 3582316485Sdavidcs default: 3583316485Sdavidcs DP_NOTICE(p_hwfn, true, "Dumping split memories is currently not supported\n"); 3584316485Sdavidcs break; 3585316485Sdavidcs } 3586316485Sdavidcs 3587316485Sdavidcs input_offset += split_data_size; 3588316485Sdavidcs } 3589316485Sdavidcs 3590316485Sdavidcs return offset; 3591316485Sdavidcs} 3592316485Sdavidcs 3593316485Sdavidcs/* Dumps GRC context data for the specified Storm. 3594316485Sdavidcs * Returns the dumped size in dwords. 3595316485Sdavidcs * The lid_size argument is specified in quad-regs. 3596316485Sdavidcs */ 3597316485Sdavidcsstatic u32 ecore_grc_dump_ctx_data(struct ecore_hwfn *p_hwfn, 3598316485Sdavidcs struct ecore_ptt *p_ptt, 3599316485Sdavidcs u32 *dump_buf, 3600316485Sdavidcs bool dump, 3601316485Sdavidcs const char *name, 3602316485Sdavidcs u32 num_lids, 3603316485Sdavidcs u32 lid_size, 3604316485Sdavidcs u32 rd_reg_addr, 3605316485Sdavidcs u8 storm_id) 3606316485Sdavidcs{ 3607316485Sdavidcs struct storm_defs *storm = &s_storm_defs[storm_id]; 3608316485Sdavidcs u32 i, lid, total_size, offset = 0; 3609316485Sdavidcs 3610316485Sdavidcs if (!lid_size) 3611316485Sdavidcs return 0; 3612316485Sdavidcs 3613316485Sdavidcs lid_size *= BYTES_IN_DWORD; 3614316485Sdavidcs total_size = num_lids * lid_size; 3615316485Sdavidcs 3616316485Sdavidcs offset += ecore_grc_dump_mem_hdr(p_hwfn, dump_buf + offset, dump, name, 0, total_size, lid_size * 32, false, name, true, storm->letter); 3617316485Sdavidcs 3618316485Sdavidcs if (!dump) 3619316485Sdavidcs return offset + total_size; 3620316485Sdavidcs 3621316485Sdavidcs /* Dump context data */ 3622316485Sdavidcs for (lid = 0; lid < num_lids; lid++) { 3623316485Sdavidcs for (i = 0; i < lid_size; i++, offset++) { 3624316485Sdavidcs ecore_wr(p_hwfn, p_ptt, storm->cm_ctx_wr_addr, (i << 9) | lid); 3625316485Sdavidcs *(dump_buf + offset) = ecore_rd(p_hwfn, p_ptt, rd_reg_addr); 3626316485Sdavidcs } 3627316485Sdavidcs } 3628316485Sdavidcs 3629316485Sdavidcs return offset; 3630316485Sdavidcs} 3631316485Sdavidcs 3632316485Sdavidcs/* Dumps GRC contexts. Returns the dumped size in dwords. */ 3633316485Sdavidcsstatic u32 ecore_grc_dump_ctx(struct ecore_hwfn *p_hwfn, 3634316485Sdavidcs struct ecore_ptt *p_ptt, 3635316485Sdavidcs u32 *dump_buf, 3636316485Sdavidcs bool dump) 3637316485Sdavidcs{ 3638316485Sdavidcs u32 offset = 0; 3639316485Sdavidcs u8 storm_id; 3640316485Sdavidcs 3641316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 3642316485Sdavidcs struct storm_defs *storm = &s_storm_defs[storm_id]; 3643316485Sdavidcs 3644316485Sdavidcs if (!ecore_grc_is_storm_included(p_hwfn, (enum dbg_storms)storm_id)) 3645316485Sdavidcs continue; 3646316485Sdavidcs 3647316485Sdavidcs /* Dump Conn AG context size */ 3648316485Sdavidcs offset += ecore_grc_dump_ctx_data(p_hwfn, p_ptt, dump_buf + offset, dump, "CONN_AG_CTX", ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NUM_LCIDS), 3649316485Sdavidcs storm->cm_conn_ag_ctx_lid_size, storm->cm_conn_ag_ctx_rd_addr, storm_id); 3650316485Sdavidcs 3651316485Sdavidcs /* Dump Conn ST context size */ 3652316485Sdavidcs offset += ecore_grc_dump_ctx_data(p_hwfn, p_ptt, dump_buf + offset, dump, "CONN_ST_CTX", ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NUM_LCIDS), 3653316485Sdavidcs storm->cm_conn_st_ctx_lid_size, storm->cm_conn_st_ctx_rd_addr, storm_id); 3654316485Sdavidcs 3655316485Sdavidcs /* Dump Task AG context size */ 3656316485Sdavidcs offset += ecore_grc_dump_ctx_data(p_hwfn, p_ptt, dump_buf + offset, dump, "TASK_AG_CTX", ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NUM_LTIDS), 3657316485Sdavidcs storm->cm_task_ag_ctx_lid_size, storm->cm_task_ag_ctx_rd_addr, storm_id); 3658316485Sdavidcs 3659316485Sdavidcs /* Dump Task ST context size */ 3660316485Sdavidcs offset += ecore_grc_dump_ctx_data(p_hwfn, p_ptt, dump_buf + offset, dump, "TASK_ST_CTX", ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NUM_LTIDS), 3661316485Sdavidcs storm->cm_task_st_ctx_lid_size, storm->cm_task_st_ctx_rd_addr, storm_id); 3662316485Sdavidcs } 3663316485Sdavidcs 3664316485Sdavidcs return offset; 3665316485Sdavidcs} 3666316485Sdavidcs 3667316485Sdavidcs/* Dumps GRC IORs data. Returns the dumped size in dwords. */ 3668316485Sdavidcsstatic u32 ecore_grc_dump_iors(struct ecore_hwfn *p_hwfn, 3669316485Sdavidcs struct ecore_ptt *p_ptt, 3670316485Sdavidcs u32 *dump_buf, 3671316485Sdavidcs bool dump) 3672316485Sdavidcs{ 3673316485Sdavidcs char buf[10] = "IOR_SET_?"; 3674316485Sdavidcs u32 addr, offset = 0; 3675316485Sdavidcs u8 storm_id, set_id; 3676316485Sdavidcs 3677316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 3678316485Sdavidcs struct storm_defs *storm = &s_storm_defs[storm_id]; 3679316485Sdavidcs 3680316485Sdavidcs if (!ecore_grc_is_storm_included(p_hwfn, (enum dbg_storms)storm_id)) 3681316485Sdavidcs continue; 3682316485Sdavidcs 3683316485Sdavidcs for (set_id = 0; set_id < NUM_IOR_SETS; set_id++) { 3684316485Sdavidcs addr = BYTES_TO_DWORDS(storm->sem_fast_mem_addr + SEM_FAST_REG_STORM_REG_FILE) + IOR_SET_OFFSET(set_id); 3685316485Sdavidcs buf[OSAL_STRLEN(buf) - 1] = '0' + set_id; 3686316485Sdavidcs offset += ecore_grc_dump_mem(p_hwfn, p_ptt, dump_buf + offset, dump, buf, addr, IORS_PER_SET, false, 32, false, "ior", true, storm->letter); 3687316485Sdavidcs } 3688316485Sdavidcs } 3689316485Sdavidcs 3690316485Sdavidcs return offset; 3691316485Sdavidcs} 3692316485Sdavidcs 3693316485Sdavidcs/* Dump VFC CAM. Returns the dumped size in dwords. */ 3694316485Sdavidcsstatic u32 ecore_grc_dump_vfc_cam(struct ecore_hwfn *p_hwfn, 3695316485Sdavidcs struct ecore_ptt *p_ptt, 3696316485Sdavidcs u32 *dump_buf, 3697316485Sdavidcs bool dump, 3698316485Sdavidcs u8 storm_id) 3699316485Sdavidcs{ 3700316485Sdavidcs u32 total_size = VFC_CAM_NUM_ROWS * VFC_CAM_RESP_DWORDS; 3701316485Sdavidcs struct storm_defs *storm = &s_storm_defs[storm_id]; 3702316485Sdavidcs u32 cam_addr[VFC_CAM_ADDR_DWORDS] = { 0 }; 3703316485Sdavidcs u32 cam_cmd[VFC_CAM_CMD_DWORDS] = { 0 }; 3704316485Sdavidcs u32 row, i, offset = 0; 3705316485Sdavidcs 3706316485Sdavidcs offset += ecore_grc_dump_mem_hdr(p_hwfn, dump_buf + offset, dump, "vfc_cam", 0, total_size, 256, false, "vfc_cam", true, storm->letter); 3707316485Sdavidcs 3708316485Sdavidcs if (!dump) 3709316485Sdavidcs return offset + total_size; 3710316485Sdavidcs 3711316485Sdavidcs /* Prepare CAM address */ 3712316485Sdavidcs SET_VAR_FIELD(cam_addr, VFC_CAM_ADDR, OP, VFC_OPCODE_CAM_RD); 3713316485Sdavidcs 3714316485Sdavidcs for (row = 0; row < VFC_CAM_NUM_ROWS; row++, offset += VFC_CAM_RESP_DWORDS) { 3715316485Sdavidcs 3716316485Sdavidcs /* Write VFC CAM command */ 3717316485Sdavidcs SET_VAR_FIELD(cam_cmd, VFC_CAM_CMD, ROW, row); 3718316485Sdavidcs ARR_REG_WR(p_hwfn, p_ptt, storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_WR, cam_cmd, VFC_CAM_CMD_DWORDS); 3719316485Sdavidcs 3720316485Sdavidcs /* Write VFC CAM address */ 3721316485Sdavidcs ARR_REG_WR(p_hwfn, p_ptt, storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_ADDR, cam_addr, VFC_CAM_ADDR_DWORDS); 3722316485Sdavidcs 3723316485Sdavidcs /* Read VFC CAM read response */ 3724316485Sdavidcs ARR_REG_RD(p_hwfn, p_ptt, storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_RD, dump_buf + offset, VFC_CAM_RESP_DWORDS); 3725316485Sdavidcs } 3726316485Sdavidcs 3727316485Sdavidcs return offset; 3728316485Sdavidcs} 3729316485Sdavidcs 3730316485Sdavidcs/* Dump VFC RAM. Returns the dumped size in dwords. */ 3731316485Sdavidcsstatic u32 ecore_grc_dump_vfc_ram(struct ecore_hwfn *p_hwfn, 3732316485Sdavidcs struct ecore_ptt *p_ptt, 3733316485Sdavidcs u32 *dump_buf, 3734316485Sdavidcs bool dump, 3735316485Sdavidcs u8 storm_id, 3736316485Sdavidcs struct vfc_ram_defs *ram_defs) 3737316485Sdavidcs{ 3738316485Sdavidcs u32 total_size = ram_defs->num_rows * VFC_RAM_RESP_DWORDS; 3739316485Sdavidcs struct storm_defs *storm = &s_storm_defs[storm_id]; 3740316485Sdavidcs u32 ram_addr[VFC_RAM_ADDR_DWORDS] = { 0 }; 3741316485Sdavidcs u32 ram_cmd[VFC_RAM_CMD_DWORDS] = { 0 }; 3742316485Sdavidcs u32 row, i, offset = 0; 3743316485Sdavidcs 3744316485Sdavidcs offset += ecore_grc_dump_mem_hdr(p_hwfn, dump_buf + offset, dump, ram_defs->mem_name, 0, total_size, 256, false, ram_defs->type_name, true, storm->letter); 3745316485Sdavidcs 3746316485Sdavidcs /* Prepare RAM address */ 3747316485Sdavidcs SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, OP, VFC_OPCODE_RAM_RD); 3748316485Sdavidcs 3749316485Sdavidcs if (!dump) 3750316485Sdavidcs return offset + total_size; 3751316485Sdavidcs 3752316485Sdavidcs for (row = ram_defs->base_row; row < ram_defs->base_row + ram_defs->num_rows; row++, offset += VFC_RAM_RESP_DWORDS) { 3753316485Sdavidcs 3754316485Sdavidcs /* Write VFC RAM command */ 3755316485Sdavidcs ARR_REG_WR(p_hwfn, p_ptt, storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_WR, ram_cmd, VFC_RAM_CMD_DWORDS); 3756316485Sdavidcs 3757316485Sdavidcs /* Write VFC RAM address */ 3758316485Sdavidcs SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, ROW, row); 3759316485Sdavidcs ARR_REG_WR(p_hwfn, p_ptt, storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_ADDR, ram_addr, VFC_RAM_ADDR_DWORDS); 3760316485Sdavidcs 3761316485Sdavidcs /* Read VFC RAM read response */ 3762316485Sdavidcs ARR_REG_RD(p_hwfn, p_ptt, storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_RD, dump_buf + offset, VFC_RAM_RESP_DWORDS); 3763316485Sdavidcs } 3764316485Sdavidcs 3765316485Sdavidcs return offset; 3766316485Sdavidcs} 3767316485Sdavidcs 3768316485Sdavidcs/* Dumps GRC VFC data. Returns the dumped size in dwords. */ 3769316485Sdavidcsstatic u32 ecore_grc_dump_vfc(struct ecore_hwfn *p_hwfn, 3770316485Sdavidcs struct ecore_ptt *p_ptt, 3771316485Sdavidcs u32 *dump_buf, 3772316485Sdavidcs bool dump) 3773316485Sdavidcs{ 3774316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3775316485Sdavidcs u8 storm_id, i; 3776316485Sdavidcs u32 offset = 0; 3777337519Sdavidcs 3778316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 3779316485Sdavidcs if (!ecore_grc_is_storm_included(p_hwfn, (enum dbg_storms)storm_id) || 3780316485Sdavidcs !s_storm_defs[storm_id].has_vfc || 3781316485Sdavidcs (storm_id == DBG_PSTORM_ID && dev_data->platform_id != PLATFORM_ASIC)) 3782316485Sdavidcs continue; 3783316485Sdavidcs 3784316485Sdavidcs /* Read CAM */ 3785316485Sdavidcs offset += ecore_grc_dump_vfc_cam(p_hwfn, p_ptt, dump_buf + offset, dump, storm_id); 3786316485Sdavidcs 3787316485Sdavidcs /* Read RAM */ 3788316485Sdavidcs for (i = 0; i < NUM_VFC_RAM_TYPES; i++) 3789316485Sdavidcs offset += ecore_grc_dump_vfc_ram(p_hwfn, p_ptt, dump_buf + offset, dump, storm_id, &s_vfc_ram_defs[i]); 3790316485Sdavidcs } 3791316485Sdavidcs 3792316485Sdavidcs return offset; 3793316485Sdavidcs} 3794316485Sdavidcs 3795316485Sdavidcs/* Dumps GRC RSS data. Returns the dumped size in dwords. */ 3796316485Sdavidcsstatic u32 ecore_grc_dump_rss(struct ecore_hwfn *p_hwfn, 3797316485Sdavidcs struct ecore_ptt *p_ptt, 3798316485Sdavidcs u32 *dump_buf, 3799316485Sdavidcs bool dump) 3800316485Sdavidcs{ 3801316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3802316485Sdavidcs u32 offset = 0; 3803316485Sdavidcs u8 rss_mem_id; 3804316485Sdavidcs 3805316485Sdavidcs for (rss_mem_id = 0; rss_mem_id < NUM_RSS_MEM_TYPES; rss_mem_id++) { 3806320162Sdavidcs u32 rss_addr, num_entries, total_dwords; 3807316485Sdavidcs struct rss_mem_defs *rss_defs; 3808316485Sdavidcs bool packed; 3809316485Sdavidcs 3810316485Sdavidcs rss_defs = &s_rss_mem_defs[rss_mem_id]; 3811316485Sdavidcs rss_addr = rss_defs->addr; 3812316485Sdavidcs num_entries = rss_defs->num_entries[dev_data->chip_id]; 3813320162Sdavidcs total_dwords = (num_entries * rss_defs->entry_width) / 32; 3814320162Sdavidcs packed = (rss_defs->entry_width == 16); 3815316485Sdavidcs 3816316485Sdavidcs offset += ecore_grc_dump_mem_hdr(p_hwfn, dump_buf + offset, dump, rss_defs->mem_name, 0, total_dwords, 3817320162Sdavidcs rss_defs->entry_width, packed, rss_defs->type_name, false, 0); 3818316485Sdavidcs 3819316485Sdavidcs /* Dump RSS data */ 3820316485Sdavidcs if (!dump) { 3821316485Sdavidcs offset += total_dwords; 3822316485Sdavidcs continue; 3823316485Sdavidcs } 3824316485Sdavidcs 3825320162Sdavidcs while (total_dwords) { 3826320162Sdavidcs u32 num_dwords_to_read = OSAL_MIN_T(u32, RSS_REG_RSS_RAM_DATA_SIZE, total_dwords); 3827316485Sdavidcs ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_ADDR, rss_addr); 3828320162Sdavidcs offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, dump, BYTES_TO_DWORDS(RSS_REG_RSS_RAM_DATA), num_dwords_to_read, false); 3829320162Sdavidcs total_dwords -= num_dwords_to_read; 3830320162Sdavidcs rss_addr++; 3831316485Sdavidcs } 3832316485Sdavidcs } 3833316485Sdavidcs 3834316485Sdavidcs return offset; 3835316485Sdavidcs} 3836316485Sdavidcs 3837316485Sdavidcs/* Dumps GRC Big RAM. Returns the dumped size in dwords. */ 3838316485Sdavidcsstatic u32 ecore_grc_dump_big_ram(struct ecore_hwfn *p_hwfn, 3839316485Sdavidcs struct ecore_ptt *p_ptt, 3840316485Sdavidcs u32 *dump_buf, 3841316485Sdavidcs bool dump, 3842316485Sdavidcs u8 big_ram_id) 3843316485Sdavidcs{ 3844316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3845337519Sdavidcs u32 block_size, ram_size, offset = 0, reg_val, i; 3846316485Sdavidcs char mem_name[12] = "???_BIG_RAM"; 3847316485Sdavidcs char type_name[8] = "???_RAM"; 3848316485Sdavidcs struct big_ram_defs *big_ram; 3849316485Sdavidcs 3850316485Sdavidcs big_ram = &s_big_ram_defs[big_ram_id]; 3851337519Sdavidcs ram_size = big_ram->ram_size[dev_data->chip_id]; 3852316485Sdavidcs 3853337519Sdavidcs reg_val = ecore_rd(p_hwfn, p_ptt, big_ram->is_256b_reg_addr); 3854337519Sdavidcs block_size = reg_val & (1 << big_ram->is_256b_bit_offset[dev_data->chip_id]) ? 256 : 128; 3855337519Sdavidcs 3856316485Sdavidcs OSAL_STRNCPY(type_name, big_ram->instance_name, OSAL_STRLEN(big_ram->instance_name)); 3857316485Sdavidcs OSAL_STRNCPY(mem_name, big_ram->instance_name, OSAL_STRLEN(big_ram->instance_name)); 3858316485Sdavidcs 3859316485Sdavidcs /* Dump memory header */ 3860337519Sdavidcs offset += ecore_grc_dump_mem_hdr(p_hwfn, dump_buf + offset, dump, mem_name, 0, ram_size, block_size * 8, false, type_name, false, 0); 3861316485Sdavidcs 3862316485Sdavidcs /* Read and dump Big RAM data */ 3863316485Sdavidcs if (!dump) 3864316485Sdavidcs return offset + ram_size; 3865316485Sdavidcs 3866316485Sdavidcs /* Dump Big RAM */ 3867337519Sdavidcs for (i = 0; i < DIV_ROUND_UP(ram_size, BRB_REG_BIG_RAM_DATA_SIZE); i++) { 3868316485Sdavidcs ecore_wr(p_hwfn, p_ptt, big_ram->addr_reg_addr, i); 3869337519Sdavidcs offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, dump, BYTES_TO_DWORDS(big_ram->data_reg_addr), BRB_REG_BIG_RAM_DATA_SIZE, false); 3870316485Sdavidcs } 3871316485Sdavidcs 3872316485Sdavidcs return offset; 3873316485Sdavidcs} 3874316485Sdavidcs 3875316485Sdavidcsstatic u32 ecore_grc_dump_mcp(struct ecore_hwfn *p_hwfn, 3876316485Sdavidcs struct ecore_ptt *p_ptt, 3877316485Sdavidcs u32 *dump_buf, 3878316485Sdavidcs bool dump) 3879316485Sdavidcs{ 3880320162Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3881316485Sdavidcs bool block_enable[MAX_BLOCK_ID] = { 0 }; 3882316485Sdavidcs bool halted = false; 3883316485Sdavidcs u32 offset = 0; 3884316485Sdavidcs 3885316485Sdavidcs /* Halt MCP */ 3886320162Sdavidcs if (dump && dev_data->platform_id == PLATFORM_ASIC && !ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP)) { 3887316485Sdavidcs halted = !ecore_mcp_halt(p_hwfn, p_ptt); 3888316485Sdavidcs if (!halted) 3889316485Sdavidcs DP_NOTICE(p_hwfn, false, "MCP halt failed!\n"); 3890316485Sdavidcs } 3891316485Sdavidcs 3892316485Sdavidcs /* Dump MCP scratchpad */ 3893337519Sdavidcs offset += ecore_grc_dump_mem(p_hwfn, p_ptt, dump_buf + offset, dump, OSAL_NULL, BYTES_TO_DWORDS(MCP_REG_SCRATCH), 3894337519Sdavidcs ECORE_IS_E5(p_hwfn->p_dev) ? MCP_REG_SCRATCH_SIZE_E5 : MCP_REG_SCRATCH_SIZE_BB_K2, false, 0, false, "MCP", false, 0); 3895316485Sdavidcs 3896316485Sdavidcs /* Dump MCP cpu_reg_file */ 3897337519Sdavidcs offset += ecore_grc_dump_mem(p_hwfn, p_ptt, dump_buf + offset, dump, OSAL_NULL, BYTES_TO_DWORDS(MCP_REG_CPU_REG_FILE), 3898337519Sdavidcs MCP_REG_CPU_REG_FILE_SIZE, false, 0, false, "MCP", false, 0); 3899316485Sdavidcs 3900316485Sdavidcs /* Dump MCP registers */ 3901316485Sdavidcs block_enable[BLOCK_MCP] = true; 3902316485Sdavidcs offset += ecore_grc_dump_registers(p_hwfn, p_ptt, dump_buf + offset, dump, block_enable, "block", "MCP"); 3903316485Sdavidcs 3904316485Sdavidcs /* Dump required non-MCP registers */ 3905316485Sdavidcs offset += ecore_grc_dump_regs_hdr(dump_buf + offset, dump, 1, "eng", -1, "block", "MCP"); 3906316485Sdavidcs offset += ecore_grc_dump_reg_entry(p_hwfn, p_ptt, dump_buf + offset, dump, BYTES_TO_DWORDS(MISC_REG_SHARED_MEM_ADDR), 1, false); 3907316485Sdavidcs 3908316485Sdavidcs /* Release MCP */ 3909316485Sdavidcs if (halted && ecore_mcp_resume(p_hwfn, p_ptt)) 3910316485Sdavidcs DP_NOTICE(p_hwfn, false, "Failed to resume MCP after halt!\n"); 3911316485Sdavidcs 3912316485Sdavidcs return offset; 3913316485Sdavidcs} 3914316485Sdavidcs 3915316485Sdavidcs/* Dumps the tbus indirect memory for all PHYs. */ 3916316485Sdavidcsstatic u32 ecore_grc_dump_phy(struct ecore_hwfn *p_hwfn, 3917316485Sdavidcs struct ecore_ptt *p_ptt, 3918316485Sdavidcs u32 *dump_buf, 3919316485Sdavidcs bool dump) 3920316485Sdavidcs{ 3921316485Sdavidcs u32 offset = 0, tbus_lo_offset, tbus_hi_offset; 3922316485Sdavidcs char mem_name[32]; 3923316485Sdavidcs u8 phy_id; 3924316485Sdavidcs 3925316485Sdavidcs for (phy_id = 0; phy_id < OSAL_ARRAY_SIZE(s_phy_defs); phy_id++) { 3926316485Sdavidcs u32 addr_lo_addr, addr_hi_addr, data_lo_addr, data_hi_addr; 3927316485Sdavidcs struct phy_defs *phy_defs; 3928316485Sdavidcs u8 *bytes_buf; 3929316485Sdavidcs 3930316485Sdavidcs phy_defs = &s_phy_defs[phy_id]; 3931316485Sdavidcs addr_lo_addr = phy_defs->base_addr + phy_defs->tbus_addr_lo_addr; 3932316485Sdavidcs addr_hi_addr = phy_defs->base_addr + phy_defs->tbus_addr_hi_addr; 3933316485Sdavidcs data_lo_addr = phy_defs->base_addr + phy_defs->tbus_data_lo_addr; 3934316485Sdavidcs data_hi_addr = phy_defs->base_addr + phy_defs->tbus_data_hi_addr; 3935316485Sdavidcs 3936316485Sdavidcs if (OSAL_SNPRINTF(mem_name, sizeof(mem_name), "tbus_%s", phy_defs->phy_name) < 0) 3937316485Sdavidcs DP_NOTICE(p_hwfn, true, "Unexpected debug error: invalid PHY memory name\n"); 3938316485Sdavidcs 3939316485Sdavidcs offset += ecore_grc_dump_mem_hdr(p_hwfn, dump_buf + offset, dump, mem_name, 0, PHY_DUMP_SIZE_DWORDS, 16, true, mem_name, false, 0); 3940316485Sdavidcs 3941316485Sdavidcs if (!dump) { 3942316485Sdavidcs offset += PHY_DUMP_SIZE_DWORDS; 3943316485Sdavidcs continue; 3944316485Sdavidcs } 3945316485Sdavidcs 3946337519Sdavidcs bytes_buf = (u8 *)(dump_buf + offset); 3947316485Sdavidcs for (tbus_hi_offset = 0; tbus_hi_offset < (NUM_PHY_TBUS_ADDRESSES >> 8); tbus_hi_offset++) { 3948316485Sdavidcs ecore_wr(p_hwfn, p_ptt, addr_hi_addr, tbus_hi_offset); 3949316485Sdavidcs for (tbus_lo_offset = 0; tbus_lo_offset < 256; tbus_lo_offset++) { 3950316485Sdavidcs ecore_wr(p_hwfn, p_ptt, addr_lo_addr, tbus_lo_offset); 3951316485Sdavidcs *(bytes_buf++) = (u8)ecore_rd(p_hwfn, p_ptt, data_lo_addr); 3952316485Sdavidcs *(bytes_buf++) = (u8)ecore_rd(p_hwfn, p_ptt, data_hi_addr); 3953316485Sdavidcs } 3954316485Sdavidcs } 3955316485Sdavidcs 3956316485Sdavidcs offset += PHY_DUMP_SIZE_DWORDS; 3957316485Sdavidcs } 3958316485Sdavidcs 3959316485Sdavidcs return offset; 3960316485Sdavidcs} 3961316485Sdavidcs 3962316485Sdavidcsstatic void ecore_config_dbg_line(struct ecore_hwfn *p_hwfn, 3963316485Sdavidcs struct ecore_ptt *p_ptt, 3964316485Sdavidcs enum block_id block_id, 3965316485Sdavidcs u8 line_id, 3966316485Sdavidcs u8 enable_mask, 3967316485Sdavidcs u8 right_shift, 3968316485Sdavidcs u8 force_valid_mask, 3969316485Sdavidcs u8 force_frame_mask) 3970316485Sdavidcs{ 3971316485Sdavidcs struct block_defs *block = s_block_defs[block_id]; 3972316485Sdavidcs 3973316485Sdavidcs ecore_wr(p_hwfn, p_ptt, block->dbg_select_addr, line_id); 3974316485Sdavidcs ecore_wr(p_hwfn, p_ptt, block->dbg_enable_addr, enable_mask); 3975316485Sdavidcs ecore_wr(p_hwfn, p_ptt, block->dbg_shift_addr, right_shift); 3976316485Sdavidcs ecore_wr(p_hwfn, p_ptt, block->dbg_force_valid_addr, force_valid_mask); 3977316485Sdavidcs ecore_wr(p_hwfn, p_ptt, block->dbg_force_frame_addr, force_frame_mask); 3978316485Sdavidcs} 3979316485Sdavidcs 3980316485Sdavidcs/* Dumps Static Debug data. Returns the dumped size in dwords. */ 3981316485Sdavidcsstatic u32 ecore_grc_dump_static_debug(struct ecore_hwfn *p_hwfn, 3982316485Sdavidcs struct ecore_ptt *p_ptt, 3983316485Sdavidcs u32 *dump_buf, 3984316485Sdavidcs bool dump) 3985316485Sdavidcs{ 3986316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3987316485Sdavidcs u32 block_id, line_id, offset = 0; 3988316485Sdavidcs 3989337519Sdavidcs /* don't dump static debug if a debug bus recording is in progress */ 3990337519Sdavidcs if (dump && ecore_rd(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON)) 3991316485Sdavidcs return 0; 3992316485Sdavidcs 3993316485Sdavidcs if (dump) { 3994316485Sdavidcs /* Disable all blocks debug output */ 3995316485Sdavidcs for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 3996316485Sdavidcs struct block_defs *block = s_block_defs[block_id]; 3997316485Sdavidcs 3998320162Sdavidcs if (block->dbg_client_id[dev_data->chip_id] != MAX_DBG_BUS_CLIENTS) 3999316485Sdavidcs ecore_wr(p_hwfn, p_ptt, block->dbg_enable_addr, 0); 4000316485Sdavidcs } 4001316485Sdavidcs 4002316485Sdavidcs ecore_bus_reset_dbg_block(p_hwfn, p_ptt); 4003316485Sdavidcs ecore_bus_set_framing_mode(p_hwfn, p_ptt, DBG_BUS_FRAME_MODE_8HW_0ST); 4004316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_DEBUG_TARGET, DBG_BUS_TARGET_ID_INT_BUF); 4005316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_FULL_MODE, 1); 4006316485Sdavidcs ecore_bus_enable_dbg_block(p_hwfn, p_ptt, true); 4007316485Sdavidcs } 4008316485Sdavidcs 4009316485Sdavidcs /* Dump all static debug lines for each relevant block */ 4010316485Sdavidcs for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 4011316485Sdavidcs struct block_defs *block = s_block_defs[block_id]; 4012316485Sdavidcs struct dbg_bus_block *block_desc; 4013316485Sdavidcs u32 block_dwords; 4014316485Sdavidcs 4015320162Sdavidcs if (block->dbg_client_id[dev_data->chip_id] == MAX_DBG_BUS_CLIENTS) 4016316485Sdavidcs continue; 4017316485Sdavidcs 4018316485Sdavidcs block_desc = get_dbg_bus_block_desc(p_hwfn, (enum block_id)block_id); 4019316485Sdavidcs block_dwords = NUM_DBG_LINES(block_desc) * STATIC_DEBUG_LINE_DWORDS; 4020316485Sdavidcs 4021316485Sdavidcs /* Dump static section params */ 4022316485Sdavidcs offset += ecore_grc_dump_mem_hdr(p_hwfn, dump_buf + offset, dump, block->name, 0, block_dwords, 32, false, "STATIC", false, 0); 4023316485Sdavidcs 4024316485Sdavidcs if (!dump) { 4025316485Sdavidcs offset += block_dwords; 4026316485Sdavidcs continue; 4027316485Sdavidcs } 4028316485Sdavidcs 4029316485Sdavidcs /* If all lines are invalid - dump zeros */ 4030316485Sdavidcs if (dev_data->block_in_reset[block_id]) { 4031316485Sdavidcs OSAL_MEMSET(dump_buf + offset, 0, DWORDS_TO_BYTES(block_dwords)); 4032316485Sdavidcs offset += block_dwords; 4033316485Sdavidcs continue; 4034316485Sdavidcs } 4035316485Sdavidcs 4036316485Sdavidcs /* Enable block's client */ 4037316485Sdavidcs ecore_bus_enable_clients(p_hwfn, p_ptt, 1 << block->dbg_client_id[dev_data->chip_id]); 4038316485Sdavidcs for (line_id = 0; line_id < (u32)NUM_DBG_LINES(block_desc); line_id++) { 4039316485Sdavidcs 4040316485Sdavidcs /* Configure debug line ID */ 4041316485Sdavidcs ecore_config_dbg_line(p_hwfn, p_ptt, (enum block_id)block_id, (u8)line_id, 0xf, 0, 0, 0); 4042316485Sdavidcs 4043316485Sdavidcs /* Read debug line info */ 4044316485Sdavidcs offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, dump, BYTES_TO_DWORDS(DBG_REG_CALENDAR_OUT_DATA), STATIC_DEBUG_LINE_DWORDS, true); 4045316485Sdavidcs } 4046316485Sdavidcs 4047316485Sdavidcs /* Disable block's client and debug output */ 4048316485Sdavidcs ecore_bus_enable_clients(p_hwfn, p_ptt, 0); 4049316485Sdavidcs ecore_wr(p_hwfn, p_ptt, block->dbg_enable_addr, 0); 4050316485Sdavidcs } 4051316485Sdavidcs 4052316485Sdavidcs if (dump) { 4053316485Sdavidcs ecore_bus_enable_dbg_block(p_hwfn, p_ptt, false); 4054316485Sdavidcs ecore_bus_enable_clients(p_hwfn, p_ptt, 0); 4055316485Sdavidcs } 4056316485Sdavidcs 4057316485Sdavidcs return offset; 4058316485Sdavidcs} 4059316485Sdavidcs 4060316485Sdavidcs/* Performs GRC Dump to the specified buffer. 4061316485Sdavidcs * Returns the dumped size in dwords. 4062316485Sdavidcs */ 4063316485Sdavidcsstatic enum dbg_status ecore_grc_dump(struct ecore_hwfn *p_hwfn, 4064316485Sdavidcs struct ecore_ptt *p_ptt, 4065316485Sdavidcs u32 *dump_buf, 4066316485Sdavidcs bool dump, 4067316485Sdavidcs u32 *num_dumped_dwords) 4068316485Sdavidcs{ 4069316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 4070320162Sdavidcs bool is_asic, parities_masked = false; 4071316485Sdavidcs u8 i, port_mode = 0; 4072316485Sdavidcs u32 offset = 0; 4073316485Sdavidcs 4074320162Sdavidcs is_asic = dev_data->platform_id == PLATFORM_ASIC; 4075316485Sdavidcs 4076316485Sdavidcs *num_dumped_dwords = 0; 4077316485Sdavidcs 4078316485Sdavidcs if (dump) { 4079316485Sdavidcs 4080316485Sdavidcs /* Find port mode */ 4081316485Sdavidcs switch (ecore_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE)) { 4082316485Sdavidcs case 0: port_mode = 1; break; 4083316485Sdavidcs case 1: port_mode = 2; break; 4084316485Sdavidcs case 2: port_mode = 4; break; 4085316485Sdavidcs } 4086316485Sdavidcs 4087316485Sdavidcs /* Update reset state */ 4088316485Sdavidcs ecore_update_blocks_reset_state(p_hwfn, p_ptt); 4089316485Sdavidcs } 4090316485Sdavidcs 4091316485Sdavidcs /* Dump global params */ 4092316485Sdavidcs offset += ecore_dump_common_global_params(p_hwfn, p_ptt, dump_buf + offset, dump, 4); 4093316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "dump-type", "grc-dump"); 4094316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "num-lcids", ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NUM_LCIDS)); 4095316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "num-ltids", ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NUM_LTIDS)); 4096316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "num-ports", port_mode); 4097316485Sdavidcs 4098316485Sdavidcs /* Dump reset registers (dumped before taking blocks out of reset ) */ 4099316485Sdavidcs if (ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS)) 4100316485Sdavidcs offset += ecore_grc_dump_reset_regs(p_hwfn, p_ptt, dump_buf + offset, dump); 4101316485Sdavidcs 4102316485Sdavidcs /* Take all blocks out of reset (using reset registers) */ 4103316485Sdavidcs if (dump) { 4104316485Sdavidcs ecore_grc_unreset_blocks(p_hwfn, p_ptt); 4105316485Sdavidcs ecore_update_blocks_reset_state(p_hwfn, p_ptt); 4106316485Sdavidcs } 4107316485Sdavidcs 4108316485Sdavidcs /* Disable all parities using MFW command */ 4109320162Sdavidcs if (dump && is_asic && !ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP)) { 4110337519Sdavidcs parities_masked = !ecore_mcp_mask_parities(p_hwfn, p_ptt, 1); 4111337519Sdavidcs if (!parities_masked) { 4112337519Sdavidcs DP_NOTICE(p_hwfn, false, "Failed to mask parities using MFW\n"); 4113337519Sdavidcs if (ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_PARITY_SAFE)) 4114337519Sdavidcs return DBG_STATUS_MCP_COULD_NOT_MASK_PRTY; 4115337519Sdavidcs } 4116316485Sdavidcs } 4117316485Sdavidcs 4118316485Sdavidcs /* Dump modified registers (dumped before modifying them) */ 4119316485Sdavidcs if (ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS)) 4120316485Sdavidcs offset += ecore_grc_dump_modified_regs(p_hwfn, p_ptt, dump_buf + offset, dump); 4121316485Sdavidcs 4122316485Sdavidcs /* Stall storms */ 4123316485Sdavidcs if (dump && (ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IOR) || ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC))) 4124316485Sdavidcs ecore_grc_stall_storms(p_hwfn, p_ptt, true); 4125316485Sdavidcs 4126316485Sdavidcs /* Dump all regs */ 4127316485Sdavidcs if (ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS)) { 4128316485Sdavidcs bool block_enable[MAX_BLOCK_ID]; 4129316485Sdavidcs 4130316485Sdavidcs /* Dump all blocks except MCP */ 4131316485Sdavidcs for (i = 0; i < MAX_BLOCK_ID; i++) 4132316485Sdavidcs block_enable[i] = true; 4133316485Sdavidcs block_enable[BLOCK_MCP] = false; 4134316485Sdavidcs offset += ecore_grc_dump_registers(p_hwfn, p_ptt, dump_buf + offset, dump, block_enable, OSAL_NULL, OSAL_NULL); 4135316485Sdavidcs 4136316485Sdavidcs /* Dump special registers */ 4137316485Sdavidcs offset += ecore_grc_dump_special_regs(p_hwfn, p_ptt, dump_buf + offset, dump); 4138316485Sdavidcs } 4139316485Sdavidcs 4140316485Sdavidcs /* Dump memories */ 4141316485Sdavidcs offset += ecore_grc_dump_memories(p_hwfn, p_ptt, dump_buf + offset, dump); 4142316485Sdavidcs 4143316485Sdavidcs /* Dump MCP */ 4144316485Sdavidcs if (ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MCP)) 4145316485Sdavidcs offset += ecore_grc_dump_mcp(p_hwfn, p_ptt, dump_buf + offset, dump); 4146316485Sdavidcs 4147316485Sdavidcs /* Dump context */ 4148316485Sdavidcs if (ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM_CTX)) 4149316485Sdavidcs offset += ecore_grc_dump_ctx(p_hwfn, p_ptt, dump_buf + offset, dump); 4150316485Sdavidcs 4151316485Sdavidcs /* Dump RSS memories */ 4152316485Sdavidcs if (ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_RSS)) 4153316485Sdavidcs offset += ecore_grc_dump_rss(p_hwfn, p_ptt, dump_buf + offset, dump); 4154316485Sdavidcs 4155316485Sdavidcs /* Dump Big RAM */ 4156316485Sdavidcs for (i = 0; i < NUM_BIG_RAM_TYPES; i++) 4157316485Sdavidcs if (ecore_grc_is_included(p_hwfn, s_big_ram_defs[i].grc_param)) 4158316485Sdavidcs offset += ecore_grc_dump_big_ram(p_hwfn, p_ptt, dump_buf + offset, dump, i); 4159316485Sdavidcs 4160316485Sdavidcs /* Dump IORs */ 4161316485Sdavidcs if (ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IOR)) 4162316485Sdavidcs offset += ecore_grc_dump_iors(p_hwfn, p_ptt, dump_buf + offset, dump); 4163316485Sdavidcs 4164316485Sdavidcs /* Dump VFC */ 4165316485Sdavidcs if (ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC)) 4166316485Sdavidcs offset += ecore_grc_dump_vfc(p_hwfn, p_ptt, dump_buf + offset, dump); 4167316485Sdavidcs 4168316485Sdavidcs /* Dump PHY tbus */ 4169316485Sdavidcs if (ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PHY) && dev_data->chip_id == CHIP_K2 && dev_data->platform_id == PLATFORM_ASIC) 4170316485Sdavidcs offset += ecore_grc_dump_phy(p_hwfn, p_ptt, dump_buf + offset, dump); 4171316485Sdavidcs 4172316485Sdavidcs /* Dump static debug data */ 4173316485Sdavidcs if (ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_STATIC) && dev_data->bus.state == DBG_BUS_STATE_IDLE) 4174316485Sdavidcs offset += ecore_grc_dump_static_debug(p_hwfn, p_ptt, dump_buf + offset, dump); 4175316485Sdavidcs 4176316485Sdavidcs /* Dump last section */ 4177320162Sdavidcs offset += ecore_dump_last_section(dump_buf, offset, dump); 4178316485Sdavidcs 4179316485Sdavidcs if (dump) { 4180316485Sdavidcs 4181316485Sdavidcs /* Unstall storms */ 4182316485Sdavidcs if (ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_UNSTALL)) 4183316485Sdavidcs ecore_grc_stall_storms(p_hwfn, p_ptt, false); 4184316485Sdavidcs 4185316485Sdavidcs /* Clear parity status */ 4186320162Sdavidcs if (is_asic) 4187316485Sdavidcs ecore_grc_clear_all_prty(p_hwfn, p_ptt); 4188316485Sdavidcs 4189316485Sdavidcs /* Enable all parities using MFW command */ 4190316485Sdavidcs if (parities_masked) 4191316485Sdavidcs ecore_mcp_mask_parities(p_hwfn, p_ptt, 0); 4192316485Sdavidcs } 4193316485Sdavidcs 4194316485Sdavidcs *num_dumped_dwords = offset; 4195316485Sdavidcs 4196316485Sdavidcs return DBG_STATUS_OK; 4197316485Sdavidcs} 4198316485Sdavidcs 4199316485Sdavidcs/* Writes the specified failing Idle Check rule to the specified buffer. 4200316485Sdavidcs * Returns the dumped size in dwords. 4201316485Sdavidcs */ 4202316485Sdavidcsstatic u32 ecore_idle_chk_dump_failure(struct ecore_hwfn *p_hwfn, 4203316485Sdavidcs struct ecore_ptt *p_ptt, 4204316485Sdavidcs u32 *dump_buf, 4205316485Sdavidcs bool dump, 4206316485Sdavidcs u16 rule_id, 4207316485Sdavidcs const struct dbg_idle_chk_rule *rule, 4208316485Sdavidcs u16 fail_entry_id, 4209316485Sdavidcs u32 *cond_reg_values) 4210316485Sdavidcs{ 4211316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 4212316485Sdavidcs const struct dbg_idle_chk_cond_reg *cond_regs; 4213316485Sdavidcs const struct dbg_idle_chk_info_reg *info_regs; 4214316485Sdavidcs u32 i, next_reg_offset = 0, offset = 0; 4215316485Sdavidcs struct dbg_idle_chk_result_hdr *hdr; 4216316485Sdavidcs const union dbg_idle_chk_reg *regs; 4217316485Sdavidcs u8 reg_id; 4218316485Sdavidcs 4219337519Sdavidcs hdr = (struct dbg_idle_chk_result_hdr *)dump_buf; 4220337519Sdavidcs regs = &((const union dbg_idle_chk_reg *)s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr)[rule->reg_offset]; 4221316485Sdavidcs cond_regs = ®s[0].cond_reg; 4222316485Sdavidcs info_regs = ®s[rule->num_cond_regs].info_reg; 4223316485Sdavidcs 4224316485Sdavidcs /* Dump rule data */ 4225316485Sdavidcs if (dump) { 4226316485Sdavidcs OSAL_MEMSET(hdr, 0, sizeof(*hdr)); 4227316485Sdavidcs hdr->rule_id = rule_id; 4228316485Sdavidcs hdr->mem_entry_id = fail_entry_id; 4229316485Sdavidcs hdr->severity = rule->severity; 4230316485Sdavidcs hdr->num_dumped_cond_regs = rule->num_cond_regs; 4231316485Sdavidcs } 4232316485Sdavidcs 4233316485Sdavidcs offset += IDLE_CHK_RESULT_HDR_DWORDS; 4234316485Sdavidcs 4235316485Sdavidcs /* Dump condition register values */ 4236316485Sdavidcs for (reg_id = 0; reg_id < rule->num_cond_regs; reg_id++) { 4237316485Sdavidcs const struct dbg_idle_chk_cond_reg *reg = &cond_regs[reg_id]; 4238316485Sdavidcs struct dbg_idle_chk_result_reg_hdr *reg_hdr; 4239316485Sdavidcs 4240337519Sdavidcs reg_hdr = (struct dbg_idle_chk_result_reg_hdr *)(dump_buf + offset); 4241316485Sdavidcs 4242316485Sdavidcs /* Write register header */ 4243316485Sdavidcs if (!dump) { 4244316485Sdavidcs offset += IDLE_CHK_RESULT_REG_HDR_DWORDS + reg->entry_size; 4245316485Sdavidcs continue; 4246316485Sdavidcs } 4247316485Sdavidcs 4248316485Sdavidcs offset += IDLE_CHK_RESULT_REG_HDR_DWORDS; 4249316485Sdavidcs OSAL_MEMSET(reg_hdr, 0, sizeof(*reg_hdr)); 4250316485Sdavidcs reg_hdr->start_entry = reg->start_entry; 4251316485Sdavidcs reg_hdr->size = reg->entry_size; 4252316485Sdavidcs SET_FIELD(reg_hdr->data, DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM, reg->num_entries > 1 || reg->start_entry > 0 ? 1 : 0); 4253316485Sdavidcs SET_FIELD(reg_hdr->data, DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID, reg_id); 4254316485Sdavidcs 4255316485Sdavidcs /* Write register values */ 4256316485Sdavidcs for (i = 0; i < reg_hdr->size; i++, next_reg_offset++, offset++) 4257316485Sdavidcs dump_buf[offset] = cond_reg_values[next_reg_offset]; 4258316485Sdavidcs } 4259316485Sdavidcs 4260316485Sdavidcs /* Dump info register values */ 4261316485Sdavidcs for (reg_id = 0; reg_id < rule->num_info_regs; reg_id++) { 4262316485Sdavidcs const struct dbg_idle_chk_info_reg *reg = &info_regs[reg_id]; 4263316485Sdavidcs u32 block_id; 4264316485Sdavidcs 4265316485Sdavidcs /* Check if register's block is in reset */ 4266316485Sdavidcs if (!dump) { 4267316485Sdavidcs offset += IDLE_CHK_RESULT_REG_HDR_DWORDS + reg->size; 4268316485Sdavidcs continue; 4269316485Sdavidcs } 4270316485Sdavidcs 4271316485Sdavidcs block_id = GET_FIELD(reg->data, DBG_IDLE_CHK_INFO_REG_BLOCK_ID); 4272316485Sdavidcs if (block_id >= MAX_BLOCK_ID) { 4273316485Sdavidcs DP_NOTICE(p_hwfn, true, "Invalid block_id\n"); 4274316485Sdavidcs return 0; 4275316485Sdavidcs } 4276316485Sdavidcs 4277316485Sdavidcs if (!dev_data->block_in_reset[block_id]) { 4278316485Sdavidcs struct dbg_idle_chk_result_reg_hdr *reg_hdr; 4279316485Sdavidcs bool wide_bus, eval_mode, mode_match = true; 4280316485Sdavidcs u16 modes_buf_offset; 4281316485Sdavidcs u32 addr; 4282316485Sdavidcs 4283337519Sdavidcs reg_hdr = (struct dbg_idle_chk_result_reg_hdr *)(dump_buf + offset); 4284316485Sdavidcs 4285316485Sdavidcs /* Check mode */ 4286316485Sdavidcs eval_mode = GET_FIELD(reg->mode.data, DBG_MODE_HDR_EVAL_MODE) > 0; 4287316485Sdavidcs if (eval_mode) { 4288316485Sdavidcs modes_buf_offset = GET_FIELD(reg->mode.data, DBG_MODE_HDR_MODES_BUF_OFFSET); 4289316485Sdavidcs mode_match = ecore_is_mode_match(p_hwfn, &modes_buf_offset); 4290316485Sdavidcs } 4291316485Sdavidcs 4292316485Sdavidcs if (!mode_match) 4293316485Sdavidcs continue; 4294316485Sdavidcs 4295316485Sdavidcs addr = GET_FIELD(reg->data, DBG_IDLE_CHK_INFO_REG_ADDRESS); 4296316485Sdavidcs wide_bus = GET_FIELD(reg->data, DBG_IDLE_CHK_INFO_REG_WIDE_BUS); 4297316485Sdavidcs 4298316485Sdavidcs /* Write register header */ 4299316485Sdavidcs offset += IDLE_CHK_RESULT_REG_HDR_DWORDS; 4300316485Sdavidcs hdr->num_dumped_info_regs++; 4301316485Sdavidcs OSAL_MEMSET(reg_hdr, 0, sizeof(*reg_hdr)); 4302316485Sdavidcs reg_hdr->size = reg->size; 4303316485Sdavidcs SET_FIELD(reg_hdr->data, DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID, rule->num_cond_regs + reg_id); 4304316485Sdavidcs 4305316485Sdavidcs /* Write register values */ 4306316485Sdavidcs offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, dump, addr, reg->size, wide_bus); 4307316485Sdavidcs } 4308316485Sdavidcs } 4309316485Sdavidcs 4310316485Sdavidcs return offset; 4311316485Sdavidcs} 4312316485Sdavidcs 4313316485Sdavidcs/* Dumps idle check rule entries. Returns the dumped size in dwords. */ 4314316485Sdavidcsstatic u32 ecore_idle_chk_dump_rule_entries(struct ecore_hwfn *p_hwfn, 4315316485Sdavidcs struct ecore_ptt *p_ptt, 4316316485Sdavidcs u32 *dump_buf, 4317316485Sdavidcs bool dump, 4318316485Sdavidcs const struct dbg_idle_chk_rule *input_rules, 4319316485Sdavidcs u32 num_input_rules, 4320316485Sdavidcs u32 *num_failing_rules) 4321316485Sdavidcs{ 4322316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 4323316485Sdavidcs u32 cond_reg_values[IDLE_CHK_MAX_ENTRIES_SIZE]; 4324316485Sdavidcs u32 i, offset = 0; 4325316485Sdavidcs u16 entry_id; 4326316485Sdavidcs u8 reg_id; 4327316485Sdavidcs 4328316485Sdavidcs *num_failing_rules = 0; 4329316485Sdavidcs 4330316485Sdavidcs for (i = 0; i < num_input_rules; i++) { 4331316485Sdavidcs const struct dbg_idle_chk_cond_reg *cond_regs; 4332316485Sdavidcs const struct dbg_idle_chk_rule *rule; 4333316485Sdavidcs const union dbg_idle_chk_reg *regs; 4334316485Sdavidcs u16 num_reg_entries = 1; 4335316485Sdavidcs bool check_rule = true; 4336316485Sdavidcs const u32 *imm_values; 4337316485Sdavidcs 4338316485Sdavidcs rule = &input_rules[i]; 4339337519Sdavidcs regs = &((const union dbg_idle_chk_reg *)s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr)[rule->reg_offset]; 4340316485Sdavidcs cond_regs = ®s[0].cond_reg; 4341316485Sdavidcs imm_values = &s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr[rule->imm_offset]; 4342316485Sdavidcs 4343316485Sdavidcs /* Check if all condition register blocks are out of reset, and 4344316485Sdavidcs * find maximal number of entries (all condition registers that 4345316485Sdavidcs * are memories must have the same size, which is > 1). 4346316485Sdavidcs */ 4347316485Sdavidcs for (reg_id = 0; reg_id < rule->num_cond_regs && check_rule; reg_id++) { 4348316485Sdavidcs u32 block_id = GET_FIELD(cond_regs[reg_id].data, DBG_IDLE_CHK_COND_REG_BLOCK_ID); 4349316485Sdavidcs 4350316485Sdavidcs if (block_id >= MAX_BLOCK_ID) { 4351316485Sdavidcs DP_NOTICE(p_hwfn, true, "Invalid block_id\n"); 4352316485Sdavidcs return 0; 4353316485Sdavidcs } 4354316485Sdavidcs 4355316485Sdavidcs check_rule = !dev_data->block_in_reset[block_id]; 4356316485Sdavidcs if (cond_regs[reg_id].num_entries > num_reg_entries) 4357316485Sdavidcs num_reg_entries = cond_regs[reg_id].num_entries; 4358316485Sdavidcs } 4359316485Sdavidcs 4360316485Sdavidcs if (!check_rule && dump) 4361316485Sdavidcs continue; 4362316485Sdavidcs 4363320162Sdavidcs if (!dump) { 4364320162Sdavidcs u32 entry_dump_size = ecore_idle_chk_dump_failure(p_hwfn, p_ptt, dump_buf + offset, false, rule->rule_id, rule, 0, OSAL_NULL); 4365320162Sdavidcs 4366320162Sdavidcs offset += num_reg_entries * entry_dump_size; 4367320162Sdavidcs (*num_failing_rules) += num_reg_entries; 4368320162Sdavidcs continue; 4369320162Sdavidcs } 4370320162Sdavidcs 4371316485Sdavidcs /* Go over all register entries (number of entries is the same for all 4372316485Sdavidcs * condition registers). 4373316485Sdavidcs */ 4374316485Sdavidcs for (entry_id = 0; entry_id < num_reg_entries; entry_id++) { 4375316485Sdavidcs u32 next_reg_offset = 0; 4376316485Sdavidcs 4377316485Sdavidcs /* Read current entry of all condition registers */ 4378316485Sdavidcs for (reg_id = 0; reg_id < rule->num_cond_regs; reg_id++) { 4379316485Sdavidcs const struct dbg_idle_chk_cond_reg *reg = &cond_regs[reg_id]; 4380316485Sdavidcs u32 padded_entry_size, addr; 4381316485Sdavidcs bool wide_bus; 4382316485Sdavidcs 4383316485Sdavidcs /* Find GRC address (if it's a memory, the address of the 4384316485Sdavidcs * specific entry is calculated). 4385316485Sdavidcs */ 4386316485Sdavidcs addr = GET_FIELD(reg->data, DBG_IDLE_CHK_COND_REG_ADDRESS); 4387316485Sdavidcs wide_bus = GET_FIELD(reg->data, DBG_IDLE_CHK_COND_REG_WIDE_BUS); 4388316485Sdavidcs if (reg->num_entries > 1 || reg->start_entry > 0) { 4389316485Sdavidcs padded_entry_size = reg->entry_size > 1 ? OSAL_ROUNDUP_POW_OF_TWO(reg->entry_size) : 1; 4390316485Sdavidcs addr += (reg->start_entry + entry_id) * padded_entry_size; 4391316485Sdavidcs } 4392316485Sdavidcs 4393316485Sdavidcs /* Read registers */ 4394316485Sdavidcs if (next_reg_offset + reg->entry_size >= IDLE_CHK_MAX_ENTRIES_SIZE) { 4395316485Sdavidcs DP_NOTICE(p_hwfn, true, "idle check registers entry is too large\n"); 4396316485Sdavidcs return 0; 4397316485Sdavidcs } 4398316485Sdavidcs 4399316485Sdavidcs next_reg_offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, cond_reg_values + next_reg_offset, dump, addr, reg->entry_size, wide_bus); 4400316485Sdavidcs } 4401316485Sdavidcs 4402316485Sdavidcs /* Call rule condition function. if returns true, it's a failure.*/ 4403316485Sdavidcs if ((*cond_arr[rule->cond_id])(cond_reg_values, imm_values)) { 4404316485Sdavidcs offset += ecore_idle_chk_dump_failure(p_hwfn, p_ptt, dump_buf + offset, dump, rule->rule_id, rule, entry_id, cond_reg_values); 4405316485Sdavidcs (*num_failing_rules)++; 4406316485Sdavidcs } 4407316485Sdavidcs } 4408316485Sdavidcs } 4409316485Sdavidcs 4410316485Sdavidcs return offset; 4411316485Sdavidcs} 4412316485Sdavidcs 4413316485Sdavidcs/* Performs Idle Check Dump to the specified buffer. 4414316485Sdavidcs * Returns the dumped size in dwords. 4415316485Sdavidcs */ 4416316485Sdavidcsstatic u32 ecore_idle_chk_dump(struct ecore_hwfn *p_hwfn, 4417316485Sdavidcs struct ecore_ptt *p_ptt, 4418316485Sdavidcs u32 *dump_buf, 4419316485Sdavidcs bool dump) 4420316485Sdavidcs{ 4421316485Sdavidcs u32 num_failing_rules_offset, offset = 0, input_offset = 0, num_failing_rules = 0; 4422316485Sdavidcs 4423316485Sdavidcs /* Dump global params */ 4424316485Sdavidcs offset += ecore_dump_common_global_params(p_hwfn, p_ptt, dump_buf + offset, dump, 1); 4425316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "dump-type", "idle-chk"); 4426316485Sdavidcs 4427316485Sdavidcs /* Dump idle check section header with a single parameter */ 4428316485Sdavidcs offset += ecore_dump_section_hdr(dump_buf + offset, dump, "idle_chk", 1); 4429316485Sdavidcs num_failing_rules_offset = offset; 4430316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "num_rules", 0); 4431316485Sdavidcs 4432316485Sdavidcs while (input_offset < s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].size_in_dwords) { 4433337519Sdavidcs const struct dbg_idle_chk_cond_hdr *cond_hdr = (const struct dbg_idle_chk_cond_hdr *)&s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].ptr[input_offset++]; 4434316485Sdavidcs bool eval_mode, mode_match = true; 4435316485Sdavidcs u32 curr_failing_rules; 4436316485Sdavidcs u16 modes_buf_offset; 4437316485Sdavidcs 4438316485Sdavidcs /* Check mode */ 4439316485Sdavidcs eval_mode = GET_FIELD(cond_hdr->mode.data, DBG_MODE_HDR_EVAL_MODE) > 0; 4440316485Sdavidcs if (eval_mode) { 4441316485Sdavidcs modes_buf_offset = GET_FIELD(cond_hdr->mode.data, DBG_MODE_HDR_MODES_BUF_OFFSET); 4442316485Sdavidcs mode_match = ecore_is_mode_match(p_hwfn, &modes_buf_offset); 4443316485Sdavidcs } 4444316485Sdavidcs 4445316485Sdavidcs if (mode_match) { 4446337519Sdavidcs offset += ecore_idle_chk_dump_rule_entries(p_hwfn, p_ptt, dump_buf + offset, dump, (const struct dbg_idle_chk_rule *)&s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].ptr[input_offset], cond_hdr->data_size / IDLE_CHK_RULE_SIZE_DWORDS, &curr_failing_rules); 4447316485Sdavidcs num_failing_rules += curr_failing_rules; 4448316485Sdavidcs } 4449316485Sdavidcs 4450316485Sdavidcs input_offset += cond_hdr->data_size; 4451316485Sdavidcs } 4452316485Sdavidcs 4453316485Sdavidcs /* Overwrite num_rules parameter */ 4454316485Sdavidcs if (dump) 4455316485Sdavidcs ecore_dump_num_param(dump_buf + num_failing_rules_offset, dump, "num_rules", num_failing_rules); 4456316485Sdavidcs 4457316485Sdavidcs /* Dump last section */ 4458320162Sdavidcs offset += ecore_dump_last_section(dump_buf, offset, dump); 4459316485Sdavidcs 4460316485Sdavidcs return offset; 4461316485Sdavidcs} 4462316485Sdavidcs 4463316485Sdavidcs/* Finds the meta data image in NVRAM */ 4464316485Sdavidcsstatic enum dbg_status ecore_find_nvram_image(struct ecore_hwfn *p_hwfn, 4465316485Sdavidcs struct ecore_ptt *p_ptt, 4466316485Sdavidcs u32 image_type, 4467316485Sdavidcs u32 *nvram_offset_bytes, 4468316485Sdavidcs u32 *nvram_size_bytes) 4469316485Sdavidcs{ 4470316485Sdavidcs u32 ret_mcp_resp, ret_mcp_param, ret_txn_size; 4471316485Sdavidcs struct mcp_file_att file_att; 4472316485Sdavidcs int nvm_result; 4473316485Sdavidcs 4474316485Sdavidcs /* Call NVRAM get file command */ 4475337519Sdavidcs nvm_result = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_GET_FILE_ATT, image_type, &ret_mcp_resp, &ret_mcp_param, &ret_txn_size, (u32 *)&file_att); 4476316485Sdavidcs 4477316485Sdavidcs /* Check response */ 4478316485Sdavidcs if (nvm_result || (ret_mcp_resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK) 4479316485Sdavidcs return DBG_STATUS_NVRAM_GET_IMAGE_FAILED; 4480316485Sdavidcs 4481316485Sdavidcs /* Update return values */ 4482316485Sdavidcs *nvram_offset_bytes = file_att.nvm_start_addr; 4483316485Sdavidcs *nvram_size_bytes = file_att.len; 4484316485Sdavidcs 4485316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "find_nvram_image: found NVRAM image of type %d in NVRAM offset %d bytes with size %d bytes\n", image_type, *nvram_offset_bytes, *nvram_size_bytes); 4486316485Sdavidcs 4487316485Sdavidcs /* Check alignment */ 4488316485Sdavidcs if (*nvram_size_bytes & 0x3) 4489316485Sdavidcs return DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE; 4490316485Sdavidcs 4491316485Sdavidcs return DBG_STATUS_OK; 4492316485Sdavidcs} 4493316485Sdavidcs 4494316485Sdavidcs/* Reads data from NVRAM */ 4495316485Sdavidcsstatic enum dbg_status ecore_nvram_read(struct ecore_hwfn *p_hwfn, 4496316485Sdavidcs struct ecore_ptt *p_ptt, 4497316485Sdavidcs u32 nvram_offset_bytes, 4498316485Sdavidcs u32 nvram_size_bytes, 4499316485Sdavidcs u32 *ret_buf) 4500316485Sdavidcs{ 4501316485Sdavidcs u32 ret_mcp_resp, ret_mcp_param, ret_read_size, bytes_to_copy; 4502316485Sdavidcs s32 bytes_left = nvram_size_bytes; 4503316485Sdavidcs u32 read_offset = 0; 4504316485Sdavidcs 4505316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "nvram_read: reading image of size %d bytes from NVRAM\n", nvram_size_bytes); 4506316485Sdavidcs 4507316485Sdavidcs do { 4508316485Sdavidcs bytes_to_copy = (bytes_left > MCP_DRV_NVM_BUF_LEN) ? MCP_DRV_NVM_BUF_LEN : bytes_left; 4509316485Sdavidcs 4510316485Sdavidcs /* Call NVRAM read command */ 4511337519Sdavidcs if (ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_READ_NVRAM, (nvram_offset_bytes + read_offset) | (bytes_to_copy << DRV_MB_PARAM_NVM_LEN_OFFSET), &ret_mcp_resp, &ret_mcp_param, &ret_read_size, (u32 *)((u8 *)ret_buf + read_offset))) 4512316485Sdavidcs return DBG_STATUS_NVRAM_READ_FAILED; 4513316485Sdavidcs 4514316485Sdavidcs /* Check response */ 4515316485Sdavidcs if ((ret_mcp_resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK) 4516316485Sdavidcs return DBG_STATUS_NVRAM_READ_FAILED; 4517316485Sdavidcs 4518316485Sdavidcs /* Update read offset */ 4519316485Sdavidcs read_offset += ret_read_size; 4520316485Sdavidcs bytes_left -= ret_read_size; 4521316485Sdavidcs } while (bytes_left > 0); 4522316485Sdavidcs 4523316485Sdavidcs return DBG_STATUS_OK; 4524316485Sdavidcs} 4525316485Sdavidcs 4526316485Sdavidcs/* Get info on the MCP Trace data in the scratchpad: 4527316485Sdavidcs * - trace_data_grc_addr (OUT): trace data GRC address in bytes 4528316485Sdavidcs * - trace_data_size (OUT): trace data size in bytes (without the header) 4529316485Sdavidcs */ 4530316485Sdavidcsstatic enum dbg_status ecore_mcp_trace_get_data_info(struct ecore_hwfn *p_hwfn, 4531316485Sdavidcs struct ecore_ptt *p_ptt, 4532316485Sdavidcs u32 *trace_data_grc_addr, 4533316485Sdavidcs u32 *trace_data_size) 4534316485Sdavidcs{ 4535316485Sdavidcs u32 spad_trace_offsize, signature; 4536316485Sdavidcs 4537316485Sdavidcs /* Read trace section offsize structure from MCP scratchpad */ 4538316485Sdavidcs spad_trace_offsize = ecore_rd(p_hwfn, p_ptt, MCP_SPAD_TRACE_OFFSIZE_ADDR); 4539316485Sdavidcs 4540316485Sdavidcs /* Extract trace section address from offsize (in scratchpad) */ 4541316485Sdavidcs *trace_data_grc_addr = MCP_REG_SCRATCH + SECTION_OFFSET(spad_trace_offsize); 4542316485Sdavidcs 4543316485Sdavidcs /* Read signature from MCP trace section */ 4544316485Sdavidcs signature = ecore_rd(p_hwfn, p_ptt, *trace_data_grc_addr + OFFSETOF(struct mcp_trace, signature)); 4545316485Sdavidcs 4546316485Sdavidcs if (signature != MFW_TRACE_SIGNATURE) 4547316485Sdavidcs return DBG_STATUS_INVALID_TRACE_SIGNATURE; 4548316485Sdavidcs 4549316485Sdavidcs /* Read trace size from MCP trace section */ 4550316485Sdavidcs *trace_data_size = ecore_rd(p_hwfn, p_ptt, *trace_data_grc_addr + OFFSETOF(struct mcp_trace, size)); 4551316485Sdavidcs 4552316485Sdavidcs return DBG_STATUS_OK; 4553316485Sdavidcs} 4554316485Sdavidcs 4555316485Sdavidcs/* Reads MCP trace meta data image from NVRAM 4556316485Sdavidcs * - running_bundle_id (OUT): running bundle ID (invalid when loaded from file) 4557316485Sdavidcs * - trace_meta_offset (OUT): trace meta offset in NVRAM in bytes (invalid when 4558316485Sdavidcs * loaded from file). 4559316485Sdavidcs * - trace_meta_size (OUT): size in bytes of the trace meta data. 4560316485Sdavidcs */ 4561316485Sdavidcsstatic enum dbg_status ecore_mcp_trace_get_meta_info(struct ecore_hwfn *p_hwfn, 4562316485Sdavidcs struct ecore_ptt *p_ptt, 4563316485Sdavidcs u32 trace_data_size_bytes, 4564316485Sdavidcs u32 *running_bundle_id, 4565316485Sdavidcs u32 *trace_meta_offset, 4566316485Sdavidcs u32 *trace_meta_size) 4567316485Sdavidcs{ 4568316485Sdavidcs u32 spad_trace_offsize, nvram_image_type, running_mfw_addr; 4569316485Sdavidcs 4570316485Sdavidcs /* Read MCP trace section offsize structure from MCP scratchpad */ 4571316485Sdavidcs spad_trace_offsize = ecore_rd(p_hwfn, p_ptt, MCP_SPAD_TRACE_OFFSIZE_ADDR); 4572316485Sdavidcs 4573316485Sdavidcs /* Find running bundle ID */ 4574316485Sdavidcs running_mfw_addr = MCP_REG_SCRATCH + SECTION_OFFSET(spad_trace_offsize) + SECTION_SIZE(spad_trace_offsize) + trace_data_size_bytes; 4575316485Sdavidcs *running_bundle_id = ecore_rd(p_hwfn, p_ptt, running_mfw_addr); 4576316485Sdavidcs if (*running_bundle_id > 1) 4577316485Sdavidcs return DBG_STATUS_INVALID_NVRAM_BUNDLE; 4578316485Sdavidcs 4579316485Sdavidcs /* Find image in NVRAM */ 4580316485Sdavidcs nvram_image_type = (*running_bundle_id == DIR_ID_1) ? NVM_TYPE_MFW_TRACE1 : NVM_TYPE_MFW_TRACE2; 4581316485Sdavidcs return ecore_find_nvram_image(p_hwfn, p_ptt, nvram_image_type, trace_meta_offset, trace_meta_size); 4582316485Sdavidcs} 4583316485Sdavidcs 4584316485Sdavidcs/* Reads the MCP Trace meta data from NVRAM into the specified buffer */ 4585316485Sdavidcsstatic enum dbg_status ecore_mcp_trace_read_meta(struct ecore_hwfn *p_hwfn, 4586316485Sdavidcs struct ecore_ptt *p_ptt, 4587316485Sdavidcs u32 nvram_offset_in_bytes, 4588316485Sdavidcs u32 size_in_bytes, 4589316485Sdavidcs u32 *buf) 4590316485Sdavidcs{ 4591337519Sdavidcs u8 modules_num, module_len, i, *byte_buf = (u8 *)buf; 4592316485Sdavidcs enum dbg_status status; 4593316485Sdavidcs u32 signature; 4594316485Sdavidcs 4595316485Sdavidcs /* Read meta data from NVRAM */ 4596316485Sdavidcs status = ecore_nvram_read(p_hwfn, p_ptt, nvram_offset_in_bytes, size_in_bytes, buf); 4597316485Sdavidcs if (status != DBG_STATUS_OK) 4598316485Sdavidcs return status; 4599316485Sdavidcs 4600316485Sdavidcs /* Extract and check first signature */ 4601316485Sdavidcs signature = ecore_read_unaligned_dword(byte_buf); 4602316485Sdavidcs byte_buf += sizeof(signature); 4603316485Sdavidcs if (signature != NVM_MAGIC_VALUE) 4604316485Sdavidcs return DBG_STATUS_INVALID_TRACE_SIGNATURE; 4605316485Sdavidcs 4606316485Sdavidcs /* Extract number of modules */ 4607316485Sdavidcs modules_num = *(byte_buf++); 4608316485Sdavidcs 4609316485Sdavidcs /* Skip all modules */ 4610316485Sdavidcs for (i = 0; i < modules_num; i++) { 4611316485Sdavidcs module_len = *(byte_buf++); 4612316485Sdavidcs byte_buf += module_len; 4613316485Sdavidcs } 4614316485Sdavidcs 4615316485Sdavidcs /* Extract and check second signature */ 4616316485Sdavidcs signature = ecore_read_unaligned_dword(byte_buf); 4617316485Sdavidcs byte_buf += sizeof(signature); 4618316485Sdavidcs if (signature != NVM_MAGIC_VALUE) 4619316485Sdavidcs return DBG_STATUS_INVALID_TRACE_SIGNATURE; 4620316485Sdavidcs 4621316485Sdavidcs return DBG_STATUS_OK; 4622316485Sdavidcs} 4623316485Sdavidcs 4624316485Sdavidcs/* Dump MCP Trace */ 4625316485Sdavidcsstatic enum dbg_status ecore_mcp_trace_dump(struct ecore_hwfn *p_hwfn, 4626316485Sdavidcs struct ecore_ptt *p_ptt, 4627316485Sdavidcs u32 *dump_buf, 4628316485Sdavidcs bool dump, 4629316485Sdavidcs u32 *num_dumped_dwords) 4630316485Sdavidcs{ 4631316485Sdavidcs u32 trace_meta_offset_bytes = 0, trace_meta_size_bytes = 0, trace_meta_size_dwords = 0; 4632316485Sdavidcs u32 trace_data_grc_addr, trace_data_size_bytes, trace_data_size_dwords; 4633320162Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 4634316485Sdavidcs u32 running_bundle_id, offset = 0; 4635316485Sdavidcs enum dbg_status status; 4636316485Sdavidcs bool mcp_access; 4637316485Sdavidcs int halted = 0; 4638316485Sdavidcs 4639316485Sdavidcs *num_dumped_dwords = 0; 4640316485Sdavidcs 4641320162Sdavidcs mcp_access = dev_data->platform_id == PLATFORM_ASIC && !ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP); 4642316485Sdavidcs 4643316485Sdavidcs /* Get trace data info */ 4644316485Sdavidcs status = ecore_mcp_trace_get_data_info(p_hwfn, p_ptt, &trace_data_grc_addr, &trace_data_size_bytes); 4645316485Sdavidcs if (status != DBG_STATUS_OK) 4646316485Sdavidcs return status; 4647316485Sdavidcs 4648316485Sdavidcs /* Dump global params */ 4649316485Sdavidcs offset += ecore_dump_common_global_params(p_hwfn, p_ptt, dump_buf + offset, dump, 1); 4650316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "dump-type", "mcp-trace"); 4651316485Sdavidcs 4652316485Sdavidcs /* Halt MCP while reading from scratchpad so the read data will be 4653316485Sdavidcs * consistent. if halt fails, MCP trace is taken anyway, with a small 4654316485Sdavidcs * risk that it may be corrupt. 4655316485Sdavidcs */ 4656316485Sdavidcs if (dump && mcp_access) { 4657316485Sdavidcs halted = !ecore_mcp_halt(p_hwfn, p_ptt); 4658316485Sdavidcs if (!halted) 4659316485Sdavidcs DP_NOTICE(p_hwfn, false, "MCP halt failed!\n"); 4660316485Sdavidcs } 4661316485Sdavidcs 4662316485Sdavidcs /* Find trace data size */ 4663316485Sdavidcs trace_data_size_dwords = DIV_ROUND_UP(trace_data_size_bytes + sizeof(struct mcp_trace), BYTES_IN_DWORD); 4664316485Sdavidcs 4665316485Sdavidcs /* Dump trace data section header and param */ 4666316485Sdavidcs offset += ecore_dump_section_hdr(dump_buf + offset, dump, "mcp_trace_data", 1); 4667316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "size", trace_data_size_dwords); 4668316485Sdavidcs 4669316485Sdavidcs /* Read trace data from scratchpad into dump buffer */ 4670316485Sdavidcs offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, dump, BYTES_TO_DWORDS(trace_data_grc_addr), trace_data_size_dwords, false); 4671316485Sdavidcs 4672316485Sdavidcs /* Resume MCP (only if halt succeeded) */ 4673316485Sdavidcs if (halted && ecore_mcp_resume(p_hwfn, p_ptt)) 4674316485Sdavidcs DP_NOTICE(p_hwfn, false, "Failed to resume MCP after halt!\n"); 4675316485Sdavidcs 4676316485Sdavidcs /* Dump trace meta section header */ 4677316485Sdavidcs offset += ecore_dump_section_hdr(dump_buf + offset, dump, "mcp_trace_meta", 1); 4678316485Sdavidcs 4679316485Sdavidcs /* Read trace meta only if NVRAM access is enabled 4680316485Sdavidcs * (trace_meta_size_bytes is dword-aligned). 4681316485Sdavidcs */ 4682316485Sdavidcs if (OSAL_NVM_IS_ACCESS_ENABLED(p_hwfn) && mcp_access) { 4683316485Sdavidcs status = ecore_mcp_trace_get_meta_info(p_hwfn, p_ptt, trace_data_size_bytes, &running_bundle_id, &trace_meta_offset_bytes, &trace_meta_size_bytes); 4684316485Sdavidcs if (status == DBG_STATUS_OK) 4685316485Sdavidcs trace_meta_size_dwords = BYTES_TO_DWORDS(trace_meta_size_bytes); 4686316485Sdavidcs } 4687316485Sdavidcs 4688316485Sdavidcs /* Dump trace meta size param */ 4689316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "size", trace_meta_size_dwords); 4690316485Sdavidcs 4691316485Sdavidcs /* Read trace meta image into dump buffer */ 4692316485Sdavidcs if (dump && trace_meta_size_dwords) 4693316485Sdavidcs status = ecore_mcp_trace_read_meta(p_hwfn, p_ptt, trace_meta_offset_bytes, trace_meta_size_bytes, dump_buf + offset); 4694316485Sdavidcs if (status == DBG_STATUS_OK) 4695316485Sdavidcs offset += trace_meta_size_dwords; 4696316485Sdavidcs 4697316485Sdavidcs /* Dump last section */ 4698320162Sdavidcs offset += ecore_dump_last_section(dump_buf, offset, dump); 4699316485Sdavidcs 4700316485Sdavidcs *num_dumped_dwords = offset; 4701316485Sdavidcs 4702316485Sdavidcs /* If no mcp access, indicate that the dump doesn't contain the meta 4703316485Sdavidcs * data from NVRAM. 4704316485Sdavidcs */ 4705316485Sdavidcs return mcp_access ? status : DBG_STATUS_NVRAM_GET_IMAGE_FAILED; 4706316485Sdavidcs} 4707316485Sdavidcs 4708316485Sdavidcs/* Dump GRC FIFO */ 4709316485Sdavidcsstatic enum dbg_status ecore_reg_fifo_dump(struct ecore_hwfn *p_hwfn, 4710316485Sdavidcs struct ecore_ptt *p_ptt, 4711316485Sdavidcs u32 *dump_buf, 4712316485Sdavidcs bool dump, 4713316485Sdavidcs u32 *num_dumped_dwords) 4714316485Sdavidcs{ 4715316485Sdavidcs u32 dwords_read, size_param_offset, offset = 0; 4716316485Sdavidcs bool fifo_has_data; 4717316485Sdavidcs 4718316485Sdavidcs *num_dumped_dwords = 0; 4719316485Sdavidcs 4720316485Sdavidcs /* Dump global params */ 4721316485Sdavidcs offset += ecore_dump_common_global_params(p_hwfn, p_ptt, dump_buf + offset, dump, 1); 4722316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "dump-type", "reg-fifo"); 4723316485Sdavidcs 4724316485Sdavidcs /* Dump fifo data section header and param. The size param is 0 for 4725316485Sdavidcs * now, and is overwritten after reading the FIFO. 4726316485Sdavidcs */ 4727316485Sdavidcs offset += ecore_dump_section_hdr(dump_buf + offset, dump, "reg_fifo_data", 1); 4728316485Sdavidcs size_param_offset = offset; 4729316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "size", 0); 4730316485Sdavidcs 4731316485Sdavidcs if (dump) { 4732316485Sdavidcs fifo_has_data = ecore_rd(p_hwfn, p_ptt, GRC_REG_TRACE_FIFO_VALID_DATA) > 0; 4733316485Sdavidcs 4734316485Sdavidcs /* Pull available data from fifo. Use DMAE since this is 4735316485Sdavidcs * widebus memory and must be accessed atomically. Test for 4736316485Sdavidcs * dwords_read not passing buffer size since more entries could 4737316485Sdavidcs * be added to the buffer as we 4738316485Sdavidcs * are emptying it. 4739316485Sdavidcs */ 4740337519Sdavidcs for (dwords_read = 0; fifo_has_data && dwords_read < REG_FIFO_DEPTH_DWORDS; dwords_read += REG_FIFO_ELEMENT_DWORDS) { 4741337519Sdavidcs offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, true, BYTES_TO_DWORDS(GRC_REG_TRACE_FIFO), REG_FIFO_ELEMENT_DWORDS, true); 4742316485Sdavidcs fifo_has_data = ecore_rd(p_hwfn, p_ptt, GRC_REG_TRACE_FIFO_VALID_DATA) > 0; 4743316485Sdavidcs } 4744316485Sdavidcs 4745316485Sdavidcs ecore_dump_num_param(dump_buf + size_param_offset, dump, "size", dwords_read); 4746316485Sdavidcs } 4747316485Sdavidcs else { 4748316485Sdavidcs 4749316485Sdavidcs /* FIFO max size is REG_FIFO_DEPTH_DWORDS. There is no way to 4750316485Sdavidcs * test how much data is available, except for reading it. 4751316485Sdavidcs */ 4752316485Sdavidcs offset += REG_FIFO_DEPTH_DWORDS; 4753316485Sdavidcs } 4754316485Sdavidcs 4755316485Sdavidcs /* Dump last section */ 4756320162Sdavidcs offset += ecore_dump_last_section(dump_buf, offset, dump); 4757316485Sdavidcs 4758316485Sdavidcs *num_dumped_dwords = offset; 4759316485Sdavidcs 4760316485Sdavidcs return DBG_STATUS_OK; 4761316485Sdavidcs} 4762316485Sdavidcs 4763316485Sdavidcs/* Dump IGU FIFO */ 4764316485Sdavidcsstatic enum dbg_status ecore_igu_fifo_dump(struct ecore_hwfn *p_hwfn, 4765316485Sdavidcs struct ecore_ptt *p_ptt, 4766316485Sdavidcs u32 *dump_buf, 4767316485Sdavidcs bool dump, 4768316485Sdavidcs u32 *num_dumped_dwords) 4769316485Sdavidcs{ 4770316485Sdavidcs u32 dwords_read, size_param_offset, offset = 0; 4771316485Sdavidcs bool fifo_has_data; 4772316485Sdavidcs 4773316485Sdavidcs *num_dumped_dwords = 0; 4774316485Sdavidcs 4775316485Sdavidcs /* Dump global params */ 4776316485Sdavidcs offset += ecore_dump_common_global_params(p_hwfn, p_ptt, dump_buf + offset, dump, 1); 4777316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "dump-type", "igu-fifo"); 4778316485Sdavidcs 4779316485Sdavidcs /* Dump fifo data section header and param. The size param is 0 for 4780316485Sdavidcs * now, and is overwritten after reading the FIFO. 4781316485Sdavidcs */ 4782316485Sdavidcs offset += ecore_dump_section_hdr(dump_buf + offset, dump, "igu_fifo_data", 1); 4783316485Sdavidcs size_param_offset = offset; 4784316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "size", 0); 4785316485Sdavidcs 4786316485Sdavidcs if (dump) { 4787316485Sdavidcs fifo_has_data = ecore_rd(p_hwfn, p_ptt, IGU_REG_ERROR_HANDLING_DATA_VALID) > 0; 4788316485Sdavidcs 4789316485Sdavidcs /* Pull available data from fifo. Use DMAE since this is 4790316485Sdavidcs * widebus memory and must be accessed atomically. Test for 4791316485Sdavidcs * dwords_read not passing buffer size since more entries could 4792316485Sdavidcs * be added to the buffer as we are emptying it. 4793316485Sdavidcs */ 4794337519Sdavidcs for (dwords_read = 0; fifo_has_data && dwords_read < IGU_FIFO_DEPTH_DWORDS; dwords_read += IGU_FIFO_ELEMENT_DWORDS) { 4795337519Sdavidcs offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, true, BYTES_TO_DWORDS(IGU_REG_ERROR_HANDLING_MEMORY), IGU_FIFO_ELEMENT_DWORDS, true); 4796316485Sdavidcs fifo_has_data = ecore_rd(p_hwfn, p_ptt, IGU_REG_ERROR_HANDLING_DATA_VALID) > 0; 4797316485Sdavidcs } 4798316485Sdavidcs 4799316485Sdavidcs ecore_dump_num_param(dump_buf + size_param_offset, dump, "size", dwords_read); 4800316485Sdavidcs } 4801316485Sdavidcs else { 4802316485Sdavidcs 4803316485Sdavidcs /* FIFO max size is IGU_FIFO_DEPTH_DWORDS. There is no way to 4804316485Sdavidcs * test how much data is available, except for reading it. 4805316485Sdavidcs */ 4806316485Sdavidcs offset += IGU_FIFO_DEPTH_DWORDS; 4807316485Sdavidcs } 4808316485Sdavidcs 4809316485Sdavidcs /* Dump last section */ 4810320162Sdavidcs offset += ecore_dump_last_section(dump_buf, offset, dump); 4811316485Sdavidcs 4812316485Sdavidcs *num_dumped_dwords = offset; 4813316485Sdavidcs 4814316485Sdavidcs return DBG_STATUS_OK; 4815316485Sdavidcs} 4816316485Sdavidcs 4817316485Sdavidcs/* Protection Override dump */ 4818316485Sdavidcsstatic enum dbg_status ecore_protection_override_dump(struct ecore_hwfn *p_hwfn, 4819316485Sdavidcs struct ecore_ptt *p_ptt, 4820316485Sdavidcs u32 *dump_buf, 4821316485Sdavidcs bool dump, 4822316485Sdavidcs u32 *num_dumped_dwords) 4823316485Sdavidcs{ 4824316485Sdavidcs u32 size_param_offset, override_window_dwords, offset = 0; 4825316485Sdavidcs 4826316485Sdavidcs *num_dumped_dwords = 0; 4827316485Sdavidcs 4828316485Sdavidcs /* Dump global params */ 4829316485Sdavidcs offset += ecore_dump_common_global_params(p_hwfn, p_ptt, dump_buf + offset, dump, 1); 4830316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "dump-type", "protection-override"); 4831316485Sdavidcs 4832316485Sdavidcs /* Dump data section header and param. The size param is 0 for now, 4833316485Sdavidcs * and is overwritten after reading the data. 4834316485Sdavidcs */ 4835316485Sdavidcs offset += ecore_dump_section_hdr(dump_buf + offset, dump, "protection_override_data", 1); 4836316485Sdavidcs size_param_offset = offset; 4837316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "size", 0); 4838316485Sdavidcs 4839316485Sdavidcs if (dump) { 4840316485Sdavidcs /* Add override window info to buffer */ 4841316485Sdavidcs override_window_dwords = ecore_rd(p_hwfn, p_ptt, GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW) * PROTECTION_OVERRIDE_ELEMENT_DWORDS; 4842337519Sdavidcs offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, true, BYTES_TO_DWORDS(GRC_REG_PROTECTION_OVERRIDE_WINDOW), override_window_dwords, true); 4843316485Sdavidcs ecore_dump_num_param(dump_buf + size_param_offset, dump, "size", override_window_dwords); 4844316485Sdavidcs } 4845316485Sdavidcs else { 4846316485Sdavidcs offset += PROTECTION_OVERRIDE_DEPTH_DWORDS; 4847316485Sdavidcs } 4848316485Sdavidcs 4849316485Sdavidcs /* Dump last section */ 4850320162Sdavidcs offset += ecore_dump_last_section(dump_buf, offset, dump); 4851316485Sdavidcs 4852316485Sdavidcs *num_dumped_dwords = offset; 4853316485Sdavidcs 4854316485Sdavidcs return DBG_STATUS_OK; 4855316485Sdavidcs} 4856316485Sdavidcs 4857316485Sdavidcs/* Performs FW Asserts Dump to the specified buffer. 4858316485Sdavidcs * Returns the dumped size in dwords. 4859316485Sdavidcs */ 4860316485Sdavidcsstatic u32 ecore_fw_asserts_dump(struct ecore_hwfn *p_hwfn, 4861316485Sdavidcs struct ecore_ptt *p_ptt, 4862316485Sdavidcs u32 *dump_buf, 4863316485Sdavidcs bool dump) 4864316485Sdavidcs{ 4865316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 4866316485Sdavidcs struct fw_asserts_ram_section *asserts; 4867316485Sdavidcs char storm_letter_str[2] = "?"; 4868316485Sdavidcs struct fw_info fw_info; 4869316485Sdavidcs u32 offset = 0; 4870316485Sdavidcs u8 storm_id; 4871316485Sdavidcs 4872316485Sdavidcs /* Dump global params */ 4873316485Sdavidcs offset += ecore_dump_common_global_params(p_hwfn, p_ptt, dump_buf + offset, dump, 1); 4874316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "dump-type", "fw-asserts"); 4875316485Sdavidcs 4876316485Sdavidcs /* Find Storm dump size */ 4877316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 4878316485Sdavidcs u32 fw_asserts_section_addr, next_list_idx_addr, next_list_idx, last_list_idx, addr; 4879316485Sdavidcs struct storm_defs *storm = &s_storm_defs[storm_id]; 4880316485Sdavidcs 4881316485Sdavidcs if (dev_data->block_in_reset[storm->block_id]) 4882316485Sdavidcs continue; 4883316485Sdavidcs 4884316485Sdavidcs /* Read FW info for the current Storm */ 4885316485Sdavidcs ecore_read_fw_info(p_hwfn, p_ptt, storm_id, &fw_info); 4886316485Sdavidcs 4887316485Sdavidcs asserts = &fw_info.fw_asserts_section; 4888316485Sdavidcs 4889316485Sdavidcs /* Dump FW Asserts section header and params */ 4890316485Sdavidcs storm_letter_str[0] = storm->letter; 4891316485Sdavidcs offset += ecore_dump_section_hdr(dump_buf + offset, dump, "fw_asserts", 2); 4892316485Sdavidcs offset += ecore_dump_str_param(dump_buf + offset, dump, "storm", storm_letter_str); 4893316485Sdavidcs offset += ecore_dump_num_param(dump_buf + offset, dump, "size", asserts->list_element_dword_size); 4894316485Sdavidcs 4895316485Sdavidcs /* Read and dump FW Asserts data */ 4896316485Sdavidcs if (!dump) { 4897316485Sdavidcs offset += asserts->list_element_dword_size; 4898316485Sdavidcs continue; 4899316485Sdavidcs } 4900316485Sdavidcs 4901316485Sdavidcs fw_asserts_section_addr = storm->sem_fast_mem_addr + SEM_FAST_REG_INT_RAM + 4902316485Sdavidcs RAM_LINES_TO_BYTES(asserts->section_ram_line_offset); 4903316485Sdavidcs next_list_idx_addr = fw_asserts_section_addr + DWORDS_TO_BYTES(asserts->list_next_index_dword_offset); 4904316485Sdavidcs next_list_idx = ecore_rd(p_hwfn, p_ptt, next_list_idx_addr); 4905316485Sdavidcs last_list_idx = (next_list_idx > 0 ? next_list_idx : asserts->list_num_elements) - 1; 4906316485Sdavidcs addr = BYTES_TO_DWORDS(fw_asserts_section_addr) + asserts->list_dword_offset + 4907316485Sdavidcs last_list_idx * asserts->list_element_dword_size; 4908316485Sdavidcs offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, dump, addr, asserts->list_element_dword_size, false); 4909316485Sdavidcs } 4910316485Sdavidcs 4911316485Sdavidcs /* Dump last section */ 4912320162Sdavidcs offset += ecore_dump_last_section(dump_buf, offset, dump); 4913316485Sdavidcs 4914316485Sdavidcs return offset; 4915316485Sdavidcs} 4916316485Sdavidcs 4917316485Sdavidcs/***************************** Public Functions *******************************/ 4918316485Sdavidcs 4919316485Sdavidcsenum dbg_status ecore_dbg_set_bin_ptr(const u8 * const bin_ptr) 4920316485Sdavidcs{ 4921337519Sdavidcs struct bin_buffer_hdr *buf_array = (struct bin_buffer_hdr *)bin_ptr; 4922316485Sdavidcs u8 buf_id; 4923316485Sdavidcs 4924316485Sdavidcs /* convert binary data to debug arrays */ 4925316485Sdavidcs for (buf_id = 0; buf_id < MAX_BIN_DBG_BUFFER_TYPE; buf_id++) { 4926337519Sdavidcs s_dbg_arrays[buf_id].ptr = (u32 *)(bin_ptr + buf_array[buf_id].offset); 4927316485Sdavidcs s_dbg_arrays[buf_id].size_in_dwords = BYTES_TO_DWORDS(buf_array[buf_id].length); 4928316485Sdavidcs } 4929316485Sdavidcs 4930316485Sdavidcs return DBG_STATUS_OK; 4931316485Sdavidcs} 4932316485Sdavidcs 4933316485Sdavidcsenum dbg_status ecore_dbg_set_app_ver(u32 ver) 4934316485Sdavidcs{ 4935316485Sdavidcs if (ver < TOOLS_VERSION) 4936316485Sdavidcs return DBG_STATUS_UNSUPPORTED_APP_VERSION; 4937316485Sdavidcs 4938316485Sdavidcs s_app_ver = ver; 4939316485Sdavidcs 4940316485Sdavidcs return DBG_STATUS_OK; 4941316485Sdavidcs} 4942316485Sdavidcs 4943316485Sdavidcsu32 ecore_dbg_get_fw_func_ver(void) 4944316485Sdavidcs{ 4945316485Sdavidcs return TOOLS_VERSION; 4946316485Sdavidcs} 4947316485Sdavidcs 4948316485Sdavidcsenum chip_ids ecore_dbg_get_chip_id(struct ecore_hwfn *p_hwfn) 4949316485Sdavidcs{ 4950316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 4951316485Sdavidcs 4952316485Sdavidcs return (enum chip_ids)dev_data->chip_id; 4953316485Sdavidcs} 4954316485Sdavidcs 4955316485Sdavidcsenum dbg_status ecore_dbg_bus_reset(struct ecore_hwfn *p_hwfn, 4956316485Sdavidcs struct ecore_ptt *p_ptt, 4957316485Sdavidcs bool one_shot_en, 4958316485Sdavidcs u8 force_hw_dwords, 4959316485Sdavidcs bool unify_inputs, 4960316485Sdavidcs bool grc_input_en) 4961316485Sdavidcs{ 4962316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 4963316485Sdavidcs enum dbg_status status; 4964337519Sdavidcs 4965316485Sdavidcs status = ecore_dbg_dev_init(p_hwfn, p_ptt); 4966316485Sdavidcs if (status != DBG_STATUS_OK) 4967316485Sdavidcs return status; 4968316485Sdavidcs 4969316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_reset: one_shot_en = %d, force_hw_dwords = %d, unify_inputs = %d, grc_input_en = %d\n", one_shot_en, force_hw_dwords, unify_inputs, grc_input_en); 4970316485Sdavidcs 4971316485Sdavidcs if (force_hw_dwords && 4972316485Sdavidcs force_hw_dwords != 4 && 4973316485Sdavidcs force_hw_dwords != 8) 4974316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 4975316485Sdavidcs 4976316485Sdavidcs if (ecore_rd(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON)) 4977316485Sdavidcs return DBG_STATUS_DBG_BUS_IN_USE; 4978316485Sdavidcs 4979316485Sdavidcs /* Update reset state of all blocks */ 4980316485Sdavidcs ecore_update_blocks_reset_state(p_hwfn, p_ptt); 4981316485Sdavidcs 4982316485Sdavidcs /* Disable all debug inputs */ 4983316485Sdavidcs status = ecore_bus_disable_inputs(p_hwfn, p_ptt, false); 4984316485Sdavidcs if (status != DBG_STATUS_OK) 4985316485Sdavidcs return status; 4986316485Sdavidcs 4987316485Sdavidcs /* Reset DBG block */ 4988316485Sdavidcs ecore_bus_reset_dbg_block(p_hwfn, p_ptt); 4989316485Sdavidcs 4990316485Sdavidcs /* Set one-shot / wrap-around */ 4991316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_FULL_MODE, one_shot_en ? 0 : 1); 4992316485Sdavidcs 4993316485Sdavidcs /* Init state params */ 4994316485Sdavidcs OSAL_MEMSET(&dev_data->bus, 0, sizeof(dev_data->bus)); 4995316485Sdavidcs dev_data->bus.target = DBG_BUS_TARGET_ID_INT_BUF; 4996316485Sdavidcs dev_data->bus.state = DBG_BUS_STATE_READY; 4997316485Sdavidcs dev_data->bus.one_shot_en = one_shot_en; 4998316485Sdavidcs dev_data->bus.hw_dwords = force_hw_dwords; 4999316485Sdavidcs dev_data->bus.grc_input_en = grc_input_en; 5000316485Sdavidcs dev_data->bus.unify_inputs = unify_inputs; 5001316485Sdavidcs dev_data->bus.num_enabled_blocks = grc_input_en ? 1 : 0; 5002316485Sdavidcs 5003316485Sdavidcs /* Init special DBG block */ 5004316485Sdavidcs if (grc_input_en) 5005316485Sdavidcs SET_FIELD(dev_data->bus.blocks[BLOCK_DBG].data, DBG_BUS_BLOCK_DATA_ENABLE_MASK, 0x1); 5006316485Sdavidcs 5007316485Sdavidcs return DBG_STATUS_OK; 5008316485Sdavidcs} 5009316485Sdavidcs 5010316485Sdavidcsenum dbg_status ecore_dbg_bus_set_pci_output(struct ecore_hwfn *p_hwfn, 5011316485Sdavidcs struct ecore_ptt *p_ptt, 5012316485Sdavidcs u16 buf_size_kb) 5013316485Sdavidcs{ 5014316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5015316485Sdavidcs dma_addr_t pci_buf_phys_addr; 5016316485Sdavidcs void *pci_buf; 5017316485Sdavidcs 5018316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_set_pci_output: buf_size_kb = %d\n", buf_size_kb); 5019316485Sdavidcs 5020316485Sdavidcs if (dev_data->bus.target != DBG_BUS_TARGET_ID_INT_BUF) 5021316485Sdavidcs return DBG_STATUS_OUTPUT_ALREADY_SET; 5022316485Sdavidcs if (dev_data->bus.state != DBG_BUS_STATE_READY || dev_data->bus.pci_buf.size > 0) 5023316485Sdavidcs return DBG_STATUS_DBG_BLOCK_NOT_RESET; 5024316485Sdavidcs 5025316485Sdavidcs dev_data->bus.target = DBG_BUS_TARGET_ID_PCI; 5026316485Sdavidcs dev_data->bus.pci_buf.size = buf_size_kb * 1024; 5027316485Sdavidcs if (dev_data->bus.pci_buf.size % PCI_PKT_SIZE_IN_BYTES) 5028316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5029316485Sdavidcs 5030316485Sdavidcs pci_buf = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, &pci_buf_phys_addr, dev_data->bus.pci_buf.size); 5031316485Sdavidcs if (!pci_buf) 5032316485Sdavidcs return DBG_STATUS_PCI_BUF_ALLOC_FAILED; 5033316485Sdavidcs 5034316485Sdavidcs OSAL_MEMCPY(&dev_data->bus.pci_buf.phys_addr, &pci_buf_phys_addr, sizeof(pci_buf_phys_addr)); 5035316485Sdavidcs 5036316485Sdavidcs dev_data->bus.pci_buf.virt_addr.lo = (u32)((u64)(osal_uintptr_t)pci_buf); 5037316485Sdavidcs dev_data->bus.pci_buf.virt_addr.hi = (u32)((u64)(osal_uintptr_t)pci_buf >> 32); 5038316485Sdavidcs 5039316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_LSB, dev_data->bus.pci_buf.phys_addr.lo); 5040316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_MSB, dev_data->bus.pci_buf.phys_addr.hi); 5041316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_TARGET_PACKET_SIZE, PCI_PKT_SIZE_IN_CHUNKS); 5042316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_PCI_EXT_BUFFER_SIZE, dev_data->bus.pci_buf.size / PCI_PKT_SIZE_IN_BYTES); 5043316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_PCI_FUNC_NUM, OPAQUE_FID(p_hwfn->rel_pf_id)); 5044316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_PCI_LOGIC_ADDR, PCI_PHYS_ADDR_TYPE); 5045316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_PCI_REQ_CREDIT, PCI_REQ_CREDIT); 5046316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_DEBUG_TARGET, DBG_BUS_TARGET_ID_PCI); 5047316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_OUTPUT_ENABLE, TARGET_EN_MASK_PCI); 5048316485Sdavidcs 5049316485Sdavidcs return DBG_STATUS_OK; 5050316485Sdavidcs} 5051316485Sdavidcs 5052316485Sdavidcsenum dbg_status ecore_dbg_bus_set_nw_output(struct ecore_hwfn *p_hwfn, 5053316485Sdavidcs struct ecore_ptt *p_ptt, 5054316485Sdavidcs u8 port_id, 5055316485Sdavidcs u32 dest_addr_lo32, 5056316485Sdavidcs u16 dest_addr_hi16, 5057316485Sdavidcs u16 data_limit_size_kb, 5058316485Sdavidcs bool send_to_other_engine, 5059316485Sdavidcs bool rcv_from_other_engine) 5060316485Sdavidcs{ 5061316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5062316485Sdavidcs 5063316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_set_nw_output: port_id = %d, dest_addr_lo32 = 0x%x, dest_addr_hi16 = 0x%x, data_limit_size_kb = %d, send_to_other_engine = %d, rcv_from_other_engine = %d\n", port_id, dest_addr_lo32, dest_addr_hi16, data_limit_size_kb, send_to_other_engine, rcv_from_other_engine); 5064316485Sdavidcs 5065316485Sdavidcs if (dev_data->bus.target != DBG_BUS_TARGET_ID_INT_BUF) 5066316485Sdavidcs return DBG_STATUS_OUTPUT_ALREADY_SET; 5067316485Sdavidcs if (dev_data->bus.state != DBG_BUS_STATE_READY) 5068316485Sdavidcs return DBG_STATUS_DBG_BLOCK_NOT_RESET; 5069316485Sdavidcs if (port_id >= s_chip_defs[dev_data->chip_id].per_platform[dev_data->platform_id].num_ports || (send_to_other_engine && rcv_from_other_engine)) 5070316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5071316485Sdavidcs 5072316485Sdavidcs dev_data->bus.target = DBG_BUS_TARGET_ID_NIG; 5073316485Sdavidcs dev_data->bus.rcv_from_other_engine = rcv_from_other_engine; 5074316485Sdavidcs 5075316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_OUTPUT_ENABLE, TARGET_EN_MASK_NIG); 5076316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_DEBUG_TARGET, DBG_BUS_TARGET_ID_NIG); 5077316485Sdavidcs 5078316485Sdavidcs if (send_to_other_engine) 5079316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_OTHER_ENGINE_MODE_BB_K2, DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX); 5080316485Sdavidcs else 5081316485Sdavidcs ecore_wr(p_hwfn, p_ptt, NIG_REG_DEBUG_PORT, port_id); 5082316485Sdavidcs 5083316485Sdavidcs if (rcv_from_other_engine) { 5084316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_OTHER_ENGINE_MODE_BB_K2, DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX); 5085316485Sdavidcs } 5086316485Sdavidcs else { 5087316485Sdavidcs 5088316485Sdavidcs /* Configure ethernet header of 14 bytes */ 5089316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_ETHERNET_HDR_WIDTH, 0); 5090316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_ETHERNET_HDR_7, dest_addr_lo32); 5091316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_ETHERNET_HDR_6, (u32)SRC_MAC_ADDR_LO16 | ((u32)dest_addr_hi16 << 16)); 5092316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_ETHERNET_HDR_5, SRC_MAC_ADDR_HI32); 5093316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_ETHERNET_HDR_4, (u32)ETH_TYPE << 16); 5094316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_TARGET_PACKET_SIZE, NIG_PKT_SIZE_IN_CHUNKS); 5095316485Sdavidcs if (data_limit_size_kb) 5096316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_NIG_DATA_LIMIT_SIZE, (data_limit_size_kb * 1024) / CHUNK_SIZE_IN_BYTES); 5097316485Sdavidcs } 5098316485Sdavidcs 5099316485Sdavidcs return DBG_STATUS_OK; 5100316485Sdavidcs} 5101316485Sdavidcs 5102316485Sdavidcsstatic bool ecore_is_overlapping_enable_mask(struct ecore_hwfn *p_hwfn, 5103316485Sdavidcs u8 enable_mask, 5104316485Sdavidcs u8 right_shift) 5105316485Sdavidcs{ 5106316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5107316485Sdavidcs u8 curr_shifted_enable_mask, shifted_enable_mask; 5108316485Sdavidcs u32 block_id; 5109316485Sdavidcs 5110316485Sdavidcs shifted_enable_mask = SHR(enable_mask, VALUES_PER_CYCLE, right_shift); 5111316485Sdavidcs 5112316485Sdavidcs if (dev_data->bus.num_enabled_blocks) { 5113316485Sdavidcs for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 5114316485Sdavidcs struct dbg_bus_block_data *block_bus = &dev_data->bus.blocks[block_id]; 5115316485Sdavidcs 5116316485Sdavidcs if (!GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_ENABLE_MASK)) 5117316485Sdavidcs continue; 5118316485Sdavidcs 5119316485Sdavidcs curr_shifted_enable_mask = 5120316485Sdavidcs SHR(GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_ENABLE_MASK), 5121316485Sdavidcs VALUES_PER_CYCLE, 5122316485Sdavidcs GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_RIGHT_SHIFT)); 5123316485Sdavidcs if (shifted_enable_mask & curr_shifted_enable_mask) 5124316485Sdavidcs return true; 5125316485Sdavidcs } 5126316485Sdavidcs } 5127316485Sdavidcs 5128316485Sdavidcs return false; 5129316485Sdavidcs} 5130316485Sdavidcs 5131316485Sdavidcsenum dbg_status ecore_dbg_bus_enable_block(struct ecore_hwfn *p_hwfn, 5132337519Sdavidcs enum block_id block_id, 5133337519Sdavidcs u8 line_num, 5134337519Sdavidcs u8 enable_mask, 5135337519Sdavidcs u8 right_shift, 5136337519Sdavidcs u8 force_valid_mask, 5137337519Sdavidcs u8 force_frame_mask) 5138316485Sdavidcs{ 5139316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5140316485Sdavidcs struct block_defs *block = s_block_defs[block_id]; 5141316485Sdavidcs struct dbg_bus_block_data *block_bus; 5142316485Sdavidcs struct dbg_bus_block *block_desc; 5143316485Sdavidcs 5144316485Sdavidcs block_bus = &dev_data->bus.blocks[block_id]; 5145316485Sdavidcs block_desc = get_dbg_bus_block_desc(p_hwfn, block_id); 5146316485Sdavidcs 5147316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_enable_block: block = %d, line_num = %d, enable_mask = 0x%x, right_shift = %d, force_valid_mask = 0x%x, force_frame_mask = 0x%x\n", block_id, line_num, enable_mask, right_shift, force_valid_mask, force_frame_mask); 5148316485Sdavidcs 5149316485Sdavidcs if (dev_data->bus.state != DBG_BUS_STATE_READY) 5150316485Sdavidcs return DBG_STATUS_DBG_BLOCK_NOT_RESET; 5151316485Sdavidcs if (block_id >= MAX_BLOCK_ID) 5152316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5153316485Sdavidcs if (GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_ENABLE_MASK)) 5154316485Sdavidcs return DBG_STATUS_BLOCK_ALREADY_ENABLED; 5155320162Sdavidcs if (block->dbg_client_id[dev_data->chip_id] == MAX_DBG_BUS_CLIENTS || 5156316485Sdavidcs line_num >= NUM_DBG_LINES(block_desc) || 5157316485Sdavidcs !enable_mask || 5158316485Sdavidcs enable_mask > MAX_CYCLE_VALUES_MASK || 5159316485Sdavidcs force_valid_mask > MAX_CYCLE_VALUES_MASK || 5160316485Sdavidcs force_frame_mask > MAX_CYCLE_VALUES_MASK || 5161316485Sdavidcs right_shift > VALUES_PER_CYCLE - 1) 5162316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5163316485Sdavidcs if (dev_data->block_in_reset[block_id]) 5164316485Sdavidcs return DBG_STATUS_BLOCK_IN_RESET; 5165316485Sdavidcs if (!dev_data->bus.unify_inputs && ecore_is_overlapping_enable_mask(p_hwfn, enable_mask, right_shift)) 5166316485Sdavidcs return DBG_STATUS_INPUT_OVERLAP; 5167316485Sdavidcs 5168316485Sdavidcs dev_data->bus.blocks[block_id].line_num = line_num; 5169316485Sdavidcs SET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_ENABLE_MASK, enable_mask); 5170316485Sdavidcs SET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_RIGHT_SHIFT, right_shift); 5171316485Sdavidcs SET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK, force_valid_mask); 5172316485Sdavidcs SET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK, force_frame_mask); 5173316485Sdavidcs 5174316485Sdavidcs dev_data->bus.num_enabled_blocks++; 5175316485Sdavidcs 5176316485Sdavidcs return DBG_STATUS_OK; 5177316485Sdavidcs} 5178316485Sdavidcs 5179316485Sdavidcsenum dbg_status ecore_dbg_bus_enable_storm(struct ecore_hwfn *p_hwfn, 5180337519Sdavidcs enum dbg_storms storm_id, 5181316485Sdavidcs enum dbg_bus_storm_modes storm_mode) 5182316485Sdavidcs{ 5183316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5184337519Sdavidcs struct dbg_bus_data *bus = &dev_data->bus; 5185337519Sdavidcs struct dbg_bus_storm_data *storm_bus; 5186337519Sdavidcs struct storm_defs *storm; 5187316485Sdavidcs 5188337519Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_enable_storm: storm = %d, storm_mode = %d\n", storm_id, storm_mode); 5189316485Sdavidcs 5190337519Sdavidcs if (bus->state != DBG_BUS_STATE_READY) 5191316485Sdavidcs return DBG_STATUS_DBG_BLOCK_NOT_RESET; 5192337519Sdavidcs if (bus->hw_dwords >= 4) 5193316485Sdavidcs return DBG_STATUS_HW_ONLY_RECORDING; 5194337519Sdavidcs if (storm_id >= MAX_DBG_STORMS) 5195316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5196316485Sdavidcs if (storm_mode >= MAX_DBG_BUS_STORM_MODES) 5197316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5198337519Sdavidcs if (bus->unify_inputs) 5199316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5200337519Sdavidcs if (bus->storms[storm_id].enabled) 5201316485Sdavidcs return DBG_STATUS_STORM_ALREADY_ENABLED; 5202316485Sdavidcs 5203337519Sdavidcs storm = &s_storm_defs[storm_id]; 5204337519Sdavidcs storm_bus = &bus->storms[storm_id]; 5205316485Sdavidcs 5206337519Sdavidcs if (dev_data->block_in_reset[storm->block_id]) 5207337519Sdavidcs return DBG_STATUS_BLOCK_IN_RESET; 5208316485Sdavidcs 5209337519Sdavidcs storm_bus->enabled = true; 5210337519Sdavidcs storm_bus->mode = (u8)storm_mode; 5211337519Sdavidcs storm_bus->hw_id = bus->num_enabled_storms; 5212337519Sdavidcs 5213337519Sdavidcs bus->num_enabled_storms++; 5214337519Sdavidcs 5215316485Sdavidcs return DBG_STATUS_OK; 5216316485Sdavidcs} 5217316485Sdavidcs 5218316485Sdavidcsenum dbg_status ecore_dbg_bus_enable_timestamp(struct ecore_hwfn *p_hwfn, 5219316485Sdavidcs struct ecore_ptt *p_ptt, 5220316485Sdavidcs u8 valid_mask, 5221316485Sdavidcs u8 frame_mask, 5222316485Sdavidcs u32 tick_len) 5223316485Sdavidcs{ 5224316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5225316485Sdavidcs 5226316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_enable_timestamp: valid_mask = 0x%x, frame_mask = 0x%x, tick_len = %d\n", valid_mask, frame_mask, tick_len); 5227316485Sdavidcs 5228316485Sdavidcs if (dev_data->bus.state != DBG_BUS_STATE_READY) 5229316485Sdavidcs return DBG_STATUS_DBG_BLOCK_NOT_RESET; 5230316485Sdavidcs if (valid_mask > 0x7 || frame_mask > 0x7) 5231316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5232316485Sdavidcs if (!dev_data->bus.unify_inputs && ecore_is_overlapping_enable_mask(p_hwfn, 0x1, 0)) 5233316485Sdavidcs return DBG_STATUS_INPUT_OVERLAP; 5234316485Sdavidcs 5235316485Sdavidcs dev_data->bus.timestamp_input_en = true; 5236316485Sdavidcs dev_data->bus.num_enabled_blocks++; 5237316485Sdavidcs 5238316485Sdavidcs SET_FIELD(dev_data->bus.blocks[BLOCK_DBG].data, DBG_BUS_BLOCK_DATA_ENABLE_MASK, 0x1); 5239316485Sdavidcs 5240316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_TIMESTAMP_VALID_EN, valid_mask); 5241316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_TIMESTAMP_FRAME_EN, frame_mask); 5242316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_TIMESTAMP_TICK, tick_len); 5243316485Sdavidcs 5244316485Sdavidcs return DBG_STATUS_OK; 5245316485Sdavidcs} 5246316485Sdavidcs 5247316485Sdavidcsenum dbg_status ecore_dbg_bus_add_eid_range_sem_filter(struct ecore_hwfn *p_hwfn, 5248316485Sdavidcs enum dbg_storms storm_id, 5249316485Sdavidcs u8 min_eid, 5250316485Sdavidcs u8 max_eid) 5251316485Sdavidcs{ 5252316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5253316485Sdavidcs struct dbg_bus_storm_data *storm_bus; 5254316485Sdavidcs 5255316485Sdavidcs storm_bus = &dev_data->bus.storms[storm_id]; 5256316485Sdavidcs 5257316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_add_eid_range_sem_filter: storm = %d, min_eid = 0x%x, max_eid = 0x%x\n", storm_id, min_eid, max_eid); 5258316485Sdavidcs 5259316485Sdavidcs if (storm_id >= MAX_DBG_STORMS) 5260316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5261316485Sdavidcs if (min_eid > max_eid) 5262316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5263316485Sdavidcs if (!storm_bus->enabled) 5264316485Sdavidcs return DBG_STATUS_STORM_NOT_ENABLED; 5265316485Sdavidcs 5266316485Sdavidcs storm_bus->eid_filter_en = 1; 5267316485Sdavidcs storm_bus->eid_range_not_mask = 1; 5268316485Sdavidcs storm_bus->eid_filter_params.range.min = min_eid; 5269316485Sdavidcs storm_bus->eid_filter_params.range.max = max_eid; 5270316485Sdavidcs 5271316485Sdavidcs return DBG_STATUS_OK; 5272316485Sdavidcs} 5273316485Sdavidcs 5274316485Sdavidcsenum dbg_status ecore_dbg_bus_add_eid_mask_sem_filter(struct ecore_hwfn *p_hwfn, 5275316485Sdavidcs enum dbg_storms storm_id, 5276316485Sdavidcs u8 eid_val, 5277316485Sdavidcs u8 eid_mask) 5278316485Sdavidcs{ 5279316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5280316485Sdavidcs struct dbg_bus_storm_data *storm_bus; 5281316485Sdavidcs 5282316485Sdavidcs storm_bus = &dev_data->bus.storms[storm_id]; 5283316485Sdavidcs 5284316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_add_eid_mask_sem_filter: storm = %d, eid_val = 0x%x, eid_mask = 0x%x\n", storm_id, eid_val, eid_mask); 5285316485Sdavidcs 5286316485Sdavidcs if (storm_id >= MAX_DBG_STORMS) 5287316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5288316485Sdavidcs if (!storm_bus->enabled) 5289316485Sdavidcs return DBG_STATUS_STORM_NOT_ENABLED; 5290316485Sdavidcs 5291316485Sdavidcs storm_bus->eid_filter_en = 1; 5292316485Sdavidcs storm_bus->eid_range_not_mask = 0; 5293316485Sdavidcs storm_bus->eid_filter_params.mask.val = eid_val; 5294316485Sdavidcs storm_bus->eid_filter_params.mask.mask = eid_mask; 5295316485Sdavidcs 5296316485Sdavidcs return DBG_STATUS_OK; 5297316485Sdavidcs} 5298316485Sdavidcs 5299316485Sdavidcsenum dbg_status ecore_dbg_bus_add_cid_sem_filter(struct ecore_hwfn *p_hwfn, 5300316485Sdavidcs enum dbg_storms storm_id, 5301316485Sdavidcs u32 cid) 5302316485Sdavidcs{ 5303316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5304316485Sdavidcs struct dbg_bus_storm_data *storm_bus; 5305316485Sdavidcs 5306316485Sdavidcs storm_bus = &dev_data->bus.storms[storm_id]; 5307316485Sdavidcs 5308316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_add_cid_sem_filter: storm = %d, cid = 0x%x\n", storm_id, cid); 5309316485Sdavidcs 5310316485Sdavidcs if (storm_id >= MAX_DBG_STORMS) 5311316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5312316485Sdavidcs if (!storm_bus->enabled) 5313316485Sdavidcs return DBG_STATUS_STORM_NOT_ENABLED; 5314316485Sdavidcs 5315316485Sdavidcs storm_bus->cid_filter_en = 1; 5316316485Sdavidcs storm_bus->cid = cid; 5317316485Sdavidcs 5318316485Sdavidcs return DBG_STATUS_OK; 5319316485Sdavidcs} 5320316485Sdavidcs 5321316485Sdavidcsenum dbg_status ecore_dbg_bus_enable_filter(struct ecore_hwfn *p_hwfn, 5322316485Sdavidcs struct ecore_ptt *p_ptt, 5323316485Sdavidcs enum block_id block_id, 5324316485Sdavidcs u8 const_msg_len) 5325316485Sdavidcs{ 5326316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5327316485Sdavidcs 5328316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_enable_filter: block = %d, const_msg_len = %d\n", block_id, const_msg_len); 5329316485Sdavidcs 5330316485Sdavidcs if (dev_data->bus.state != DBG_BUS_STATE_READY) 5331316485Sdavidcs return DBG_STATUS_DBG_BLOCK_NOT_RESET; 5332316485Sdavidcs if (dev_data->bus.filter_en) 5333316485Sdavidcs return DBG_STATUS_FILTER_ALREADY_ENABLED; 5334316485Sdavidcs if (block_id >= MAX_BLOCK_ID) 5335316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5336316485Sdavidcs if (!GET_FIELD(dev_data->bus.blocks[block_id].data, DBG_BUS_BLOCK_DATA_ENABLE_MASK)) 5337316485Sdavidcs return DBG_STATUS_BLOCK_NOT_ENABLED; 5338316485Sdavidcs if (!dev_data->bus.unify_inputs) 5339316485Sdavidcs return DBG_STATUS_FILTER_BUG; 5340316485Sdavidcs 5341316485Sdavidcs dev_data->bus.filter_en = true; 5342316485Sdavidcs dev_data->bus.next_constraint_id = 0; 5343316485Sdavidcs dev_data->bus.adding_filter = true; 5344316485Sdavidcs 5345316485Sdavidcs /* HW ID is set to 0 due to required unifyInputs */ 5346337519Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_FILTER_ID_NUM, 0); 5347316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_FILTER_MSG_LENGTH_ENABLE, const_msg_len > 0 ? 1 : 0); 5348316485Sdavidcs if (const_msg_len > 0) 5349316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_FILTER_MSG_LENGTH, const_msg_len - 1); 5350316485Sdavidcs 5351316485Sdavidcs return DBG_STATUS_OK; 5352316485Sdavidcs} 5353316485Sdavidcs 5354316485Sdavidcsenum dbg_status ecore_dbg_bus_enable_trigger(struct ecore_hwfn *p_hwfn, 5355316485Sdavidcs struct ecore_ptt *p_ptt, 5356316485Sdavidcs bool rec_pre_trigger, 5357316485Sdavidcs u8 pre_chunks, 5358316485Sdavidcs bool rec_post_trigger, 5359316485Sdavidcs u32 post_cycles, 5360316485Sdavidcs bool filter_pre_trigger, 5361316485Sdavidcs bool filter_post_trigger) 5362316485Sdavidcs{ 5363316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5364316485Sdavidcs enum dbg_bus_post_trigger_types post_trigger_type; 5365316485Sdavidcs enum dbg_bus_pre_trigger_types pre_trigger_type; 5366316485Sdavidcs struct dbg_bus_data *bus = &dev_data->bus; 5367316485Sdavidcs 5368316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_enable_trigger: rec_pre_trigger = %d, pre_chunks = %d, rec_post_trigger = %d, post_cycles = %d, filter_pre_trigger = %d, filter_post_trigger = %d\n", rec_pre_trigger, pre_chunks, rec_post_trigger, post_cycles, filter_pre_trigger, filter_post_trigger); 5369316485Sdavidcs 5370316485Sdavidcs if (bus->state != DBG_BUS_STATE_READY) 5371316485Sdavidcs return DBG_STATUS_DBG_BLOCK_NOT_RESET; 5372316485Sdavidcs if (bus->trigger_en) 5373316485Sdavidcs return DBG_STATUS_TRIGGER_ALREADY_ENABLED; 5374316485Sdavidcs if (rec_pre_trigger && pre_chunks >= INT_BUF_SIZE_IN_CHUNKS) 5375316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5376316485Sdavidcs 5377316485Sdavidcs bus->trigger_en = true; 5378316485Sdavidcs bus->filter_pre_trigger = filter_pre_trigger; 5379316485Sdavidcs bus->filter_post_trigger = filter_post_trigger; 5380316485Sdavidcs 5381316485Sdavidcs if (rec_pre_trigger) { 5382316485Sdavidcs pre_trigger_type = pre_chunks ? DBG_BUS_PRE_TRIGGER_NUM_CHUNKS : DBG_BUS_PRE_TRIGGER_START_FROM_ZERO; 5383316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_RCRD_ON_WINDOW_PRE_NUM_CHUNKS, pre_chunks); 5384316485Sdavidcs } 5385316485Sdavidcs else { 5386316485Sdavidcs pre_trigger_type = DBG_BUS_PRE_TRIGGER_DROP; 5387316485Sdavidcs } 5388316485Sdavidcs 5389316485Sdavidcs if (rec_post_trigger) { 5390316485Sdavidcs post_trigger_type = DBG_BUS_POST_TRIGGER_RECORD; 5391316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_RCRD_ON_WINDOW_POST_NUM_CYCLES, post_cycles ? post_cycles : 0xffffffff); 5392316485Sdavidcs } 5393316485Sdavidcs else { 5394316485Sdavidcs post_trigger_type = DBG_BUS_POST_TRIGGER_DROP; 5395316485Sdavidcs } 5396316485Sdavidcs 5397316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_RCRD_ON_WINDOW_PRE_TRGR_EVNT_MODE, pre_trigger_type); 5398316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_RCRD_ON_WINDOW_POST_TRGR_EVNT_MODE, post_trigger_type); 5399316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_TRIGGER_ENABLE, 1); 5400316485Sdavidcs 5401316485Sdavidcs return DBG_STATUS_OK; 5402316485Sdavidcs} 5403316485Sdavidcs 5404316485Sdavidcsenum dbg_status ecore_dbg_bus_add_trigger_state(struct ecore_hwfn *p_hwfn, 5405316485Sdavidcs struct ecore_ptt *p_ptt, 5406316485Sdavidcs enum block_id block_id, 5407316485Sdavidcs u8 const_msg_len, 5408316485Sdavidcs u16 count_to_next) 5409316485Sdavidcs{ 5410316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5411316485Sdavidcs struct dbg_bus_data *bus = &dev_data->bus; 5412316485Sdavidcs struct dbg_bus_block_data *block_bus; 5413316485Sdavidcs u8 reg_offset; 5414316485Sdavidcs 5415316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_add_trigger_state: block = %d, const_msg_len = %d, count_to_next = %d\n", block_id, const_msg_len, count_to_next); 5416316485Sdavidcs 5417316485Sdavidcs block_bus = &bus->blocks[block_id]; 5418316485Sdavidcs 5419316485Sdavidcs if (!bus->trigger_en) 5420316485Sdavidcs return DBG_STATUS_TRIGGER_NOT_ENABLED; 5421316485Sdavidcs if (bus->next_trigger_state == MAX_TRIGGER_STATES) 5422316485Sdavidcs return DBG_STATUS_TOO_MANY_TRIGGER_STATES; 5423316485Sdavidcs if (block_id >= MAX_BLOCK_ID) 5424316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5425316485Sdavidcs if (!GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_ENABLE_MASK)) 5426316485Sdavidcs return DBG_STATUS_BLOCK_NOT_ENABLED; 5427316485Sdavidcs if (!count_to_next) 5428316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5429316485Sdavidcs 5430316485Sdavidcs bus->next_constraint_id = 0; 5431316485Sdavidcs bus->adding_filter = false; 5432316485Sdavidcs 5433316485Sdavidcs /* Store block's shifted enable mask */ 5434316485Sdavidcs SET_FIELD(bus->trigger_states[dev_data->bus.next_trigger_state].data, DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK, SHR(GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_ENABLE_MASK), 5435316485Sdavidcs VALUES_PER_CYCLE, 5436316485Sdavidcs GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_RIGHT_SHIFT))); 5437316485Sdavidcs 5438316485Sdavidcs /* Set trigger state registers */ 5439316485Sdavidcs reg_offset = bus->next_trigger_state * BYTES_IN_DWORD; 5440316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_0 + reg_offset, const_msg_len > 0 ? 1 : 0); 5441316485Sdavidcs if (const_msg_len > 0) 5442316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_TRIGGER_STATE_MSG_LENGTH_0 + reg_offset, const_msg_len - 1); 5443316485Sdavidcs 5444316485Sdavidcs /* Set trigger set registers */ 5445316485Sdavidcs reg_offset = bus->next_trigger_state * TRIGGER_SETS_PER_STATE * BYTES_IN_DWORD; 5446316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_TRIGGER_STATE_SET_COUNT_0 + reg_offset, count_to_next); 5447316485Sdavidcs 5448316485Sdavidcs /* Set next state to final state, and overwrite previous next state 5449316485Sdavidcs * (if any). 5450316485Sdavidcs */ 5451316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_TRIGGER_STATE_SET_NXT_STATE_0 + reg_offset, MAX_TRIGGER_STATES); 5452316485Sdavidcs if (bus->next_trigger_state > 0) { 5453316485Sdavidcs reg_offset = (bus->next_trigger_state - 1) * TRIGGER_SETS_PER_STATE * BYTES_IN_DWORD; 5454316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_TRIGGER_STATE_SET_NXT_STATE_0 + reg_offset, bus->next_trigger_state); 5455316485Sdavidcs } 5456316485Sdavidcs 5457316485Sdavidcs bus->next_trigger_state++; 5458316485Sdavidcs 5459316485Sdavidcs return DBG_STATUS_OK; 5460316485Sdavidcs} 5461316485Sdavidcs 5462316485Sdavidcsenum dbg_status ecore_dbg_bus_add_constraint(struct ecore_hwfn *p_hwfn, 5463337519Sdavidcs struct ecore_ptt *p_ptt, 5464337519Sdavidcs enum dbg_bus_constraint_ops constraint_op, 5465337519Sdavidcs u32 data_val, 5466337519Sdavidcs u32 data_mask, 5467337519Sdavidcs bool compare_frame, 5468337519Sdavidcs u8 frame_bit, 5469337519Sdavidcs u8 cycle_offset, 5470337519Sdavidcs u8 dword_offset_in_cycle, 5471337519Sdavidcs bool is_mandatory) 5472316485Sdavidcs{ 5473316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5474316485Sdavidcs struct dbg_bus_data *bus = &dev_data->bus; 5475316485Sdavidcs u16 dword_offset, range = 0; 5476316485Sdavidcs 5477316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_add_constraint: op = %d, data_val = 0x%x, data_mask = 0x%x, compare_frame = %d, frame_bit = %d, cycle_offset = %d, dword_offset_in_cycle = %d, is_mandatory = %d\n", constraint_op, data_val, data_mask, compare_frame, frame_bit, cycle_offset, dword_offset_in_cycle, is_mandatory); 5478316485Sdavidcs 5479316485Sdavidcs if (!bus->filter_en && !dev_data->bus.trigger_en) 5480316485Sdavidcs return DBG_STATUS_CANT_ADD_CONSTRAINT; 5481316485Sdavidcs if (bus->trigger_en && !bus->adding_filter && !bus->next_trigger_state) 5482316485Sdavidcs return DBG_STATUS_CANT_ADD_CONSTRAINT; 5483316485Sdavidcs if (bus->next_constraint_id >= MAX_CONSTRAINTS) 5484316485Sdavidcs return DBG_STATUS_TOO_MANY_CONSTRAINTS; 5485316485Sdavidcs if (constraint_op >= MAX_DBG_BUS_CONSTRAINT_OPS || frame_bit > 1 || dword_offset_in_cycle > 3 || (bus->adding_filter && cycle_offset > 3)) 5486316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5487316485Sdavidcs if (compare_frame && 5488316485Sdavidcs constraint_op != DBG_BUS_CONSTRAINT_OP_EQ && 5489316485Sdavidcs constraint_op != DBG_BUS_CONSTRAINT_OP_NE) 5490316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5491316485Sdavidcs 5492316485Sdavidcs dword_offset = cycle_offset * VALUES_PER_CYCLE + dword_offset_in_cycle; 5493316485Sdavidcs 5494316485Sdavidcs if (!bus->adding_filter) { 5495316485Sdavidcs u8 curr_trigger_state_id = bus->next_trigger_state - 1; 5496316485Sdavidcs struct dbg_bus_trigger_state_data *trigger_state; 5497316485Sdavidcs 5498316485Sdavidcs trigger_state = &bus->trigger_states[curr_trigger_state_id]; 5499316485Sdavidcs 5500316485Sdavidcs /* Check if the selected dword is enabled in the block */ 5501316485Sdavidcs if (!(GET_FIELD(trigger_state->data, DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK) & (u8)(1 << dword_offset_in_cycle))) 5502316485Sdavidcs return DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET; 5503316485Sdavidcs 5504316485Sdavidcs /* Add selected dword to trigger state's dword mask */ 5505316485Sdavidcs SET_FIELD(trigger_state->data, DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK, GET_FIELD(trigger_state->data, DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK) | (u8)(1 << dword_offset_in_cycle)); 5506316485Sdavidcs } 5507316485Sdavidcs 5508316485Sdavidcs /* Prepare data mask and range */ 5509316485Sdavidcs if (constraint_op == DBG_BUS_CONSTRAINT_OP_EQ || 5510316485Sdavidcs constraint_op == DBG_BUS_CONSTRAINT_OP_NE) { 5511316485Sdavidcs data_mask = ~data_mask; 5512316485Sdavidcs } 5513316485Sdavidcs else { 5514316485Sdavidcs u8 lsb, width; 5515337519Sdavidcs 5516316485Sdavidcs /* Extract lsb and width from mask */ 5517316485Sdavidcs if (!data_mask) 5518316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 5519316485Sdavidcs 5520316485Sdavidcs for (lsb = 0; lsb < 32 && !(data_mask & 1); lsb++, data_mask >>= 1); 5521337519Sdavidcs for (width = 0; width < 32 - lsb && (data_mask & 1); width++, data_mask >>= 1); 5522337519Sdavidcs if (data_mask) 5523337519Sdavidcs return DBG_STATUS_INVALID_ARGS; 5524316485Sdavidcs range = (lsb << 5) | (width - 1); 5525316485Sdavidcs } 5526316485Sdavidcs 5527316485Sdavidcs /* Add constraint */ 5528316485Sdavidcs ecore_bus_set_constraint(p_hwfn, p_ptt, dev_data->bus.adding_filter ? 1 : 0, 5529316485Sdavidcs dev_data->bus.next_constraint_id, 5530316485Sdavidcs s_constraint_op_defs[constraint_op].hw_op_val, 5531316485Sdavidcs data_val, data_mask, frame_bit, 5532316485Sdavidcs compare_frame ? 0 : 1, dword_offset, range, 5533316485Sdavidcs s_constraint_op_defs[constraint_op].is_cyclic ? 1 : 0, 5534316485Sdavidcs is_mandatory ? 1 : 0); 5535316485Sdavidcs 5536316485Sdavidcs /* If first constraint, fill other 3 constraints with dummy constraints 5537316485Sdavidcs * that always match (using the same offset). 5538316485Sdavidcs */ 5539316485Sdavidcs if (!dev_data->bus.next_constraint_id) { 5540316485Sdavidcs u8 i; 5541316485Sdavidcs 5542316485Sdavidcs for (i = 1; i < MAX_CONSTRAINTS; i++) 5543316485Sdavidcs ecore_bus_set_constraint(p_hwfn, p_ptt, bus->adding_filter ? 1 : 0, 5544316485Sdavidcs i, DBG_BUS_CONSTRAINT_OP_EQ, 0, 0xffffffff, 5545316485Sdavidcs 0, 1, dword_offset, 0, 0, 1); 5546316485Sdavidcs } 5547316485Sdavidcs 5548316485Sdavidcs bus->next_constraint_id++; 5549316485Sdavidcs 5550316485Sdavidcs return DBG_STATUS_OK; 5551316485Sdavidcs} 5552316485Sdavidcs 5553316485Sdavidcs/* Configure the DBG block client mask */ 5554316485Sdavidcsstatic void ecore_config_dbg_block_client_mask(struct ecore_hwfn *p_hwfn, 5555316485Sdavidcs struct ecore_ptt *p_ptt) 5556316485Sdavidcs{ 5557316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5558316485Sdavidcs struct dbg_bus_data *bus = &dev_data->bus; 5559316485Sdavidcs u32 block_id, client_mask = 0; 5560316485Sdavidcs u8 storm_id; 5561316485Sdavidcs 5562316485Sdavidcs /* Update client mask for Storm inputs */ 5563316485Sdavidcs if (bus->num_enabled_storms) 5564316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 5565316485Sdavidcs struct storm_defs *storm = &s_storm_defs[storm_id]; 5566316485Sdavidcs 5567316485Sdavidcs if (bus->storms[storm_id].enabled) 5568316485Sdavidcs client_mask |= (1 << storm->dbg_client_id[dev_data->chip_id]); 5569316485Sdavidcs } 5570316485Sdavidcs 5571316485Sdavidcs /* Update client mask for block inputs */ 5572316485Sdavidcs if (bus->num_enabled_blocks) { 5573316485Sdavidcs for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 5574316485Sdavidcs struct dbg_bus_block_data *block_bus = &bus->blocks[block_id]; 5575316485Sdavidcs struct block_defs *block = s_block_defs[block_id]; 5576316485Sdavidcs 5577316485Sdavidcs if (GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_ENABLE_MASK) && block_id != BLOCK_DBG) 5578316485Sdavidcs client_mask |= (1 << block->dbg_client_id[dev_data->chip_id]); 5579316485Sdavidcs } 5580316485Sdavidcs } 5581316485Sdavidcs 5582316485Sdavidcs /* Update client mask for GRC input */ 5583316485Sdavidcs if (bus->grc_input_en) 5584316485Sdavidcs client_mask |= (1 << DBG_BUS_CLIENT_CPU); 5585316485Sdavidcs 5586316485Sdavidcs /* Update client mask for timestamp input */ 5587316485Sdavidcs if (bus->timestamp_input_en) 5588316485Sdavidcs client_mask |= (1 << DBG_BUS_CLIENT_TIMESTAMP); 5589316485Sdavidcs 5590316485Sdavidcs ecore_bus_enable_clients(p_hwfn, p_ptt, client_mask); 5591316485Sdavidcs} 5592316485Sdavidcs 5593316485Sdavidcs/* Configure the DBG block framing mode */ 5594316485Sdavidcsstatic enum dbg_status ecore_config_dbg_block_framing_mode(struct ecore_hwfn *p_hwfn, 5595316485Sdavidcs struct ecore_ptt *p_ptt) 5596316485Sdavidcs{ 5597316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5598316485Sdavidcs struct dbg_bus_data *bus = &dev_data->bus; 5599316485Sdavidcs enum dbg_bus_frame_modes dbg_framing_mode; 5600316485Sdavidcs u32 block_id; 5601316485Sdavidcs 5602316485Sdavidcs if (!bus->hw_dwords && bus->num_enabled_blocks) { 5603316485Sdavidcs struct dbg_bus_line *line_desc; 5604316485Sdavidcs u8 hw_dwords; 5605316485Sdavidcs 5606316485Sdavidcs /* Choose either 4 HW dwords (128-bit mode) or 8 HW dwords 5607316485Sdavidcs * (256-bit mode). 5608316485Sdavidcs */ 5609316485Sdavidcs for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 5610316485Sdavidcs struct dbg_bus_block_data *block_bus = &bus->blocks[block_id]; 5611316485Sdavidcs 5612316485Sdavidcs if (!GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_ENABLE_MASK)) 5613316485Sdavidcs continue; 5614316485Sdavidcs 5615316485Sdavidcs line_desc = get_dbg_bus_line_desc(p_hwfn, (enum block_id)block_id); 5616316485Sdavidcs hw_dwords = line_desc && GET_FIELD(line_desc->data, DBG_BUS_LINE_IS_256B) ? 8 : 4; 5617316485Sdavidcs 5618316485Sdavidcs if (bus->hw_dwords > 0 && bus->hw_dwords != hw_dwords) 5619316485Sdavidcs return DBG_STATUS_NON_MATCHING_LINES; 5620316485Sdavidcs 5621316485Sdavidcs /* The DBG block doesn't support triggers and 5622316485Sdavidcs * filters on 256b debug lines. 5623316485Sdavidcs */ 5624316485Sdavidcs if (hw_dwords == 8 && (bus->trigger_en || bus->filter_en)) 5625316485Sdavidcs return DBG_STATUS_NO_FILTER_TRIGGER_64B; 5626316485Sdavidcs 5627316485Sdavidcs bus->hw_dwords = hw_dwords; 5628316485Sdavidcs } 5629316485Sdavidcs } 5630316485Sdavidcs 5631316485Sdavidcs switch (bus->hw_dwords) { 5632316485Sdavidcs case 0: dbg_framing_mode = DBG_BUS_FRAME_MODE_0HW_4ST; break; 5633316485Sdavidcs case 4: dbg_framing_mode = DBG_BUS_FRAME_MODE_4HW_0ST; break; 5634316485Sdavidcs case 8: dbg_framing_mode = DBG_BUS_FRAME_MODE_8HW_0ST; break; 5635316485Sdavidcs default: dbg_framing_mode = DBG_BUS_FRAME_MODE_0HW_4ST; break; 5636316485Sdavidcs } 5637316485Sdavidcs ecore_bus_set_framing_mode(p_hwfn, p_ptt, dbg_framing_mode); 5638316485Sdavidcs 5639316485Sdavidcs return DBG_STATUS_OK; 5640316485Sdavidcs} 5641316485Sdavidcs 5642316485Sdavidcs/* Configure the DBG block Storm data */ 5643316485Sdavidcsstatic enum dbg_status ecore_config_storm_inputs(struct ecore_hwfn *p_hwfn, 5644316485Sdavidcs struct ecore_ptt *p_ptt) 5645316485Sdavidcs{ 5646316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5647316485Sdavidcs struct dbg_bus_data *bus = &dev_data->bus; 5648316485Sdavidcs u8 storm_id, i, next_storm_id = 0; 5649316485Sdavidcs u32 storm_id_mask = 0; 5650316485Sdavidcs 5651316485Sdavidcs /* Check if SEMI sync FIFO is empty */ 5652316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 5653316485Sdavidcs struct dbg_bus_storm_data *storm_bus = &bus->storms[storm_id]; 5654316485Sdavidcs struct storm_defs *storm = &s_storm_defs[storm_id]; 5655316485Sdavidcs 5656316485Sdavidcs if (storm_bus->enabled && !ecore_rd(p_hwfn, p_ptt, storm->sem_sync_dbg_empty_addr)) 5657316485Sdavidcs return DBG_STATUS_SEMI_FIFO_NOT_EMPTY; 5658316485Sdavidcs } 5659316485Sdavidcs 5660316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 5661316485Sdavidcs struct dbg_bus_storm_data *storm_bus = &bus->storms[storm_id]; 5662316485Sdavidcs 5663316485Sdavidcs if (storm_bus->enabled) 5664316485Sdavidcs storm_id_mask |= (storm_bus->hw_id << (storm_id * HW_ID_BITS)); 5665316485Sdavidcs } 5666316485Sdavidcs 5667316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_STORM_ID_NUM, storm_id_mask); 5668316485Sdavidcs 5669316485Sdavidcs /* Disable storm stall if recording to internal buffer in one-shot */ 5670316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_NO_GRANT_ON_FULL, (dev_data->bus.target == DBG_BUS_TARGET_ID_INT_BUF && bus->one_shot_en) ? 0 : 1); 5671316485Sdavidcs 5672316485Sdavidcs /* Configure calendar */ 5673316485Sdavidcs for (i = 0; i < NUM_CALENDAR_SLOTS; i++, next_storm_id = (next_storm_id + 1) % MAX_DBG_STORMS) { 5674316485Sdavidcs 5675316485Sdavidcs /* Find next enabled Storm */ 5676316485Sdavidcs for (; !dev_data->bus.storms[next_storm_id].enabled; next_storm_id = (next_storm_id + 1) % MAX_DBG_STORMS); 5677316485Sdavidcs 5678316485Sdavidcs /* Configure calendar slot */ 5679316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_CALENDAR_SLOT0 + DWORDS_TO_BYTES(i), next_storm_id); 5680316485Sdavidcs } 5681316485Sdavidcs 5682316485Sdavidcs return DBG_STATUS_OK; 5683316485Sdavidcs} 5684316485Sdavidcs 5685316485Sdavidcs/* Assign HW ID to each dword/qword: 5686316485Sdavidcs * if the inputs are unified, HW ID 0 is assigned to all dwords/qwords. 5687316485Sdavidcs * Otherwise, we would like to assign a different HW ID to each dword, to avoid 5688316485Sdavidcs * data synchronization issues. however, we need to check if there is a trigger 5689316485Sdavidcs * state for which more than one dword has a constraint. if there is, we cannot 5690316485Sdavidcs * assign a different HW ID to each dword (since a trigger state has a single 5691316485Sdavidcs * HW ID), so we assign a different HW ID to each block. 5692316485Sdavidcs */ 5693316485Sdavidcsstatic void ecore_assign_hw_ids(struct ecore_hwfn *p_hwfn, 5694316485Sdavidcs u8 hw_ids[VALUES_PER_CYCLE]) 5695316485Sdavidcs{ 5696316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5697316485Sdavidcs struct dbg_bus_data *bus = &dev_data->bus; 5698316485Sdavidcs bool hw_id_per_dword = true; 5699316485Sdavidcs u8 val_id, state_id; 5700316485Sdavidcs u32 block_id; 5701316485Sdavidcs 5702316485Sdavidcs OSAL_MEMSET(hw_ids, 0, VALUES_PER_CYCLE); 5703316485Sdavidcs 5704316485Sdavidcs if (bus->unify_inputs) 5705316485Sdavidcs return; 5706316485Sdavidcs 5707316485Sdavidcs if (bus->trigger_en) { 5708316485Sdavidcs for (state_id = 0; state_id < bus->next_trigger_state && hw_id_per_dword; state_id++) { 5709316485Sdavidcs u8 num_dwords = 0; 5710316485Sdavidcs 5711316485Sdavidcs for (val_id = 0; val_id < VALUES_PER_CYCLE; val_id++) 5712316485Sdavidcs if (GET_FIELD(bus->trigger_states[state_id].data, DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK) & (1 << val_id)) 5713316485Sdavidcs num_dwords++; 5714316485Sdavidcs 5715316485Sdavidcs if (num_dwords > 1) 5716316485Sdavidcs hw_id_per_dword = false; 5717316485Sdavidcs } 5718316485Sdavidcs } 5719316485Sdavidcs 5720316485Sdavidcs if (hw_id_per_dword) { 5721316485Sdavidcs 5722316485Sdavidcs /* Assign a different HW ID for each dword */ 5723316485Sdavidcs for (val_id = 0; val_id < VALUES_PER_CYCLE; val_id++) 5724316485Sdavidcs hw_ids[val_id] = val_id; 5725316485Sdavidcs } 5726316485Sdavidcs else { 5727316485Sdavidcs u8 shifted_enable_mask, next_hw_id = 0; 5728316485Sdavidcs 5729316485Sdavidcs /* Assign HW IDs according to blocks enable / */ 5730316485Sdavidcs for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 5731316485Sdavidcs struct dbg_bus_block_data *block_bus = &bus->blocks[block_id]; 5732316485Sdavidcs 5733316485Sdavidcs if (!GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_ENABLE_MASK)) 5734316485Sdavidcs continue; 5735316485Sdavidcs 5736316485Sdavidcs block_bus->hw_id = next_hw_id++; 5737316485Sdavidcs if (!block_bus->hw_id) 5738316485Sdavidcs continue; 5739316485Sdavidcs 5740316485Sdavidcs shifted_enable_mask = 5741316485Sdavidcs SHR(GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_ENABLE_MASK), 5742316485Sdavidcs VALUES_PER_CYCLE, 5743316485Sdavidcs GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_RIGHT_SHIFT)); 5744316485Sdavidcs 5745316485Sdavidcs for (val_id = 0; val_id < VALUES_PER_CYCLE; val_id++) 5746316485Sdavidcs if (shifted_enable_mask & (1 << val_id)) 5747316485Sdavidcs hw_ids[val_id] = block_bus->hw_id; 5748316485Sdavidcs } 5749316485Sdavidcs } 5750316485Sdavidcs} 5751316485Sdavidcs 5752316485Sdavidcs/* Configure the DBG block HW blocks data */ 5753316485Sdavidcsstatic void ecore_config_block_inputs(struct ecore_hwfn *p_hwfn, 5754316485Sdavidcs struct ecore_ptt *p_ptt) 5755316485Sdavidcs{ 5756316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5757316485Sdavidcs struct dbg_bus_data *bus = &dev_data->bus; 5758316485Sdavidcs u8 hw_ids[VALUES_PER_CYCLE]; 5759316485Sdavidcs u8 val_id, state_id; 5760316485Sdavidcs 5761316485Sdavidcs ecore_assign_hw_ids(p_hwfn, hw_ids); 5762316485Sdavidcs 5763316485Sdavidcs /* Assign a HW ID to each trigger state */ 5764316485Sdavidcs if (dev_data->bus.trigger_en) { 5765316485Sdavidcs for (state_id = 0; state_id < bus->next_trigger_state; state_id++) { 5766316485Sdavidcs for (val_id = 0; val_id < VALUES_PER_CYCLE; val_id++) { 5767316485Sdavidcs u8 state_data = bus->trigger_states[state_id].data; 5768316485Sdavidcs 5769316485Sdavidcs if (GET_FIELD(state_data, DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK) & (1 << val_id)) { 5770316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_TRIGGER_STATE_ID_0 + state_id * BYTES_IN_DWORD, hw_ids[val_id]); 5771316485Sdavidcs break; 5772316485Sdavidcs } 5773316485Sdavidcs } 5774316485Sdavidcs } 5775316485Sdavidcs } 5776316485Sdavidcs 5777316485Sdavidcs /* Configure HW ID mask */ 5778316485Sdavidcs dev_data->bus.hw_id_mask = 0; 5779316485Sdavidcs for (val_id = 0; val_id < VALUES_PER_CYCLE; val_id++) 5780316485Sdavidcs bus->hw_id_mask |= (hw_ids[val_id] << (val_id * HW_ID_BITS)); 5781316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_HW_ID_NUM, bus->hw_id_mask); 5782316485Sdavidcs 5783316485Sdavidcs /* Configure additional K2 PCIE registers */ 5784316485Sdavidcs if (dev_data->chip_id == CHIP_K2 && 5785316485Sdavidcs (GET_FIELD(bus->blocks[BLOCK_PCIE].data, DBG_BUS_BLOCK_DATA_ENABLE_MASK) || 5786316485Sdavidcs GET_FIELD(bus->blocks[BLOCK_PHY_PCIE].data, DBG_BUS_BLOCK_DATA_ENABLE_MASK))) { 5787316485Sdavidcs ecore_wr(p_hwfn, p_ptt, PCIE_REG_DBG_REPEAT_THRESHOLD_COUNT_K2_E5, 1); 5788316485Sdavidcs ecore_wr(p_hwfn, p_ptt, PCIE_REG_DBG_FW_TRIGGER_ENABLE_K2_E5, 1); 5789316485Sdavidcs } 5790316485Sdavidcs} 5791316485Sdavidcs 5792316485Sdavidcsenum dbg_status ecore_dbg_bus_start(struct ecore_hwfn *p_hwfn, 5793316485Sdavidcs struct ecore_ptt *p_ptt) 5794316485Sdavidcs{ 5795316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5796316485Sdavidcs struct dbg_bus_data *bus = &dev_data->bus; 5797316485Sdavidcs enum dbg_bus_filter_types filter_type; 5798316485Sdavidcs enum dbg_status status; 5799316485Sdavidcs u32 block_id; 5800316485Sdavidcs u8 storm_id; 5801316485Sdavidcs 5802316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_start\n"); 5803316485Sdavidcs 5804316485Sdavidcs if (bus->state != DBG_BUS_STATE_READY) 5805316485Sdavidcs return DBG_STATUS_DBG_BLOCK_NOT_RESET; 5806316485Sdavidcs 5807316485Sdavidcs /* Check if any input was enabled */ 5808316485Sdavidcs if (!bus->num_enabled_storms && 5809316485Sdavidcs !bus->num_enabled_blocks && 5810316485Sdavidcs !bus->rcv_from_other_engine) 5811316485Sdavidcs return DBG_STATUS_NO_INPUT_ENABLED; 5812316485Sdavidcs 5813316485Sdavidcs /* Check if too many input types were enabled (storm+dbgmux) */ 5814316485Sdavidcs if (bus->num_enabled_storms && bus->num_enabled_blocks) 5815316485Sdavidcs return DBG_STATUS_TOO_MANY_INPUTS; 5816316485Sdavidcs 5817316485Sdavidcs /* Configure framing mode */ 5818316485Sdavidcs if ((status = ecore_config_dbg_block_framing_mode(p_hwfn, p_ptt)) != DBG_STATUS_OK) 5819316485Sdavidcs return status; 5820316485Sdavidcs 5821316485Sdavidcs /* Configure DBG block for Storm inputs */ 5822316485Sdavidcs if (bus->num_enabled_storms) 5823316485Sdavidcs if ((status = ecore_config_storm_inputs(p_hwfn, p_ptt)) != DBG_STATUS_OK) 5824316485Sdavidcs return status; 5825316485Sdavidcs 5826316485Sdavidcs /* Configure DBG block for block inputs */ 5827316485Sdavidcs if (bus->num_enabled_blocks) 5828316485Sdavidcs ecore_config_block_inputs(p_hwfn, p_ptt); 5829337519Sdavidcs 5830316485Sdavidcs /* Configure filter type */ 5831316485Sdavidcs if (bus->filter_en) { 5832316485Sdavidcs if (bus->trigger_en) { 5833316485Sdavidcs if (bus->filter_pre_trigger) 5834316485Sdavidcs filter_type = bus->filter_post_trigger ? DBG_BUS_FILTER_TYPE_ON : DBG_BUS_FILTER_TYPE_PRE; 5835316485Sdavidcs else 5836316485Sdavidcs filter_type = bus->filter_post_trigger ? DBG_BUS_FILTER_TYPE_POST : DBG_BUS_FILTER_TYPE_OFF; 5837316485Sdavidcs } 5838316485Sdavidcs else { 5839316485Sdavidcs filter_type = DBG_BUS_FILTER_TYPE_ON; 5840316485Sdavidcs } 5841316485Sdavidcs } 5842316485Sdavidcs else { 5843316485Sdavidcs filter_type = DBG_BUS_FILTER_TYPE_OFF; 5844316485Sdavidcs } 5845316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_FILTER_ENABLE, filter_type); 5846316485Sdavidcs 5847316485Sdavidcs /* Restart timestamp */ 5848316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_TIMESTAMP, 0); 5849316485Sdavidcs 5850316485Sdavidcs /* Enable debug block */ 5851316485Sdavidcs ecore_bus_enable_dbg_block(p_hwfn, p_ptt, 1); 5852316485Sdavidcs 5853316485Sdavidcs /* Configure enabled blocks - must be done before the DBG block is 5854316485Sdavidcs * enabled. 5855316485Sdavidcs */ 5856316485Sdavidcs if (dev_data->bus.num_enabled_blocks) { 5857316485Sdavidcs for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 5858316485Sdavidcs if (!GET_FIELD(dev_data->bus.blocks[block_id].data, DBG_BUS_BLOCK_DATA_ENABLE_MASK) || block_id == BLOCK_DBG) 5859316485Sdavidcs continue; 5860316485Sdavidcs 5861316485Sdavidcs ecore_config_dbg_line(p_hwfn, p_ptt, (enum block_id)block_id, 5862316485Sdavidcs dev_data->bus.blocks[block_id].line_num, 5863316485Sdavidcs GET_FIELD(dev_data->bus.blocks[block_id].data, DBG_BUS_BLOCK_DATA_ENABLE_MASK), 5864316485Sdavidcs GET_FIELD(dev_data->bus.blocks[block_id].data, DBG_BUS_BLOCK_DATA_RIGHT_SHIFT), 5865316485Sdavidcs GET_FIELD(dev_data->bus.blocks[block_id].data, DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK), 5866316485Sdavidcs GET_FIELD(dev_data->bus.blocks[block_id].data, DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK)); 5867316485Sdavidcs } 5868316485Sdavidcs } 5869316485Sdavidcs 5870316485Sdavidcs /* Configure client mask */ 5871316485Sdavidcs ecore_config_dbg_block_client_mask(p_hwfn, p_ptt); 5872316485Sdavidcs 5873316485Sdavidcs /* Configure enabled Storms - must be done after the DBG block is 5874316485Sdavidcs * enabled. 5875316485Sdavidcs */ 5876316485Sdavidcs if (dev_data->bus.num_enabled_storms) 5877316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) 5878316485Sdavidcs if (dev_data->bus.storms[storm_id].enabled) 5879337519Sdavidcs ecore_bus_enable_storm(p_hwfn, p_ptt, (enum dbg_storms)storm_id); 5880316485Sdavidcs 5881316485Sdavidcs dev_data->bus.state = DBG_BUS_STATE_RECORDING; 5882316485Sdavidcs 5883316485Sdavidcs return DBG_STATUS_OK; 5884316485Sdavidcs} 5885316485Sdavidcs 5886316485Sdavidcsenum dbg_status ecore_dbg_bus_stop(struct ecore_hwfn *p_hwfn, 5887316485Sdavidcs struct ecore_ptt *p_ptt) 5888316485Sdavidcs{ 5889316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5890316485Sdavidcs struct dbg_bus_data *bus = &dev_data->bus; 5891316485Sdavidcs enum dbg_status status = DBG_STATUS_OK; 5892316485Sdavidcs 5893316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_stop\n"); 5894316485Sdavidcs 5895316485Sdavidcs if (bus->state != DBG_BUS_STATE_RECORDING) 5896316485Sdavidcs return DBG_STATUS_RECORDING_NOT_STARTED; 5897316485Sdavidcs 5898316485Sdavidcs status = ecore_bus_disable_inputs(p_hwfn, p_ptt, true); 5899316485Sdavidcs if (status != DBG_STATUS_OK) 5900316485Sdavidcs return status; 5901316485Sdavidcs 5902316485Sdavidcs ecore_wr(p_hwfn, p_ptt, DBG_REG_CPU_TIMEOUT, 1); 5903316485Sdavidcs 5904316485Sdavidcs OSAL_MSLEEP(FLUSH_DELAY_MS); 5905316485Sdavidcs 5906316485Sdavidcs ecore_bus_enable_dbg_block(p_hwfn, p_ptt, false); 5907316485Sdavidcs 5908316485Sdavidcs /* Check if trigger worked */ 5909316485Sdavidcs if (bus->trigger_en) { 5910316485Sdavidcs u32 trigger_state = ecore_rd(p_hwfn, p_ptt, DBG_REG_TRIGGER_STATUS_CUR_STATE); 5911316485Sdavidcs 5912316485Sdavidcs if (trigger_state != MAX_TRIGGER_STATES) 5913316485Sdavidcs return DBG_STATUS_DATA_DIDNT_TRIGGER; 5914316485Sdavidcs } 5915316485Sdavidcs 5916316485Sdavidcs bus->state = DBG_BUS_STATE_STOPPED; 5917316485Sdavidcs 5918316485Sdavidcs return status; 5919316485Sdavidcs} 5920316485Sdavidcs 5921316485Sdavidcsenum dbg_status ecore_dbg_bus_get_dump_buf_size(struct ecore_hwfn *p_hwfn, 5922316485Sdavidcs struct ecore_ptt *p_ptt, 5923316485Sdavidcs u32 *buf_size) 5924316485Sdavidcs{ 5925316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5926316485Sdavidcs struct dbg_bus_data *bus = &dev_data->bus; 5927316485Sdavidcs enum dbg_status status; 5928316485Sdavidcs 5929316485Sdavidcs status = ecore_dbg_dev_init(p_hwfn, p_ptt); 5930316485Sdavidcs 5931316485Sdavidcs *buf_size = 0; 5932316485Sdavidcs 5933316485Sdavidcs if (status != DBG_STATUS_OK) 5934316485Sdavidcs return status; 5935316485Sdavidcs 5936316485Sdavidcs /* Add dump header */ 5937316485Sdavidcs *buf_size = (u32)ecore_bus_dump_hdr(p_hwfn, p_ptt, OSAL_NULL, false); 5938316485Sdavidcs 5939316485Sdavidcs switch (bus->target) { 5940316485Sdavidcs case DBG_BUS_TARGET_ID_INT_BUF: 5941316485Sdavidcs *buf_size += INT_BUF_SIZE_IN_DWORDS; break; 5942316485Sdavidcs case DBG_BUS_TARGET_ID_PCI: 5943316485Sdavidcs *buf_size += BYTES_TO_DWORDS(bus->pci_buf.size); break; 5944316485Sdavidcs default: 5945316485Sdavidcs break; 5946316485Sdavidcs } 5947316485Sdavidcs 5948316485Sdavidcs /* Dump last section */ 5949320162Sdavidcs *buf_size += ecore_dump_last_section(OSAL_NULL, 0, false); 5950316485Sdavidcs 5951316485Sdavidcs return DBG_STATUS_OK; 5952316485Sdavidcs} 5953316485Sdavidcs 5954316485Sdavidcsenum dbg_status ecore_dbg_bus_dump(struct ecore_hwfn *p_hwfn, 5955316485Sdavidcs struct ecore_ptt *p_ptt, 5956316485Sdavidcs u32 *dump_buf, 5957316485Sdavidcs u32 buf_size_in_dwords, 5958316485Sdavidcs u32 *num_dumped_dwords) 5959316485Sdavidcs{ 5960316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5961316485Sdavidcs u32 min_buf_size_in_dwords, block_id, offset = 0; 5962316485Sdavidcs struct dbg_bus_data *bus = &dev_data->bus; 5963316485Sdavidcs enum dbg_status status; 5964316485Sdavidcs u8 storm_id; 5965316485Sdavidcs 5966316485Sdavidcs *num_dumped_dwords = 0; 5967316485Sdavidcs 5968316485Sdavidcs status = ecore_dbg_bus_get_dump_buf_size(p_hwfn, p_ptt, &min_buf_size_in_dwords); 5969316485Sdavidcs if (status != DBG_STATUS_OK) 5970316485Sdavidcs return status; 5971316485Sdavidcs 5972316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_bus_dump: dump_buf = 0x%p, buf_size_in_dwords = %d\n", dump_buf, buf_size_in_dwords); 5973316485Sdavidcs 5974316485Sdavidcs if (bus->state != DBG_BUS_STATE_RECORDING && bus->state != DBG_BUS_STATE_STOPPED) 5975316485Sdavidcs return DBG_STATUS_RECORDING_NOT_STARTED; 5976316485Sdavidcs 5977316485Sdavidcs if (bus->state == DBG_BUS_STATE_RECORDING) { 5978316485Sdavidcs enum dbg_status stop_state = ecore_dbg_bus_stop(p_hwfn, p_ptt); 5979316485Sdavidcs if (stop_state != DBG_STATUS_OK) 5980316485Sdavidcs return stop_state; 5981316485Sdavidcs } 5982316485Sdavidcs 5983316485Sdavidcs if (buf_size_in_dwords < min_buf_size_in_dwords) 5984316485Sdavidcs return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5985316485Sdavidcs 5986316485Sdavidcs if (bus->target == DBG_BUS_TARGET_ID_PCI && !bus->pci_buf.size) 5987316485Sdavidcs return DBG_STATUS_PCI_BUF_NOT_ALLOCATED; 5988316485Sdavidcs 5989316485Sdavidcs /* Dump header */ 5990316485Sdavidcs offset += ecore_bus_dump_hdr(p_hwfn, p_ptt, dump_buf + offset, true); 5991316485Sdavidcs 5992316485Sdavidcs /* Dump recorded data */ 5993316485Sdavidcs if (bus->target != DBG_BUS_TARGET_ID_NIG) { 5994316485Sdavidcs u32 recorded_dwords = ecore_bus_dump_data(p_hwfn, p_ptt, dump_buf + offset, true); 5995316485Sdavidcs 5996316485Sdavidcs if (!recorded_dwords) 5997316485Sdavidcs return DBG_STATUS_NO_DATA_RECORDED; 5998316485Sdavidcs if (recorded_dwords % CHUNK_SIZE_IN_DWORDS) 5999316485Sdavidcs return DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED; 6000316485Sdavidcs offset += recorded_dwords; 6001316485Sdavidcs } 6002316485Sdavidcs 6003316485Sdavidcs /* Dump last section */ 6004320162Sdavidcs offset += ecore_dump_last_section(dump_buf, offset, true); 6005316485Sdavidcs 6006316485Sdavidcs /* If recorded to PCI buffer - free the buffer */ 6007316485Sdavidcs ecore_bus_free_pci_buf(p_hwfn); 6008316485Sdavidcs 6009316485Sdavidcs /* Clear debug bus parameters */ 6010316485Sdavidcs bus->state = DBG_BUS_STATE_IDLE; 6011316485Sdavidcs bus->num_enabled_blocks = 0; 6012316485Sdavidcs bus->num_enabled_storms = 0; 6013316485Sdavidcs bus->filter_en = bus->trigger_en = 0; 6014316485Sdavidcs 6015316485Sdavidcs for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) 6016316485Sdavidcs SET_FIELD(bus->blocks[BLOCK_PCIE].data, DBG_BUS_BLOCK_DATA_ENABLE_MASK, 0); 6017316485Sdavidcs 6018316485Sdavidcs for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 6019316485Sdavidcs struct dbg_bus_storm_data *storm_bus = &bus->storms[storm_id]; 6020316485Sdavidcs 6021316485Sdavidcs storm_bus->enabled = false; 6022316485Sdavidcs storm_bus->eid_filter_en = storm_bus->cid_filter_en = 0; 6023316485Sdavidcs } 6024316485Sdavidcs 6025316485Sdavidcs *num_dumped_dwords = offset; 6026316485Sdavidcs 6027316485Sdavidcs return DBG_STATUS_OK; 6028316485Sdavidcs} 6029316485Sdavidcs 6030316485Sdavidcsenum dbg_status ecore_dbg_grc_config(struct ecore_hwfn *p_hwfn, 6031316485Sdavidcs enum dbg_grc_params grc_param, 6032316485Sdavidcs u32 val) 6033316485Sdavidcs{ 6034316485Sdavidcs int i; 6035316485Sdavidcs 6036316485Sdavidcs DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "dbg_grc_config: paramId = %d, val = %d\n", grc_param, val); 6037316485Sdavidcs 6038316485Sdavidcs /* Initializes the GRC parameters (if not initialized). Needed in order 6039316485Sdavidcs * to set the default parameter values for the first time. 6040316485Sdavidcs */ 6041316485Sdavidcs ecore_dbg_grc_init_params(p_hwfn); 6042316485Sdavidcs 6043316485Sdavidcs if (grc_param >= MAX_DBG_GRC_PARAMS) 6044316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 6045316485Sdavidcs if (val < s_grc_param_defs[grc_param].min || 6046316485Sdavidcs val > s_grc_param_defs[grc_param].max) 6047316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 6048316485Sdavidcs 6049316485Sdavidcs if (s_grc_param_defs[grc_param].is_preset) { 6050316485Sdavidcs 6051316485Sdavidcs /* Preset param */ 6052316485Sdavidcs 6053316485Sdavidcs /* Disabling a preset is not allowed. Call 6054316485Sdavidcs * dbg_grc_set_params_default instead. 6055316485Sdavidcs */ 6056316485Sdavidcs if (!val) 6057316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 6058316485Sdavidcs 6059316485Sdavidcs /* Update all params with the preset values */ 6060316485Sdavidcs for (i = 0; i < MAX_DBG_GRC_PARAMS; i++) { 6061316485Sdavidcs u32 preset_val; 6062316485Sdavidcs 6063316485Sdavidcs if (grc_param == DBG_GRC_PARAM_EXCLUDE_ALL) 6064316485Sdavidcs preset_val = s_grc_param_defs[i].exclude_all_preset_val; 6065316485Sdavidcs else if (grc_param == DBG_GRC_PARAM_CRASH) 6066316485Sdavidcs preset_val = s_grc_param_defs[i].crash_preset_val; 6067316485Sdavidcs else 6068316485Sdavidcs return DBG_STATUS_INVALID_ARGS; 6069316485Sdavidcs 6070316485Sdavidcs ecore_grc_set_param(p_hwfn, (enum dbg_grc_params)i, preset_val); 6071316485Sdavidcs } 6072316485Sdavidcs } 6073316485Sdavidcs else { 6074316485Sdavidcs 6075316485Sdavidcs /* Regular param - set its value */ 6076316485Sdavidcs ecore_grc_set_param(p_hwfn, grc_param, val); 6077316485Sdavidcs } 6078316485Sdavidcs 6079316485Sdavidcs return DBG_STATUS_OK; 6080316485Sdavidcs} 6081316485Sdavidcs 6082316485Sdavidcs/* Assign default GRC param values */ 6083316485Sdavidcsvoid ecore_dbg_grc_set_params_default(struct ecore_hwfn *p_hwfn) 6084316485Sdavidcs{ 6085316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 6086316485Sdavidcs u32 i; 6087316485Sdavidcs 6088316485Sdavidcs for (i = 0; i < MAX_DBG_GRC_PARAMS; i++) 6089316485Sdavidcs dev_data->grc.param_val[i] = s_grc_param_defs[i].default_val[dev_data->chip_id]; 6090316485Sdavidcs} 6091316485Sdavidcs 6092316485Sdavidcsenum dbg_status ecore_dbg_grc_get_dump_buf_size(struct ecore_hwfn *p_hwfn, 6093316485Sdavidcs struct ecore_ptt *p_ptt, 6094316485Sdavidcs u32 *buf_size) 6095316485Sdavidcs{ 6096316485Sdavidcs enum dbg_status status = ecore_dbg_dev_init(p_hwfn, p_ptt); 6097316485Sdavidcs 6098316485Sdavidcs *buf_size = 0; 6099316485Sdavidcs 6100316485Sdavidcs if (status != DBG_STATUS_OK) 6101316485Sdavidcs return status; 6102316485Sdavidcs 6103316485Sdavidcs if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr || !s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr || !s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr || 6104316485Sdavidcs !s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr || !s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr) 6105316485Sdavidcs return DBG_STATUS_DBG_ARRAY_NOT_SET; 6106316485Sdavidcs 6107316485Sdavidcs return ecore_grc_dump(p_hwfn, p_ptt, OSAL_NULL, false, buf_size); 6108316485Sdavidcs} 6109316485Sdavidcs 6110316485Sdavidcsenum dbg_status ecore_dbg_grc_dump(struct ecore_hwfn *p_hwfn, 6111316485Sdavidcs struct ecore_ptt *p_ptt, 6112316485Sdavidcs u32 *dump_buf, 6113316485Sdavidcs u32 buf_size_in_dwords, 6114316485Sdavidcs u32 *num_dumped_dwords) 6115316485Sdavidcs{ 6116316485Sdavidcs u32 needed_buf_size_in_dwords; 6117316485Sdavidcs enum dbg_status status; 6118316485Sdavidcs 6119316485Sdavidcs *num_dumped_dwords = 0; 6120316485Sdavidcs 6121316485Sdavidcs status = ecore_dbg_grc_get_dump_buf_size(p_hwfn, p_ptt, &needed_buf_size_in_dwords); 6122316485Sdavidcs if (status != DBG_STATUS_OK) 6123316485Sdavidcs return status; 6124316485Sdavidcs 6125316485Sdavidcs if (buf_size_in_dwords < needed_buf_size_in_dwords) 6126316485Sdavidcs return DBG_STATUS_DUMP_BUF_TOO_SMALL; 6127316485Sdavidcs 6128316485Sdavidcs /* Doesn't do anything, needed for compile time asserts */ 6129316485Sdavidcs ecore_static_asserts(); 6130316485Sdavidcs 6131316485Sdavidcs /* GRC Dump */ 6132316485Sdavidcs status = ecore_grc_dump(p_hwfn, p_ptt, dump_buf, true, num_dumped_dwords); 6133316485Sdavidcs 6134316485Sdavidcs /* Reveret GRC params to their default */ 6135316485Sdavidcs ecore_dbg_grc_set_params_default(p_hwfn); 6136316485Sdavidcs 6137316485Sdavidcs return status; 6138316485Sdavidcs} 6139316485Sdavidcs 6140316485Sdavidcsenum dbg_status ecore_dbg_idle_chk_get_dump_buf_size(struct ecore_hwfn *p_hwfn, 6141316485Sdavidcs struct ecore_ptt *p_ptt, 6142316485Sdavidcs u32 *buf_size) 6143316485Sdavidcs{ 6144316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 6145316485Sdavidcs struct idle_chk_data *idle_chk = &dev_data->idle_chk; 6146316485Sdavidcs enum dbg_status status; 6147316485Sdavidcs 6148316485Sdavidcs *buf_size = 0; 6149337519Sdavidcs 6150316485Sdavidcs status = ecore_dbg_dev_init(p_hwfn, p_ptt); 6151316485Sdavidcs if (status != DBG_STATUS_OK) 6152316485Sdavidcs return status; 6153316485Sdavidcs 6154316485Sdavidcs if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr || !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr || 6155316485Sdavidcs !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr || !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].ptr) 6156316485Sdavidcs return DBG_STATUS_DBG_ARRAY_NOT_SET; 6157316485Sdavidcs 6158316485Sdavidcs if (!idle_chk->buf_size_set) { 6159316485Sdavidcs idle_chk->buf_size = ecore_idle_chk_dump(p_hwfn, p_ptt, OSAL_NULL, false); 6160316485Sdavidcs idle_chk->buf_size_set = true; 6161316485Sdavidcs } 6162316485Sdavidcs 6163316485Sdavidcs *buf_size = idle_chk->buf_size; 6164316485Sdavidcs 6165316485Sdavidcs return DBG_STATUS_OK; 6166316485Sdavidcs} 6167316485Sdavidcs 6168316485Sdavidcsenum dbg_status ecore_dbg_idle_chk_dump(struct ecore_hwfn *p_hwfn, 6169316485Sdavidcs struct ecore_ptt *p_ptt, 6170316485Sdavidcs u32 *dump_buf, 6171316485Sdavidcs u32 buf_size_in_dwords, 6172316485Sdavidcs u32 *num_dumped_dwords) 6173316485Sdavidcs{ 6174316485Sdavidcs u32 needed_buf_size_in_dwords; 6175316485Sdavidcs enum dbg_status status; 6176316485Sdavidcs 6177316485Sdavidcs *num_dumped_dwords = 0; 6178316485Sdavidcs 6179316485Sdavidcs status = ecore_dbg_idle_chk_get_dump_buf_size(p_hwfn, p_ptt, &needed_buf_size_in_dwords); 6180316485Sdavidcs if (status != DBG_STATUS_OK) 6181316485Sdavidcs return status; 6182316485Sdavidcs 6183316485Sdavidcs if (buf_size_in_dwords < needed_buf_size_in_dwords) 6184316485Sdavidcs return DBG_STATUS_DUMP_BUF_TOO_SMALL; 6185316485Sdavidcs 6186316485Sdavidcs /* Update reset state */ 6187316485Sdavidcs ecore_update_blocks_reset_state(p_hwfn, p_ptt); 6188316485Sdavidcs 6189316485Sdavidcs /* Idle Check Dump */ 6190316485Sdavidcs *num_dumped_dwords = ecore_idle_chk_dump(p_hwfn, p_ptt, dump_buf, true); 6191316485Sdavidcs 6192316485Sdavidcs /* Reveret GRC params to their default */ 6193316485Sdavidcs ecore_dbg_grc_set_params_default(p_hwfn); 6194316485Sdavidcs 6195316485Sdavidcs return DBG_STATUS_OK; 6196316485Sdavidcs} 6197316485Sdavidcs 6198316485Sdavidcsenum dbg_status ecore_dbg_mcp_trace_get_dump_buf_size(struct ecore_hwfn *p_hwfn, 6199316485Sdavidcs struct ecore_ptt *p_ptt, 6200316485Sdavidcs u32 *buf_size) 6201316485Sdavidcs{ 6202316485Sdavidcs enum dbg_status status = ecore_dbg_dev_init(p_hwfn, p_ptt); 6203316485Sdavidcs 6204316485Sdavidcs *buf_size = 0; 6205316485Sdavidcs 6206316485Sdavidcs if (status != DBG_STATUS_OK) 6207316485Sdavidcs return status; 6208316485Sdavidcs 6209316485Sdavidcs return ecore_mcp_trace_dump(p_hwfn, p_ptt, OSAL_NULL, false, buf_size); 6210316485Sdavidcs} 6211316485Sdavidcs 6212316485Sdavidcsenum dbg_status ecore_dbg_mcp_trace_dump(struct ecore_hwfn *p_hwfn, 6213316485Sdavidcs struct ecore_ptt *p_ptt, 6214316485Sdavidcs u32 *dump_buf, 6215316485Sdavidcs u32 buf_size_in_dwords, 6216316485Sdavidcs u32 *num_dumped_dwords) 6217316485Sdavidcs{ 6218316485Sdavidcs u32 needed_buf_size_in_dwords; 6219316485Sdavidcs enum dbg_status status; 6220316485Sdavidcs 6221316485Sdavidcs status = ecore_dbg_mcp_trace_get_dump_buf_size(p_hwfn, p_ptt, &needed_buf_size_in_dwords); 6222316485Sdavidcs if (status != DBG_STATUS_OK && status != DBG_STATUS_NVRAM_GET_IMAGE_FAILED) 6223316485Sdavidcs return status; 6224316485Sdavidcs 6225316485Sdavidcs if (buf_size_in_dwords < needed_buf_size_in_dwords) 6226316485Sdavidcs return DBG_STATUS_DUMP_BUF_TOO_SMALL; 6227316485Sdavidcs 6228316485Sdavidcs /* Update reset state */ 6229316485Sdavidcs ecore_update_blocks_reset_state(p_hwfn, p_ptt); 6230316485Sdavidcs 6231316485Sdavidcs /* Perform dump */ 6232316485Sdavidcs status = ecore_mcp_trace_dump(p_hwfn, p_ptt, dump_buf, true, num_dumped_dwords); 6233316485Sdavidcs 6234316485Sdavidcs /* Reveret GRC params to their default */ 6235316485Sdavidcs ecore_dbg_grc_set_params_default(p_hwfn); 6236316485Sdavidcs 6237316485Sdavidcs return status; 6238316485Sdavidcs} 6239316485Sdavidcs 6240316485Sdavidcsenum dbg_status ecore_dbg_reg_fifo_get_dump_buf_size(struct ecore_hwfn *p_hwfn, 6241316485Sdavidcs struct ecore_ptt *p_ptt, 6242316485Sdavidcs u32 *buf_size) 6243316485Sdavidcs{ 6244316485Sdavidcs enum dbg_status status = ecore_dbg_dev_init(p_hwfn, p_ptt); 6245316485Sdavidcs 6246316485Sdavidcs *buf_size = 0; 6247316485Sdavidcs 6248316485Sdavidcs if (status != DBG_STATUS_OK) 6249316485Sdavidcs return status; 6250316485Sdavidcs 6251316485Sdavidcs return ecore_reg_fifo_dump(p_hwfn, p_ptt, OSAL_NULL, false, buf_size); 6252316485Sdavidcs} 6253316485Sdavidcs 6254316485Sdavidcsenum dbg_status ecore_dbg_reg_fifo_dump(struct ecore_hwfn *p_hwfn, 6255316485Sdavidcs struct ecore_ptt *p_ptt, 6256316485Sdavidcs u32 *dump_buf, 6257316485Sdavidcs u32 buf_size_in_dwords, 6258316485Sdavidcs u32 *num_dumped_dwords) 6259316485Sdavidcs{ 6260316485Sdavidcs u32 needed_buf_size_in_dwords; 6261316485Sdavidcs enum dbg_status status; 6262316485Sdavidcs 6263316485Sdavidcs *num_dumped_dwords = 0; 6264316485Sdavidcs 6265316485Sdavidcs status = ecore_dbg_reg_fifo_get_dump_buf_size(p_hwfn, p_ptt, &needed_buf_size_in_dwords); 6266316485Sdavidcs if (status != DBG_STATUS_OK) 6267316485Sdavidcs return status; 6268316485Sdavidcs 6269316485Sdavidcs if (buf_size_in_dwords < needed_buf_size_in_dwords) 6270316485Sdavidcs return DBG_STATUS_DUMP_BUF_TOO_SMALL; 6271316485Sdavidcs 6272316485Sdavidcs /* Update reset state */ 6273316485Sdavidcs ecore_update_blocks_reset_state(p_hwfn, p_ptt); 6274316485Sdavidcs 6275316485Sdavidcs status = ecore_reg_fifo_dump(p_hwfn, p_ptt, dump_buf, true, num_dumped_dwords); 6276316485Sdavidcs 6277316485Sdavidcs /* Reveret GRC params to their default */ 6278316485Sdavidcs ecore_dbg_grc_set_params_default(p_hwfn); 6279316485Sdavidcs 6280316485Sdavidcs return status; 6281316485Sdavidcs} 6282316485Sdavidcs 6283316485Sdavidcsenum dbg_status ecore_dbg_igu_fifo_get_dump_buf_size(struct ecore_hwfn *p_hwfn, 6284316485Sdavidcs struct ecore_ptt *p_ptt, 6285316485Sdavidcs u32 *buf_size) 6286316485Sdavidcs{ 6287316485Sdavidcs enum dbg_status status = ecore_dbg_dev_init(p_hwfn, p_ptt); 6288316485Sdavidcs 6289316485Sdavidcs *buf_size = 0; 6290316485Sdavidcs 6291316485Sdavidcs if (status != DBG_STATUS_OK) 6292316485Sdavidcs return status; 6293316485Sdavidcs 6294316485Sdavidcs return ecore_igu_fifo_dump(p_hwfn, p_ptt, OSAL_NULL, false, buf_size); 6295316485Sdavidcs} 6296316485Sdavidcs 6297316485Sdavidcsenum dbg_status ecore_dbg_igu_fifo_dump(struct ecore_hwfn *p_hwfn, 6298316485Sdavidcs struct ecore_ptt *p_ptt, 6299316485Sdavidcs u32 *dump_buf, 6300316485Sdavidcs u32 buf_size_in_dwords, 6301316485Sdavidcs u32 *num_dumped_dwords) 6302316485Sdavidcs{ 6303316485Sdavidcs u32 needed_buf_size_in_dwords; 6304316485Sdavidcs enum dbg_status status; 6305316485Sdavidcs 6306316485Sdavidcs *num_dumped_dwords = 0; 6307316485Sdavidcs 6308316485Sdavidcs status = ecore_dbg_igu_fifo_get_dump_buf_size(p_hwfn, p_ptt, &needed_buf_size_in_dwords); 6309316485Sdavidcs if (status != DBG_STATUS_OK) 6310316485Sdavidcs return status; 6311316485Sdavidcs 6312316485Sdavidcs if (buf_size_in_dwords < needed_buf_size_in_dwords) 6313316485Sdavidcs return DBG_STATUS_DUMP_BUF_TOO_SMALL; 6314316485Sdavidcs 6315316485Sdavidcs /* Update reset state */ 6316316485Sdavidcs ecore_update_blocks_reset_state(p_hwfn, p_ptt); 6317316485Sdavidcs 6318316485Sdavidcs status = ecore_igu_fifo_dump(p_hwfn, p_ptt, dump_buf, true, num_dumped_dwords); 6319316485Sdavidcs 6320316485Sdavidcs /* Reveret GRC params to their default */ 6321316485Sdavidcs ecore_dbg_grc_set_params_default(p_hwfn); 6322316485Sdavidcs 6323316485Sdavidcs return status; 6324316485Sdavidcs} 6325316485Sdavidcs 6326316485Sdavidcsenum dbg_status ecore_dbg_protection_override_get_dump_buf_size(struct ecore_hwfn *p_hwfn, 6327316485Sdavidcs struct ecore_ptt *p_ptt, 6328316485Sdavidcs u32 *buf_size) 6329316485Sdavidcs{ 6330316485Sdavidcs enum dbg_status status = ecore_dbg_dev_init(p_hwfn, p_ptt); 6331316485Sdavidcs 6332316485Sdavidcs *buf_size = 0; 6333316485Sdavidcs 6334316485Sdavidcs if (status != DBG_STATUS_OK) 6335316485Sdavidcs return status; 6336316485Sdavidcs 6337316485Sdavidcs return ecore_protection_override_dump(p_hwfn, p_ptt, OSAL_NULL, false, buf_size); 6338316485Sdavidcs} 6339316485Sdavidcs 6340316485Sdavidcsenum dbg_status ecore_dbg_protection_override_dump(struct ecore_hwfn *p_hwfn, 6341316485Sdavidcs struct ecore_ptt *p_ptt, 6342316485Sdavidcs u32 *dump_buf, 6343316485Sdavidcs u32 buf_size_in_dwords, 6344316485Sdavidcs u32 *num_dumped_dwords) 6345316485Sdavidcs{ 6346316485Sdavidcs u32 needed_buf_size_in_dwords; 6347316485Sdavidcs enum dbg_status status; 6348316485Sdavidcs 6349316485Sdavidcs *num_dumped_dwords = 0; 6350316485Sdavidcs 6351316485Sdavidcs status = ecore_dbg_protection_override_get_dump_buf_size(p_hwfn, p_ptt, &needed_buf_size_in_dwords); 6352316485Sdavidcs if (status != DBG_STATUS_OK) 6353316485Sdavidcs return status; 6354316485Sdavidcs 6355316485Sdavidcs if (buf_size_in_dwords < needed_buf_size_in_dwords) 6356316485Sdavidcs return DBG_STATUS_DUMP_BUF_TOO_SMALL; 6357316485Sdavidcs 6358316485Sdavidcs /* Update reset state */ 6359316485Sdavidcs ecore_update_blocks_reset_state(p_hwfn, p_ptt); 6360316485Sdavidcs 6361316485Sdavidcs status = ecore_protection_override_dump(p_hwfn, p_ptt, dump_buf, true, num_dumped_dwords); 6362316485Sdavidcs 6363316485Sdavidcs /* Reveret GRC params to their default */ 6364316485Sdavidcs ecore_dbg_grc_set_params_default(p_hwfn); 6365316485Sdavidcs 6366316485Sdavidcs return status; 6367316485Sdavidcs} 6368316485Sdavidcs 6369316485Sdavidcsenum dbg_status ecore_dbg_fw_asserts_get_dump_buf_size(struct ecore_hwfn *p_hwfn, 6370316485Sdavidcs struct ecore_ptt *p_ptt, 6371316485Sdavidcs u32 *buf_size) 6372316485Sdavidcs{ 6373316485Sdavidcs enum dbg_status status = ecore_dbg_dev_init(p_hwfn, p_ptt); 6374316485Sdavidcs 6375316485Sdavidcs *buf_size = 0; 6376316485Sdavidcs 6377316485Sdavidcs if (status != DBG_STATUS_OK) 6378316485Sdavidcs return status; 6379316485Sdavidcs 6380316485Sdavidcs /* Update reset state */ 6381316485Sdavidcs ecore_update_blocks_reset_state(p_hwfn, p_ptt); 6382316485Sdavidcs 6383316485Sdavidcs *buf_size = ecore_fw_asserts_dump(p_hwfn, p_ptt, OSAL_NULL, false); 6384316485Sdavidcs 6385316485Sdavidcs return DBG_STATUS_OK; 6386316485Sdavidcs} 6387316485Sdavidcs 6388316485Sdavidcsenum dbg_status ecore_dbg_fw_asserts_dump(struct ecore_hwfn *p_hwfn, 6389316485Sdavidcs struct ecore_ptt *p_ptt, 6390316485Sdavidcs u32 *dump_buf, 6391316485Sdavidcs u32 buf_size_in_dwords, 6392316485Sdavidcs u32 *num_dumped_dwords) 6393316485Sdavidcs{ 6394316485Sdavidcs u32 needed_buf_size_in_dwords; 6395316485Sdavidcs enum dbg_status status; 6396316485Sdavidcs 6397316485Sdavidcs *num_dumped_dwords = 0; 6398316485Sdavidcs 6399316485Sdavidcs status = ecore_dbg_fw_asserts_get_dump_buf_size(p_hwfn, p_ptt, &needed_buf_size_in_dwords); 6400316485Sdavidcs if (status != DBG_STATUS_OK) 6401316485Sdavidcs return status; 6402316485Sdavidcs 6403316485Sdavidcs if (buf_size_in_dwords < needed_buf_size_in_dwords) 6404316485Sdavidcs return DBG_STATUS_DUMP_BUF_TOO_SMALL; 6405316485Sdavidcs 6406316485Sdavidcs *num_dumped_dwords = ecore_fw_asserts_dump(p_hwfn, p_ptt, dump_buf, true); 6407316485Sdavidcs 6408316485Sdavidcs /* Reveret GRC params to their default */ 6409316485Sdavidcs ecore_dbg_grc_set_params_default(p_hwfn); 6410316485Sdavidcs 6411316485Sdavidcs return DBG_STATUS_OK; 6412316485Sdavidcs} 6413316485Sdavidcs 6414316485Sdavidcsenum dbg_status ecore_dbg_read_attn(struct ecore_hwfn *p_hwfn, 6415316485Sdavidcs struct ecore_ptt *p_ptt, 6416316485Sdavidcs enum block_id block_id, 6417316485Sdavidcs enum dbg_attn_type attn_type, 6418316485Sdavidcs bool clear_status, 6419316485Sdavidcs struct dbg_attn_block_result *results) 6420316485Sdavidcs{ 6421316485Sdavidcs enum dbg_status status = ecore_dbg_dev_init(p_hwfn, p_ptt); 6422316485Sdavidcs u8 reg_idx, num_attn_regs, num_result_regs = 0; 6423316485Sdavidcs const struct dbg_attn_reg *attn_reg_arr; 6424316485Sdavidcs 6425316485Sdavidcs if (status != DBG_STATUS_OK) 6426316485Sdavidcs return status; 6427316485Sdavidcs 6428316485Sdavidcs if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr || !s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr || !s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr) 6429316485Sdavidcs return DBG_STATUS_DBG_ARRAY_NOT_SET; 6430316485Sdavidcs 6431316485Sdavidcs attn_reg_arr = ecore_get_block_attn_regs(block_id, attn_type, &num_attn_regs); 6432316485Sdavidcs 6433316485Sdavidcs for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) { 6434316485Sdavidcs const struct dbg_attn_reg *reg_data = &attn_reg_arr[reg_idx]; 6435316485Sdavidcs struct dbg_attn_reg_result *reg_result; 6436316485Sdavidcs u32 sts_addr, sts_val; 6437316485Sdavidcs u16 modes_buf_offset; 6438316485Sdavidcs bool eval_mode; 6439316485Sdavidcs 6440316485Sdavidcs /* Check mode */ 6441316485Sdavidcs eval_mode = GET_FIELD(reg_data->mode.data, DBG_MODE_HDR_EVAL_MODE) > 0; 6442316485Sdavidcs modes_buf_offset = GET_FIELD(reg_data->mode.data, DBG_MODE_HDR_MODES_BUF_OFFSET); 6443316485Sdavidcs if (eval_mode && !ecore_is_mode_match(p_hwfn, &modes_buf_offset)) 6444316485Sdavidcs continue; 6445316485Sdavidcs 6446316485Sdavidcs /* Mode match - read attention status register */ 6447316485Sdavidcs sts_addr = DWORDS_TO_BYTES(clear_status ? reg_data->sts_clr_address : GET_FIELD(reg_data->data, DBG_ATTN_REG_STS_ADDRESS)); 6448316485Sdavidcs sts_val = ecore_rd(p_hwfn, p_ptt, sts_addr); 6449316485Sdavidcs if (!sts_val) 6450316485Sdavidcs continue; 6451316485Sdavidcs 6452316485Sdavidcs /* Non-zero attention status - add to results */ 6453316485Sdavidcs reg_result = &results->reg_results[num_result_regs]; 6454316485Sdavidcs SET_FIELD(reg_result->data, DBG_ATTN_REG_RESULT_STS_ADDRESS, sts_addr); 6455316485Sdavidcs SET_FIELD(reg_result->data, DBG_ATTN_REG_RESULT_NUM_REG_ATTN, GET_FIELD(reg_data->data, DBG_ATTN_REG_NUM_REG_ATTN)); 6456316485Sdavidcs reg_result->block_attn_offset = reg_data->block_attn_offset; 6457316485Sdavidcs reg_result->sts_val = sts_val; 6458316485Sdavidcs reg_result->mask_val = ecore_rd(p_hwfn, p_ptt, DWORDS_TO_BYTES(reg_data->mask_address)); 6459316485Sdavidcs num_result_regs++; 6460316485Sdavidcs } 6461316485Sdavidcs 6462316485Sdavidcs results->block_id = (u8)block_id; 6463316485Sdavidcs results->names_offset = ecore_get_block_attn_data(block_id, attn_type)->names_offset; 6464316485Sdavidcs SET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_ATTN_TYPE, attn_type); 6465316485Sdavidcs SET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_NUM_REGS, num_result_regs); 6466316485Sdavidcs 6467316485Sdavidcs return DBG_STATUS_OK; 6468316485Sdavidcs} 6469316485Sdavidcs 6470316485Sdavidcsenum dbg_status ecore_dbg_print_attn(struct ecore_hwfn *p_hwfn, 6471316485Sdavidcs struct dbg_attn_block_result *results) 6472316485Sdavidcs{ 6473316485Sdavidcs enum dbg_attn_type attn_type; 6474316485Sdavidcs u8 num_regs, i; 6475316485Sdavidcs 6476316485Sdavidcs num_regs = GET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_NUM_REGS); 6477316485Sdavidcs attn_type = (enum dbg_attn_type)GET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_ATTN_TYPE); 6478316485Sdavidcs 6479316485Sdavidcs for (i = 0; i < num_regs; i++) { 6480316485Sdavidcs struct dbg_attn_reg_result *reg_result; 6481316485Sdavidcs const char *attn_type_str; 6482316485Sdavidcs u32 sts_addr; 6483316485Sdavidcs 6484316485Sdavidcs reg_result = &results->reg_results[i]; 6485316485Sdavidcs attn_type_str = (attn_type == ATTN_TYPE_INTERRUPT ? "interrupt" : "parity"); 6486316485Sdavidcs sts_addr = GET_FIELD(reg_result->data, DBG_ATTN_REG_RESULT_STS_ADDRESS); 6487316485Sdavidcs DP_NOTICE(p_hwfn, false, "%s: address 0x%08x, status 0x%08x, mask 0x%08x\n", attn_type_str, sts_addr, reg_result->sts_val, reg_result->mask_val); 6488316485Sdavidcs } 6489316485Sdavidcs 6490316485Sdavidcs return DBG_STATUS_OK; 6491316485Sdavidcs} 6492316485Sdavidcs 6493316485Sdavidcsbool ecore_is_block_in_reset(struct ecore_hwfn *p_hwfn, 6494316485Sdavidcs struct ecore_ptt *p_ptt, 6495316485Sdavidcs enum block_id block_id) 6496316485Sdavidcs{ 6497316485Sdavidcs struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 6498316485Sdavidcs struct block_defs *block = s_block_defs[block_id]; 6499316485Sdavidcs u32 reset_reg; 6500337519Sdavidcs 6501316485Sdavidcs if (!block->has_reset_bit) 6502316485Sdavidcs return false; 6503316485Sdavidcs 6504316485Sdavidcs reset_reg = block->reset_reg; 6505316485Sdavidcs 6506316485Sdavidcs return s_reset_regs_defs[reset_reg].exists[dev_data->chip_id] ? 6507316485Sdavidcs !(ecore_rd(p_hwfn, p_ptt, s_reset_regs_defs[reset_reg].addr) & (1 << block->reset_bit_offset)) : true; 6508316485Sdavidcs} 6509316485Sdavidcs 6510