Searched refs:radeon_ring_write (Results 1 - 14 of 14) sorted by relevance

/freebsd-10-stable/sys/dev/drm2/radeon/
H A Devergreen_blit_kms.c59 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
60 radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
61 radeon_ring_write(ring, gpu_addr >> 8);
62 radeon_ring_write(ring, pitch);
63 radeon_ring_write(ring, slice);
64 radeon_ring_write(ring, 0);
65 radeon_ring_write(ring, cb_color_info);
66 radeon_ring_write(ring, 0);
67 radeon_ring_write(ring, (w - 1) | ((h - 1) << 16));
68 radeon_ring_write(rin
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H A Dr600_blit_kms.c57 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
58 radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
59 radeon_ring_write(ring, gpu_addr >> 8);
62 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
63 radeon_ring_write(ring, 2 << 0);
66 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
67 radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
68 radeon_ring_write(ring, (pitch << 0) | (slice << 10));
70 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
71 radeon_ring_write(rin
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H A Dni.c928 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
929 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
930 radeon_ring_write(ring, 0);
931 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
932 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
933 radeon_ring_write(ring, 0xFFFFFFFF);
934 radeon_ring_write(ring, 0);
935 radeon_ring_write(ring, 10); /* poll interval */
937 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
938 radeon_ring_write(rin
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H A Dr300.c186 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
187 radeon_ring_write(ring, 0);
188 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
189 radeon_ring_write(ring, 0);
191 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
192 radeon_ring_write(ring, R300_RB3D_DC_FLUSH);
193 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
194 radeon_ring_write(ring, R300_ZC_FLUSH);
196 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
197 radeon_ring_write(rin
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H A Dsi.c1803 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1804 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1805 radeon_ring_write(ring, 0);
1806 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1807 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1811 radeon_ring_write(ring, 0xFFFFFFFF);
1812 radeon_ring_write(ring, 0);
1813 radeon_ring_write(ring, 10); /* poll interval */
1815 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1816 radeon_ring_write(rin
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H A Drv515.c74 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
75 radeon_ring_write(ring,
80 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
81 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
82 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
83 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
84 radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
85 radeon_ring_write(ring, 0);
86 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
87 radeon_ring_write(rin
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H A Dr600.c2211 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2212 radeon_ring_write(ring, 0x1);
2214 radeon_ring_write(ring, 0x0);
2215 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2217 radeon_ring_write(ring, 0x3);
2218 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2220 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2221 radeon_ring_write(ring, 0);
2222 radeon_ring_write(ring, 0);
2481 radeon_ring_write(rin
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H A Dr200.c108 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
109 radeon_ring_write(ring, (1 << 16));
116 radeon_ring_write(ring, PACKET0(0x720, 2));
117 radeon_ring_write(ring, src_offset);
118 radeon_ring_write(ring, dst_offset);
119 radeon_ring_write(ring, cur_size | (1U << 31) | (1 << 30));
123 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
124 radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE);
H A Devergreen.c1609 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1610 radeon_ring_write(ring, 1);
1614 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1615 radeon_ring_write(ring, ((ring->rptr_save_reg -
1617 radeon_ring_write(ring, next_rptr);
1620 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
1621 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1622 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
1623 radeon_ring_write(ring, next_rptr);
1624 radeon_ring_write(rin
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H A Dr420.c214 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
215 radeon_ring_write(ring, rdev->config.r300.resync_scratch);
216 radeon_ring_write(ring, 0xDEADBEEF);
228 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
229 radeon_ring_write(ring, R300_RB3D_DC_FINISH);
H A Dr100.c854 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
855 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
856 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
857 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
859 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
860 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
861 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
862 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
864 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
865 radeon_ring_write(rin
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H A Dradeon_ring.c306 * radeon_ring_write - write a value to the ring
313 void radeon_ring_write(struct radeon_ring *ring, uint32_t v) function
447 radeon_ring_write(ring, ring->nop);
511 radeon_ring_write(ring, ring->nop);
663 radeon_ring_write(ring, data[i]);
H A Drv770.c946 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
947 radeon_ring_write(ring, dst_offset & 0xfffffffc);
948 radeon_ring_write(ring, src_offset & 0xfffffffc);
949 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
950 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
H A Dradeon.h1804 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) function
1813 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);

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