Searched refs:WREG32_PLL (Results 1 - 12 of 12) sorted by relevance

/freebsd-10-stable/sys/dev/drm2/radeon/
H A Dradeon_clocks.c402 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
406 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
412 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
418 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
425 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
434 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
438 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
444 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
465 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
471 WREG32_PLL(RADEON_CLK_PIN_CNT
[all...]
H A Drs600.c208 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
220 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
227 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
235 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
242 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
H A Dr520.c91 WREG32_PLL(0x000D, tmp);
H A Dradeon_legacy_crtc.c867 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
892 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
972 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
998 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
H A Dradeon_legacy_tv.c287 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B);
296 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test);
774 WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl);
H A Dradeon_legacy_encoders.c124 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
663 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
706 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
1597 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1671 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
H A Dr420.c199 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
H A Drv515.c171 WREG32_PLL(0x000D, tmp);
502 WREG32_PLL(R_00000F_CP_DYN_CNTL,
504 WREG32_PLL(R_000011_E2_DYN_CNTL,
506 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
H A Dr100.c436 WREG32_PLL(SCLK_CNTL, sclk_cntl);
437 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
438 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
2804 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
3967 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
H A Dradeon_combios.c3073 WREG32_PLL(reg, val);
3190 WREG32_PLL(addr, val);
3203 WREG32_PLL(addr, tmp);
3242 WREG32_PLL(RADEON_MCLK_CNTL,
3246 WREG32_PLL
H A Dradeon.h1697 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) macro
1716 WREG32_PLL(reg, tmp_); \
H A Dr300.c1350 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);

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