Searched refs:WREG32_P (Results 1 - 10 of 10) sorted by relevance

/freebsd-10-stable/sys/dev/drm2/radeon/
H A Dr600_audio.c164 WREG32_P(R600_AUDIO_ENABLE,
204 WREG32_P(R600_AUDIO_TIMING, 0, ~0x301);
210 WREG32_P(R600_AUDIO_TIMING, 0x100, ~0x301);
H A Dr600_hdmi.c313 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
467 WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);
500 WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
505 WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,
510 WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN);
567 WREG32_P(AVIVO_TMDSA_CNTL, 0,
571 WREG32_P(AVIVO_LVTMA_CNTL, 0,
575 WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN);
H A Dradeon_legacy_crtc.c331 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
333 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
335 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
345 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
347 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
349 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
913 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
934 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
H A Dradeon_legacy_encoders.c617 WREG32_P(RADEON_DAC_CNTL,
1281 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1318 WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1368 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1609 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1665 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
H A Dradeon_cursor.c121 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
H A Dni.c1177 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1184 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
H A Dradeon.h1704 #define WREG32_P(reg, val, mask) \ macro
H A Dr100.c2858 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
H A Dsi.c3975 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
H A Devergreen.c3315 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);

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