Searched refs:TRC (Results 1 - 8 of 8) sorted by relevance
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 80 const TargetRegisterClass *TRC); 104 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC); 140 const TargetRegisterClass *TRC) { 146 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); 148 return TRC->contains(Reg); 282 const TargetRegisterClass *TRC = local 284 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { 455 const TargetRegisterClass *TRC) { 456 unsigned Out = MRI->createVirtualRegister(TRC); 139 usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC) argument 451 createExtractSubreg(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned DReg, unsigned Lane, const TargetRegisterClass *TRC) argument
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H A D | ARMISelLowering.cpp | 6340 const TargetRegisterClass *TRC = isThumb2 ? local 6343 unsigned scratch = MRI.createVirtualRegister(TRC); 6344 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC); 6448 const TargetRegisterClass *TRC = isThumb2 ? local 6451 unsigned scratch = MRI.createVirtualRegister(TRC); 6452 unsigned scratch2 = MRI.createVirtualRegister(TRC); 6568 const TargetRegisterClass *TRC = isThumb2 ? local 6571 unsigned storesuccess = MRI.createVirtualRegister(TRC); 6627 unsigned tmpRegLo = MRI.createVirtualRegister(TRC); 6631 unsigned tmpRegHi = MRI.createVirtualRegister(TRC); 6764 const TargetRegisterClass *TRC = isThumb ? local 6870 const TargetRegisterClass *TRC = Subtarget->isThumb() ? local 7393 const TargetRegisterClass *TRC = 0; local [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 1834 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); local 1835 MRI->constrainRegClass(EvenReg, TRC); 1836 MRI->constrainRegClass(OddReg, TRC);
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/freebsd-10-stable/usr.sbin/lpr/lpd/ |
H A D | printjob.c | 1500 #define TRC(q) (((q)-' ')&0177) macro 1514 d = dropit(c = TRC(cc = *sp++)); 1539 case TRC('_'): 1540 case TRC(';'): 1541 case TRC(','): 1542 case TRC('g'): 1543 case TRC('j'): 1544 case TRC('p'): 1545 case TRC('q'): 1546 case TRC(' [all...] |
/freebsd-10-stable/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 491 const TargetRegisterClass *TRC = 500 TRC == MRI->getRegClass(SrcReg)) { 506 VRBase = MRI->createVirtualRegister(TRC); 520 VRBase = MRI->createVirtualRegister(TRC); 625 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 627 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
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/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 566 const TargetRegisterClass *TRC; local 568 TRC = &Hexagon::PredRegsRegClass; 570 TRC = &Hexagon::IntRegsRegClass; 572 TRC = &Hexagon::DoubleRegsRegClass; 577 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
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/freebsd-10-stable/contrib/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 2620 const TargetRegisterClass *TRC; local 2622 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; 2623 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; 2626 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); 2655 const TargetRegisterClass *TRC; local 2657 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break; 2658 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; 2659 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; 2662 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
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/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 465 const TargetRegisterClass *TRC local 467 unsigned scratch = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC); 537 const TargetRegisterClass *TRC, *TRCsp; local 539 TRC = &AArch64::GPR64RegClass; 542 TRC = &AArch64::GPR32RegClass; 560 unsigned scratch = MRI.createVirtualRegister(TRC);
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