Searched refs:RREG32_PLL (Results 1 - 11 of 11) sorted by relevance

/freebsd-10-stable/sys/dev/drm2/radeon/
H A Dradeon_clocks.c45 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
51 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
58 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
75 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
81 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
88 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
122 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
152 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
200 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
216 RREG32_PLL(RADEON_M_SPLL_REF_FB_DI
[all...]
H A Dradeon_legacy_crtc.c224 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
232 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
251 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
259 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
830 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
879 RREG32_PLL(RADEON_P2PLL_CNTL));
898 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
910 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
911 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
985 RREG32_PLL(RADEON_PPLL_CNT
[all...]
H A Drs600.c193 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
210 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
222 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
230 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
237 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
H A Dr420.c195 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
H A Dradeon_combios.c1230 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1235 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
3071 val = RREG32_PLL(reg);
3150 (RREG32_PLL
3200 tmp = RREG32_PLL(addr);
3218 (RREG32_PLL
3226 if (RREG32_PLL
3234 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3238 RREG32_PLL
H A Dradeon_legacy_encoders.c111 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
655 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
1578 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
H A Drv515.c503 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
505 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
507 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
H A Dr100.c390 sclk_cntl = RREG32_PLL(SCLK_CNTL);
391 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
393 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
2802 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
3963 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
H A Dradeon.h1696 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) macro
1713 uint32_t tmp_ = RREG32_PLL(reg); \
H A Dradeon_legacy_tv.c286 save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL);
H A Dr300.c1346 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);

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