/freebsd-10-stable/sys/contrib/dev/ath/ath_hal/ar9300/ |
H A D | ar9300_tx99_tgt.c | 150 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 157 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 164 OS_REG_WRITE(ah, AR_PHY_TST_DAC_CONST, OS_REG_READ(ah, AR_PHY_TST_DAC_CONST) | (0x7ff<<11) | 0x7ff); 165 OS_REG_WRITE(ah, AR_PHY_TEST_CTL_STATUS, OS_REG_READ(ah, AR_PHY_TEST_CTL_STATUS) | (1<<7) | (1<<1)); 166 OS_REG_WRITE(ah, AR_PHY_ADDAC_PARA_CTL, (OS_REG_READ(ah, AR_PHY_ADDAC_PARA_CTL) | (1<<31) | (1<<15)) & ~(1<<13)); 171 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 174 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) 176 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 180 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP) 182 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, (OS_REG_READ(a [all...] |
H A D | ar9300_recv.c | 34 return OS_REG_READ(ath, AR_HP_RXDP); 36 return OS_REG_READ(ath, AR_LP_RXDP); 91 __func__, OS_REG_READ(ah, AR_OBS_BUS_1)); 120 org_value = OS_REG_READ(ah, AR_MACMISC); 132 OS_REG_READ(ah, AR_DMADBG_7)); 140 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) { 151 OS_REG_READ(ah, AR_CR), 152 OS_REG_READ(ah, AR_DIAG_SW)); 207 u_int32_t bits = OS_REG_READ(ah, AR_RX_FILTER); 208 u_int32_t phybits = OS_REG_READ(a [all...] |
H A D | ar9300_gpio.c | 406 gpio_in = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN)); 468 reg_val = OS_REG_READ(ah, regs[i]); 482 reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL)); 495 reg_val = OS_REG_READ(ah, regs[i]); 513 return OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL)); 535 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR)); 587 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT))); 590 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN))); 593 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT))); 596 OS_REG_READ(a [all...] |
H A D | ar9300_misc.c | 312 tsf = OS_REG_READ(ah, AR_TSF_U32); 313 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32); 330 return OS_REG_READ(ah, AR_TSF_L32); 336 return OS_REG_READ(ah, AR_TSF2_L32); 348 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { 388 reg = OS_REG_READ(ah, AR_STA_ID1); 405 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 409 return (OS_REG_READ(ah, AR_TSF_U32) ^ 410 OS_REG_READ(ah, AR_TSF_L32) ^ nf); 427 v = OS_REG_READ(a [all...] |
H A D | ar9300_interrupts.c | 42 host_isr = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE)); 47 host_isr = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE)); 124 async_cause = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE)); 131 (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 134 isr = OS_REG_READ(ah, AR_ISR); 146 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE)) & 164 isr2 = OS_REG_READ(ah, AR_ISR_S2); 194 isr = OS_REG_READ(ah, AR_ISR_RAC); 241 s0 = OS_REG_READ(ah, AR_ISR_S0); 243 s1 = OS_REG_READ(a [all...] |
/freebsd-10-stable/sys/dev/ath/ath_hal/ar5416/ |
H A D | ar5416_eeprom.c | 37 OS_REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); 41 *data = MS(OS_REG_READ(ah, AR_EEPROM_STATUS_DATA),
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H A D | ar5416_gpio.c | 72 tmp = OS_REG_READ(ah, addr); 124 reg = OS_REG_READ(ah, AR_GPIO_OE_OUT); 149 reg = OS_REG_READ(ah, AR_GPIO_OE_OUT); 169 reg = OS_REG_READ(ah, AR_GPIO_IN_OUT); 193 bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9287_GPIO_IN_VAL); 195 bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9285_GPIO_IN_VAL); 197 bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR928X_GPIO_IN_VAL); 199 bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL); 217 val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE), 222 mask = MS(OS_REG_READ(a [all...] |
H A D | ar5416_interrupts.c | 45 isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE); 49 isr = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 86 isr = OS_REG_READ(ah, AR_ISR); 88 if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) && 89 (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON) 90 isr = OS_REG_READ(ah, AR_ISR); 96 o_sync_cause = sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 106 ah->ah_intrstate[1] = OS_REG_READ(ah, AR_ISR_S0); 107 ah->ah_intrstate[2] = OS_REG_READ(ah, AR_ISR_S1); 108 ah->ah_intrstate[3] = OS_REG_READ(a [all...] |
H A D | ar5416_spectral.c | 53 val = OS_REG_READ(ah, AR_PHY_RADAR_0); 67 val = OS_REG_READ(ah, AR_PHY_RADAR_EXT); 70 val = OS_REG_READ(ah, AR_RX_FILTER); 90 val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); 155 val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); 166 val = OS_REG_READ(ah, AR_PHY_RADAR_1); 175 val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); 184 val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); 196 val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); 200 val = OS_REG_READ(a [all...] |
/freebsd-10-stable/sys/dev/ath/ath_hal/ar5212/ |
H A D | ar5212_interrupts.c | 42 return (OS_REG_READ(ah, AR_INTPEND) == AR_INTPEND_TRUE); 61 isr = OS_REG_READ(ah, AR_ISR); 64 uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2); 76 isr = OS_REG_READ(ah, AR_ISR_RAC); 90 isr0 = OS_REG_READ(ah, AR_ISR_S0_S); 93 isr1 = OS_REG_READ(ah, AR_ISR_S1_S); 115 AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S); 116 AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S); 117 AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S); 118 AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(a [all...] |
H A D | ar5212_recv.c | 37 return OS_REG_READ(ath, AR_RXDP); 49 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp); 75 OS_REG_READ(ah, AR_CR), 76 OS_REG_READ(ah, AR_DIAG_SW)); 94 OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 108 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); 134 val = OS_REG_READ(ah, AR_MCAST_FIL1); 137 val = OS_REG_READ(ah, AR_MCAST_FIL0); 154 val = OS_REG_READ(ah, AR_MCAST_FIL1); 157 val = OS_REG_READ(a [all...] |
H A D | ar5212_gpio.c | 48 OS_REG_READ(ah, AR_GPIOCR) | AR_GPIOCR_CR_A(gpio)); 62 (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_CR_A(gpio)) 78 reg = OS_REG_READ(ah, AR_GPIODO); 93 uint32_t val = OS_REG_READ(ah, AR_GPIODI); 110 val = OS_REG_READ(ah, AR_GPIOCR);
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H A D | ar5212_eeprom.c | 48 *data = OS_REG_READ(ah, AR_EEPROM_DATA) & 0xffff;
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H A D | ar5212_power.c | 57 scr = OS_REG_READ(ah, AR_SCR); 61 __func__, scr, OS_REG_READ(ah, AR_PCICFG)); 69 val = OS_REG_READ(ah, AR_PCICFG); 162 return MS(OS_REG_READ(ah, AR_SCR), AR_SCR_SLE); 173 return (OS_REG_READ(ah, AR_PCICFG) & AR_PCICFG_SPWR_DN) != 0;
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/freebsd-10-stable/sys/dev/ath/ath_hal/ar5211/ |
H A D | ar5211_recv.c | 37 return OS_REG_READ(ah, AR_RXDP); 49 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp); 74 , OS_REG_READ(ah, AR_CR) 75 , OS_REG_READ(ah, AR_DIAG_SW) 91 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX)); 101 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX); 126 val = OS_REG_READ(ah, AR_MCAST_FIL1); 129 val = OS_REG_READ(ah, AR_MCAST_FIL0); 146 val = OS_REG_READ(ah, AR_MCAST_FIL1); 149 val = OS_REG_READ(a [all...] |
H A D | ar5211_interrupts.c | 36 return OS_REG_READ(ah, AR_INTPEND) != 0; 53 isr = OS_REG_READ(ah, AR_ISR_RAC); 83 AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S); 84 AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S); 85 AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S); 86 AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S); 87 AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S); 124 (void) OS_REG_READ(ah, AR_IER); /* flush write to HW */
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H A D | ar5211_beacon.c | 39 return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0)); 108 val = OS_REG_READ(ah, AR_STA_ID1); 133 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF); 146 OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF); 162 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
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/freebsd-10-stable/sys/dev/ath/ath_hal/ar5312/ |
H A D | ar5315_gpio.c | 45 (OS_REG_READ(ah, gpioOffset+AR5315_GPIODIR) &~ AR5315_GPIODIR_M(gpio)) 62 (OS_REG_READ(ah, gpioOffset+AR5315_GPIODIR) &~ AR5315_GPIODIR_M(gpio)) 79 reg = OS_REG_READ(ah, gpioOffset+AR5315_GPIODO); 96 uint32_t val = OS_REG_READ(ah, gpioOffset+AR5315_GPIODI); 114 val = OS_REG_READ(ah, gpioOffset+AR5315_GPIOINT);
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/freebsd-10-stable/tools/tools/ath/athregs/ |
H A D | dumpregs.c | 57 #undef OS_REG_READ macro 58 #define OS_REG_READ(ah, off) state.regdata[(off) >> 2] macro 454 fprintf(fd, " %08x", OS_REG_READ(ah, dr->addr)); 472 , r, OS_REG_READ(ah, r) 473 , r+4, OS_REG_READ(ah, r+4) 474 , r+8, OS_REG_READ(ah, r+8) 475 , r+12, OS_REG_READ(ah, r+12) 476 , r+16, OS_REG_READ(ah, r+16) 482 , r, OS_REG_READ(ah, r) 483 , r+4, OS_REG_READ(a [all...] |
/freebsd-10-stable/sys/dev/ath/ath_hal/ar9002/ |
H A D | ar9285_cal.c | 72 regList[i][1] = OS_REG_READ(ah, regList[i][0]); 74 regVal = OS_REG_READ(ah, 0x7834); 77 regVal = OS_REG_READ(ah, 0x9808); 93 ccomp_org = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP); 102 regVal = OS_REG_READ(ah, 0x7834); 106 regVal = OS_REG_READ(ah, 0x7834); 108 reg_field = MS(OS_REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9); 115 reg_field = MS(OS_REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9); 117 offs_6_1 = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS); 118 offs_0 = MS(OS_REG_READ(a [all...] |
H A D | ar9285.c | 46 nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); 54 nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
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H A D | ar9287_cal.c | 59 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
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/freebsd-10-stable/sys/dev/ath/ath_hal/ar5210/ |
H A D | ar5210_recv.c | 37 return OS_REG_READ(ah, AR_RXDP); 71 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) 77 ath_hal_printf(ah, "AR_CR=0x%x\n", OS_REG_READ(ah, AR_CR)); 78 ath_hal_printf(ah, "AR_DIAG_SW=0x%x\n", OS_REG_READ(ah, AR_DIAG_SW)); 90 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX)); 100 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX); 125 val = OS_REG_READ(ah, AR_MCAST_FIL1); 128 val = OS_REG_READ(ah, AR_MCAST_FIL0); 145 val = OS_REG_READ(ah, AR_MCAST_FIL1); 148 val = OS_REG_READ(a [all...] |
H A D | ar5210_misc.c | 70 (void) OS_REG_READ(ah, AR_EP_AIR(off)); /* activate read op */ 77 *data = OS_REG_READ(ah, AR_EP_RDATA) & 0xffff; 166 (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio)) 181 (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio)) 197 reg = OS_REG_READ(ah, AR_GPIODO); 212 uint32_t val = OS_REG_READ(ah, AR_GPIODI); 226 uint32_t val = OS_REG_READ(ah, AR_GPIOCR); 251 val = OS_REG_READ(ah, AR_PCICFG); 275 uint32_t val = OS_REG_READ(ah, AR_STA_ID1); 282 uint32_t val = OS_REG_READ(a [all...] |
H A D | ar5210_beacon.c | 36 return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0)); 99 val = OS_REG_READ(ah, AR_STA_ID1); 127 (OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_DEFAULT_ANTENNA) 141 OS_REG_READ(ah, AR_STA_ID1) &~ (AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF)); 157 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
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