1250003Sadrian/* 2250003Sadrian * Copyright (c) 2013 Qualcomm Atheros, Inc. 3250003Sadrian * 4250003Sadrian * Permission to use, copy, modify, and/or distribute this software for any 5250003Sadrian * purpose with or without fee is hereby granted, provided that the above 6250003Sadrian * copyright notice and this permission notice appear in all copies. 7250003Sadrian * 8250003Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9250003Sadrian * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10250003Sadrian * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11250003Sadrian * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12250003Sadrian * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13250003Sadrian * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14250003Sadrian * PERFORMANCE OF THIS SOFTWARE. 15250003Sadrian */ 16250003Sadrian/* 17250003Sadrian * Copyright (c) 2010 Atheros Communications Inc. 18250003Sadrian * 19250003Sadrian * Permission to use, copy, modify, and/or distribute this software for any 20250003Sadrian * purpose with or without fee is hereby granted, provided that the above 21250003Sadrian * copyright notice and this permission notice appear in all copies. 22250003Sadrian * 23250003Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 24250003Sadrian * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 25250003Sadrian * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 26250003Sadrian * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 27250003Sadrian * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 28250003Sadrian * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 29250003Sadrian * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 30250003Sadrian */ 31250003Sadrian 32250003Sadrian#include "ah.h" 33250003Sadrian#include "ah_internal.h" 34250003Sadrian#include "ar9300phy.h" 35250003Sadrian#include "ar9300reg.h" 36250003Sadrian#include "ar9300eep.h" 37250003Sadrian 38250003Sadrian#ifdef ATH_TX99_DIAG 39250003Sadrianvoid 40250003Sadrianar9300_tx99_tgt_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, u_int32_t txpower) 41250003Sadrian{ 42250003Sadrian#define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s)) 43250003Sadrian static int16_t pPwrArray[ar9300_rate_size] = { 0 }; 44250003Sadrian int32_t i; 45250003Sadrian //u_int8_t ht40PowerIncForPdadc = 2; 46250003Sadrian 47250003Sadrian for (i = 0; i < ar9300_rate_size; i++) 48250003Sadrian pPwrArray[i] = txpower; 49250003Sadrian 50250003Sadrian OS_REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0); 51250003Sadrian 52250003Sadrian /* Write the OFDM power per rate set */ 53250003Sadrian /* 6 (LSB), 9, 12, 18 (MSB) */ 54250003Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1), 55250003Sadrian PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) 56250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) 57250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) 58250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 0) 59250003Sadrian ); 60250003Sadrian /* 24 (LSB), 36, 48, 54 (MSB) */ 61250003Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2), 62250003Sadrian PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_54], 24) 63250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_48], 16) 64250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_36], 8) 65250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 0) 66250003Sadrian ); 67250003Sadrian 68250003Sadrian /* Write the CCK power per rate set */ 69250003Sadrian /* 1L (LSB), reserved, 2L, 2S (MSB) */ 70250003Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3), 71250003Sadrian PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) 72250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) 73250003Sadrian// | PWR_MAS(txPowerTimes2, 8) /* this is reserved for Osprey */ 74250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0) 75250003Sadrian ); 76250003Sadrian /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ 77250003Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4), 78250003Sadrian PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_11S], 24) 79250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_11L], 16) 80250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_5S], 8) 81250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0) 82250003Sadrian ); 83250003Sadrian 84250003Sadrian /* Write the HT20 power per rate set */ 85250003Sadrian /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 86250003Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5), 87250003Sadrian PWR_MAS(pPwrArray[ALL_TARGET_HT20_5], 24) 88250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT20_4], 16) 89250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) 90250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT20_0_8_16], 0) 91250003Sadrian ); 92250003Sadrian 93250003Sadrian /* 6 (LSB), 7, 12, 13 (MSB) */ 94250003Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6), 95250003Sadrian PWR_MAS(pPwrArray[ALL_TARGET_HT20_13], 24) 96250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT20_12], 16) 97250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT20_7], 8) 98250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT20_6], 0) 99250003Sadrian ); 100250003Sadrian 101250003Sadrian /* 14 (LSB), 15, 20, 21 */ 102250003Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10), 103250003Sadrian PWR_MAS(pPwrArray[ALL_TARGET_HT20_21], 24) 104250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT20_20], 16) 105250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT20_15], 8) 106250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT20_14], 0) 107250003Sadrian ); 108250003Sadrian 109250003Sadrian /* Mixed HT20 and HT40 rates */ 110250003Sadrian /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ 111250003Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11), 112250003Sadrian PWR_MAS(pPwrArray[ALL_TARGET_HT40_23], 24) 113250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT40_22], 16) 114250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT20_23], 8) 115250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT20_22], 0) 116250003Sadrian ); 117250003Sadrian 118250003Sadrian /* Write the HT40 power per rate set */ 119250003Sadrian // correct PAR difference between HT40 and HT20/LEGACY 120250003Sadrian /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 121250003Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7), 122250003Sadrian PWR_MAS(pPwrArray[ALL_TARGET_HT40_5], 24) 123250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT40_4], 16) 124250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) 125250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT40_0_8_16], 0) 126250003Sadrian ); 127250003Sadrian 128250003Sadrian /* 6 (LSB), 7, 12, 13 (MSB) */ 129250003Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8), 130250003Sadrian PWR_MAS(pPwrArray[ALL_TARGET_HT40_13], 24) 131250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT40_12], 16) 132250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT40_7], 8) 133250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT40_6], 0) 134250003Sadrian ); 135250003Sadrian 136250003Sadrian /* 14 (LSB), 15, 20, 21 */ 137250003Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(12), 138250003Sadrian PWR_MAS(pPwrArray[ALL_TARGET_HT40_21], 24) 139250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT40_20], 16) 140250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT40_15], 8) 141250003Sadrian | PWR_MAS(pPwrArray[ALL_TARGET_HT40_14], 0) 142250003Sadrian ); 143250003Sadrian#undef PWR_MAS 144250003Sadrian} 145250003Sadrian 146250003Sadrianvoid 147250003Sadrianar9300_tx99_tgt_chainmsk_setup(struct ath_hal *ah, int tx_chainmask) 148250003Sadrian{ 149250003Sadrian if (tx_chainmask == 0x5) { 150250003Sadrian OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 151250003Sadrian } 152250003Sadrian OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask); 153250003Sadrian OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask); 154250003Sadrian 155250003Sadrian OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 156250003Sadrian if (tx_chainmask == 0x5) { 157250003Sadrian OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 158250003Sadrian } 159250003Sadrian} 160250003Sadrian 161250003Sadrianvoid 162250003Sadrianar9300_tx99_tgt_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, int chtype) 163250003Sadrian{ 164250003Sadrian OS_REG_WRITE(ah, AR_PHY_TST_DAC_CONST, OS_REG_READ(ah, AR_PHY_TST_DAC_CONST) | (0x7ff<<11) | 0x7ff); 165250003Sadrian OS_REG_WRITE(ah, AR_PHY_TEST_CTL_STATUS, OS_REG_READ(ah, AR_PHY_TEST_CTL_STATUS) | (1<<7) | (1<<1)); 166250003Sadrian OS_REG_WRITE(ah, AR_PHY_ADDAC_PARA_CTL, (OS_REG_READ(ah, AR_PHY_ADDAC_PARA_CTL) | (1<<31) | (1<<15)) & ~(1<<13)); 167250003Sadrian 168250003Sadrian /* 11G mode */ 169250003Sadrian if (!chtype) 170250003Sadrian { 171250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 172250003Sadrian | (0x1 << 3) | (0x1 << 2)); 173250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 174250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) 175250003Sadrian & ~(0x1 << 4)); 176250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 177250003Sadrian | (0x1 << 26) | (0x7 << 24)) 178250003Sadrian & ~(0x1 << 22)); 179250003Sadrian } else { 180250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP) 181250003Sadrian & ~(0x1 << 4)); 182250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, (OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 183250003Sadrian | (0x1 << 26) | (0x7 << 24)) 184250003Sadrian & ~(0x1 << 22)); 185250003Sadrian } 186250003Sadrian 187250003Sadrian /* chain zero */ 188250003Sadrian if((tx_chain_mask & 0x01) == 0x01) { 189250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 190250003Sadrian | (0x1 << 31) | (0x5 << 15) 191250003Sadrian | (0x3 << 9)) & ~(0x1 << 27) 192250003Sadrian & ~(0x1 << 12)); 193250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 194250003Sadrian | (0x1 << 12) | (0x1 << 10) 195250003Sadrian | (0x1 << 9) | (0x1 << 8) 196250003Sadrian | (0x1 << 7)) & ~(0x1 << 11)); 197250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 198250003Sadrian | (0x1 << 29) | (0x1 << 25) 199250003Sadrian | (0x1 << 23) | (0x1 << 19) 200250003Sadrian | (0x1 << 10) | (0x1 << 9) 201250003Sadrian | (0x1 << 8) | (0x1 << 3)) 202250003Sadrian & ~(0x1 << 28)& ~(0x1 << 24) 203250003Sadrian & ~(0x1 << 22)& ~(0x1 << 7)); 204250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 205250003Sadrian | (0x1 << 23))& ~(0x1 << 21)); 206250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 207250003Sadrian | (0x1 << 12) | (0x1 << 10) 208250003Sadrian | (0x1 << 9) | (0x1 << 8) 209250003Sadrian | (0x1 << 6) | (0x1 << 5) 210250003Sadrian | (0x1 << 4) | (0x1 << 3) 211250003Sadrian | (0x1 << 2)); 212250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) 213250003Sadrian | (0x1 << 31)); 214250003Sadrian } 215250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 216250003Sadrian /* chain one */ 217250003Sadrian if ((tx_chain_mask & 0x02) == 0x02 ) { 218250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 219250003Sadrian | (0x1 << 31) | (0x5 << 15) 220250003Sadrian | (0x3 << 9)) & ~(0x1 << 27) 221250003Sadrian & ~(0x1 << 12)); 222250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 223250003Sadrian | (0x1 << 12) | (0x1 << 10) 224250003Sadrian | (0x1 << 9) | (0x1 << 8) 225250003Sadrian | (0x1 << 7)) & ~(0x1 << 11)); 226250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 227250003Sadrian | (0x1 << 29) | (0x1 << 25) 228250003Sadrian | (0x1 << 23) | (0x1 << 19) 229250003Sadrian | (0x1 << 10) | (0x1 << 9) 230250003Sadrian | (0x1 << 8) | (0x1 << 3)) 231250003Sadrian & ~(0x1 << 28)& ~(0x1 << 24) 232250003Sadrian & ~(0x1 << 22)& ~(0x1 << 7)); 233250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 234250003Sadrian | (0x1 << 23))& ~(0x1 << 21)); 235250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 236250003Sadrian | (0x1 << 12) | (0x1 << 10) 237250003Sadrian | (0x1 << 9) | (0x1 << 8) 238250003Sadrian | (0x1 << 6) | (0x1 << 5) 239250003Sadrian | (0x1 << 4) | (0x1 << 3) 240250003Sadrian | (0x1 << 2)); 241250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) 242250003Sadrian | (0x1 << 31)); 243250003Sadrian } 244250003Sadrian } 245250003Sadrian if (AR_SREV_OSPREY(ah)) { 246250003Sadrian /* chain two */ 247250003Sadrian if ((tx_chain_mask & 0x04) == 0x04 ) { 248250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 249250003Sadrian | (0x1 << 31) | (0x5 << 15) 250250003Sadrian | (0x3 << 9)) & ~(0x1 << 27) 251250003Sadrian & ~(0x1 << 12)); 252250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 253250003Sadrian | (0x1 << 12) | (0x1 << 10) 254250003Sadrian | (0x1 << 9) | (0x1 << 8) 255250003Sadrian | (0x1 << 7)) & ~(0x1 << 11)); 256250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 257250003Sadrian | (0x1 << 29) | (0x1 << 25) 258250003Sadrian | (0x1 << 23) | (0x1 << 19) 259250003Sadrian | (0x1 << 10) | (0x1 << 9) 260250003Sadrian | (0x1 << 8) | (0x1 << 3)) 261250003Sadrian & ~(0x1 << 28)& ~(0x1 << 24) 262250003Sadrian & ~(0x1 << 22)& ~(0x1 << 7)); 263250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 264250003Sadrian | (0x1 << 23))& ~(0x1 << 21)); 265250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 266250003Sadrian | (0x1 << 12) | (0x1 << 10) 267250003Sadrian | (0x1 << 9) | (0x1 << 8) 268250003Sadrian | (0x1 << 6) | (0x1 << 5) 269250003Sadrian | (0x1 << 4) | (0x1 << 3) 270250003Sadrian | (0x1 << 2)); 271250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) 272250003Sadrian | (0x1 << 31)); 273250003Sadrian } 274250003Sadrian } 275250003Sadrian 276250003Sadrian OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0x11111); 277250003Sadrian OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x111); 278250003Sadrian } 279250003Sadrian else 280250003Sadrian { 281250003Sadrian /* chain zero */ 282250003Sadrian if((tx_chain_mask & 0x01) == 0x01) { 283250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 284250003Sadrian | (0x1 << 31) | (0x1 << 27) 285250003Sadrian | (0x3 << 23) | (0x1 << 19) 286250003Sadrian | (0x1 << 15) | (0x3 << 9)) 287250003Sadrian & ~(0x1 << 12)); 288250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 289250003Sadrian | (0x1 << 12) | (0x1 << 10) 290250003Sadrian | (0x1 << 9) | (0x1 << 8) 291250003Sadrian | (0x1 << 7) | (0x1 << 3) 292250003Sadrian | (0x1 << 2) | (0x1 << 1)) 293250003Sadrian & ~(0x1 << 11)& ~(0x1 << 0)); 294250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 295250003Sadrian | (0x1 << 29) | (0x1 << 25) 296250003Sadrian | (0x1 << 23) | (0x1 << 19) 297250003Sadrian | (0x1 << 10) | (0x1 << 9) 298250003Sadrian | (0x1 << 8) | (0x1 << 3)) 299250003Sadrian & ~(0x1 << 28)& ~(0x1 << 24) 300250003Sadrian & ~(0x1 << 22)& ~(0x1 << 7)); 301250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 302250003Sadrian | (0x1 << 23))& ~(0x1 << 21)); 303250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2) 304250003Sadrian | (0x3 << 3) | (0x3 << 0)); 305250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3) 306250003Sadrian | (0x3 << 29) | (0x3 << 26) 307250003Sadrian | (0x2 << 23) | (0x2 << 20) 308250003Sadrian | (0x2 << 17))& ~(0x1 << 14)); 309250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 310250003Sadrian | (0x1 << 12) | (0x1 << 10) 311250003Sadrian | (0x1 << 9) | (0x1 << 8) 312250003Sadrian | (0x1 << 6) | (0x1 << 5) 313250003Sadrian | (0x1 << 4) | (0x1 << 3) 314250003Sadrian | (0x1 << 2)); 315250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) 316250003Sadrian | (0x1 << 31)); 317250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 318250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) 319250003Sadrian & ~(0x1 << 4)); 320250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 321250003Sadrian | (0x1 << 26) | (0x7 << 24) 322250003Sadrian | (0x3 << 22)); 323250003Sadrian } else { 324250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP) 325250003Sadrian & ~(0x1 << 4)); 326250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 327250003Sadrian | (0x1 << 26) | (0x7 << 24) 328250003Sadrian | (0x3 << 22)); 329250003Sadrian } 330250003Sadrian 331250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 332250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 333250003Sadrian | (0x1 << 3) | (0x1 << 2) 334250003Sadrian | (0x1 << 1)) & ~(0x1 << 0)); 335250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 336250003Sadrian | (0x1 << 19) | (0x1 << 3)); 337250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 338250003Sadrian | (0x1 << 23)); 339250003Sadrian } 340250003Sadrian if (AR_SREV_OSPREY(ah)) { 341250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 342250003Sadrian | (0x1 << 3) | (0x1 << 2) 343250003Sadrian | (0x1 << 1)) & ~(0x1 << 0)); 344250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 345250003Sadrian | (0x1 << 19) | (0x1 << 3)); 346250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 347250003Sadrian | (0x1 << 23)); 348250003Sadrian } 349250003Sadrian } 350250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 351250003Sadrian /* chain one */ 352250003Sadrian if ((tx_chain_mask & 0x02) == 0x02 ) { 353250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 354250003Sadrian | (0x1 << 3) | (0x1 << 2) 355250003Sadrian | (0x1 << 1)) & ~(0x1 << 0)); 356250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 357250003Sadrian | (0x1 << 19) | (0x1 << 3)); 358250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 359250003Sadrian | (0x1 << 23)); 360250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 361250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) 362250003Sadrian & ~(0x1 << 4)); 363250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 364250003Sadrian | (0x1 << 26) | (0x7 << 24) 365250003Sadrian | (0x3 << 22)); 366250003Sadrian } else { 367250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP) 368250003Sadrian & ~(0x1 << 4)); 369250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 370250003Sadrian | (0x1 << 26) | (0x7 << 24) 371250003Sadrian | (0x3 << 22)); 372250003Sadrian } 373250003Sadrian 374250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 375250003Sadrian | (0x1 << 31) | (0x1 << 27) 376250003Sadrian | (0x3 << 23) | (0x1 << 19) 377250003Sadrian | (0x1 << 15) | (0x3 << 9)) 378250003Sadrian & ~(0x1 << 12)); 379250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 380250003Sadrian | (0x1 << 12) | (0x1 << 10) 381250003Sadrian | (0x1 << 9) | (0x1 << 8) 382250003Sadrian | (0x1 << 7) | (0x1 << 3) 383250003Sadrian | (0x1 << 2) | (0x1 << 1)) 384250003Sadrian & ~(0x1 << 11)& ~(0x1 << 0)); 385250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 386250003Sadrian | (0x1 << 29) | (0x1 << 25) 387250003Sadrian | (0x1 << 23) | (0x1 << 19) 388250003Sadrian | (0x1 << 10) | (0x1 << 9) 389250003Sadrian | (0x1 << 8) | (0x1 << 3)) 390250003Sadrian & ~(0x1 << 28)& ~(0x1 << 24) 391250003Sadrian & ~(0x1 << 22)& ~(0x1 << 7)); 392250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 393250003Sadrian | (0x1 << 23))& ~(0x1 << 21)); 394250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2, OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2) 395250003Sadrian | (0x3 << 3) | (0x3 << 0)); 396250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3, (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3) 397250003Sadrian | (0x3 << 29) | (0x3 << 26) 398250003Sadrian | (0x2 << 23) | (0x2 << 20) 399250003Sadrian | (0x2 << 17))& ~(0x1 << 14)); 400250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 401250003Sadrian | (0x1 << 12) | (0x1 << 10) 402250003Sadrian | (0x1 << 9) | (0x1 << 8) 403250003Sadrian | (0x1 << 6) | (0x1 << 5) 404250003Sadrian | (0x1 << 4) | (0x1 << 3) 405250003Sadrian | (0x1 << 2)); 406250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) 407250003Sadrian | (0x1 << 31)); 408250003Sadrian 409250003Sadrian if (AR_SREV_OSPREY(ah)) { 410250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 411250003Sadrian | (0x1 << 3) | (0x1 << 2) 412250003Sadrian | (0x1 << 1)) & ~(0x1 << 0)); 413250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 414250003Sadrian | (0x1 << 19) | (0x1 << 3)); 415250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 416250003Sadrian | (0x1 << 23)); 417250003Sadrian } 418250003Sadrian } 419250003Sadrian } 420250003Sadrian if (AR_SREV_OSPREY(ah)) { 421250003Sadrian /* chain two */ 422250003Sadrian if ((tx_chain_mask & 0x04) == 0x04 ) { 423250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 424250003Sadrian | (0x1 << 3) | (0x1 << 2) 425250003Sadrian | (0x1 << 1)) & ~(0x1 << 0)); 426250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 427250003Sadrian | (0x1 << 19) | (0x1 << 3)); 428250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 429250003Sadrian | (0x1 << 23)); 430250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 431250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) 432250003Sadrian & ~(0x1 << 4)); 433250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 434250003Sadrian | (0x1 << 26) | (0x7 << 24) 435250003Sadrian | (0x3 << 22)); 436250003Sadrian } else { 437250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP) 438250003Sadrian & ~(0x1 << 4)); 439250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 440250003Sadrian | (0x1 << 26) | (0x7 << 24) 441250003Sadrian | (0x3 << 22)); 442250003Sadrian } 443250003Sadrian 444250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 445250003Sadrian | (0x1 << 3) | (0x1 << 2) 446250003Sadrian | (0x1 << 1)) & ~(0x1 << 0)); 447250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 448250003Sadrian | (0x1 << 19) | (0x1 << 3)); 449250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 450250003Sadrian | (0x1 << 23)); 451250003Sadrian 452250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 453250003Sadrian | (0x1 << 31) | (0x1 << 27) 454250003Sadrian | (0x3 << 23) | (0x1 << 19) 455250003Sadrian | (0x1 << 15) | (0x3 << 9)) 456250003Sadrian & ~(0x1 << 12)); 457250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 458250003Sadrian | (0x1 << 12) | (0x1 << 10) 459250003Sadrian | (0x1 << 9) | (0x1 << 8) 460250003Sadrian | (0x1 << 7) | (0x1 << 3) 461250003Sadrian | (0x1 << 2) | (0x1 << 1)) 462250003Sadrian & ~(0x1 << 11)& ~(0x1 << 0)); 463250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 464250003Sadrian | (0x1 << 29) | (0x1 << 25) 465250003Sadrian | (0x1 << 23) | (0x1 << 19) 466250003Sadrian | (0x1 << 10) | (0x1 << 9) 467250003Sadrian | (0x1 << 8) | (0x1 << 3)) 468250003Sadrian & ~(0x1 << 28)& ~(0x1 << 24) 469250003Sadrian & ~(0x1 << 22)& ~(0x1 << 7)); 470250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 471250003Sadrian | (0x1 << 23))& ~(0x1 << 21)); 472250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2, OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2) 473250003Sadrian | (0x3 << 3) | (0x3 << 0)); 474250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3, (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3) 475250003Sadrian | (0x3 << 29) | (0x3 << 26) 476250003Sadrian | (0x2 << 23) | (0x2 << 20) 477250003Sadrian | (0x2 << 17))& ~(0x1 << 14)); 478250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 479250003Sadrian | (0x1 << 12) | (0x1 << 10) 480250003Sadrian | (0x1 << 9) | (0x1 << 8) 481250003Sadrian | (0x1 << 6) | (0x1 << 5) 482250003Sadrian | (0x1 << 4) | (0x1 << 3) 483250003Sadrian | (0x1 << 2)); 484250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) 485250003Sadrian | (0x1 << 31)); 486250003Sadrian } 487250003Sadrian } 488250003Sadrian 489250003Sadrian OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0x22222); 490250003Sadrian OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x222); 491250003Sadrian } 492250003Sadrian} 493250003Sadrian 494250003Sadrianvoid 495250003Sadrianar9300_tx99_tgt_start(struct ath_hal *ah, u_int8_t data) 496250003Sadrian{ 497250003Sadrian a_uint32_t val; 498250003Sadrian a_uint32_t qnum = (a_uint32_t)data; 499250003Sadrian 500250003Sadrian /* Disable AGC to A2 */ 501250003Sadrian OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR) ); 502250003Sadrian OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000); 503250003Sadrian OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe); 504250003Sadrian OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 505250003Sadrian //OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_FORCE_RX_CLEAR+AR_DIAG_IGNORE_VIRT_CS)); 506250003Sadrian OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); // set receive disable 507250003Sadrian //set CW_MIN and CW_MAX both to 0, AIFS=2 508250003Sadrian OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 509250003Sadrian OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); //50 OK 510250003Sadrian OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); 511250003Sadrian OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400); //200 ok for HT20, 400 ok for HT40 512250003Sadrian OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 513250003Sadrian 514250003Sadrian /* set QCU modes to early termination */ 515250003Sadrian val = OS_REG_READ(ah, AR_QMISC(qnum)); 516250003Sadrian OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ); 517250003Sadrian} 518250003Sadrian 519250003Sadrianvoid 520250003Sadrianar9300_tx99_tgt_stop(struct ath_hal *ah) 521250003Sadrian{ 522250003Sadrian OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR); 523250003Sadrian OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ (AR_DIAG_FORCE_RX_CLEAR | AR_DIAG_IGNORE_VIRT_CS)); 524250003Sadrian} 525250003Sadrian#endif 526