Searched refs:FPSCR (Results 1 - 4 of 4) sorted by relevance
| /freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 123 Reserved.set(ARM::FPSCR);
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| H A D | ARMISelLowering.cpp | 3960 // The rounding mode is in bits 23:22 of the FPSCR.
3962 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3965 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, local
3968 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
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| /freebsd-10-stable/contrib/gdb/gdb/ |
| H A D | rs6000-nat.c | 179 return FPSCR;
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| /freebsd-10-stable/contrib/binutils/gas/config/ |
| H A D | tc-arm.c | 7118 first_error (_("operand 1 must be FPSCR"));
14556 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
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