Searched refs:reg (Results 1 - 25 of 92) sorted by relevance

1234

/barrelfish-master/include/arch/powerpc64/arch/
H A Dasm.h47 * LD_ADDR ( reg, symbol )
48 * loads the address of symbol into reg
50 #define LD_ADDR(reg, symbol) \
51 lis reg, symbol##@highest; \
52 ori reg, reg, symbol##@higher; \
53 rldicr reg, reg, 32,31; \
54 oris reg, reg, symbo
[all...]
/barrelfish-master/usr/drivers/solarflare/
H A Dbuffer_tbl.c31 uint64_t reg = 0; local
38 reg = 0;
39 reg = sfn5122f_buf_full_tbl_buf_adr_region_insert(reg, 0 );
40 reg = sfn5122f_buf_full_tbl_buf_adr_fbuf_insert(reg,
43 reg = sfn5122f_buf_full_tbl_buf_owner_id_fbuf_insert(reg, qid+1);
49 reg = sfn5122f_buf_full_tbl_buf_owner_id_fbuf_insert(reg,
82 uint64_t reg; local
[all...]
H A Dmcdi_rpc.c49 uint32_t reg = 0; local
83 reg = sfn5122f_mc_treg_smem_rd(d, offset);
84 // If the reg is 0xffffffff the memory resets
85 if (reg != 0xffffffff && ((reg >> 23) & 0x001))
89 error = (reg >> 22) & 0x001;
90 rlen = (reg >> 8) & 0x0FF;
96 reg = sfn5122f_mc_treg_smem_rd(d,offset+1);
97 DEBUG("AN ERROR OCCURRED: CMD %d, ERROR %d \n",cmd , reg);
98 switch(reg){
[all...]
H A Dsfn5122f_cdriver.c462 uint32_t reg; local
470 reg = MTU_MAX;
471 memcpy(in + CMD_SET_MAC_IN_MTU_OFFSET , &reg, 4);
496 uint64_t reg; local
512 reg = MTU_MAX;
513 memcpy(in + CMD_SET_MAC_IN_MTU_OFFSET , &reg, 4);
538 uint64_t reg = 0; local
551 reg = sfn5122f_mc_treg_smem_rd(st->d,offset);
552 if (reg != 0) {
684 uint64_t reg, reg local
824 uint64_t reg; local
889 uint64_t reg = 0; local
949 uint64_t reg, buffer_offset; local
1075 uint64_t reg, reg1, buffer_offset; local
[all...]
/barrelfish-master/usr/drivers/iommu/modules/intel_vtd/
H A Dintel_vtd_ctxt_cache.h20 static inline void vtd_ctxt_cache_do_invalidate(vtd_t *vtd, vtd_CCMD_t reg) argument
23 reg = vtd_CCMD_icc_insert(reg, 1);
24 vtd_CCMD_wr(vtd, reg);
41 vtd_CCMD_t reg = vtd_CCMD_default; local
42 reg = vtd_CCMD_cirg_insert(reg, vtd_gir);
44 vtd_ctxt_cache_do_invalidate(&vtd->vtd_dev, reg);
55 vtd_CCMD_t reg = vtd_CCMD_default; local
56 reg
71 vtd_CCMD_t reg = vtd_CCMD_default; local
[all...]
/barrelfish-master/lib/cpuid/
H A Dcpuid_amd.h23 struct cpuid_regs reg = CPUID_REGS_INITIAL(0, 0); local
24 cpuid_exec(&reg);
26 return (strncmp((char *)&reg.ebx, CPUID_VENDOR_STRING_AMD, 12) == 0);
H A Dcpuid_intel.h24 struct cpuid_regs reg = CPUID_REGS_INITIAL(0, 0); local
25 cpuid_exec(&reg);
27 return (strncmp((char *)&reg.ebx, CPUID_VENDOR_STRING_INTEL, 12) == 0);
H A Dcpuid_internal.h20 * \param reg cpuid_regs struct to store the result value
22 * the reg parameter is used to supply the function & argument information and
25 static inline void cpuid_exec(struct cpuid_regs *reg) argument
27 if (reg == NULL) {
32 : "=a" (reg->eax), "=b" (reg->ebx),
33 "=c" (reg->ecx), "=d" (reg->edx)
34 : "a" (reg->eax), "c" (reg
[all...]
H A Dcpuid_amd.c65 struct cpuid_regs reg = CPUID_REGS_INITIAL(0x80000002, 0); local
66 cpuid_exec(&reg);
67 written = snprintf(buf, len, "%s", (char *)&reg.eax);
71 reg.eax = 0x80000003;
72 reg.ecx = 0x0;
73 cpuid_exec(&reg);
74 written = snprintf(buf, len, "%s", (char *)&reg.eax);
78 reg.eax = 0x80000004;
79 reg.ecx = 0x0;
80 cpuid_exec(&reg);
94 struct cpuid_regs reg = CPUID_REGS_INITIAL(1, 0); local
120 struct cpuid_regs reg = CPUID_REGS_INITIAL(0, 0); local
128 struct cpuid_regs reg = CPUID_REGS_INITIAL(0x80000000, 0); local
162 struct cpuid_regs reg = CPUID_REGS_INITIAL(fn, 0); local
234 struct cpuid_regs reg = CPUID_REGS_INITIAL(0x8000001d, idx); local
290 struct cpuid_regs reg = CPUID_REGS_INITIAL(1, 0); local
309 struct cpuid_regs reg = CPUID_REGS_INITIAL(0x80000005, 0); local
395 struct cpuid_regs reg = CPUID_REGS_INITIAL(0x01, 0); local
465 struct cpuid_regs reg = CPUID_REGS_INITIAL(0x80000008, 0); local
[all...]
/barrelfish-master/include/arch/x86_32/barrelfish_kpi/
H A Dpic_arch.h23 # define DEREF_EXTERN(reg) movl (reg), reg
32 # define DEREF_EXTERN(reg)
/barrelfish-master/lib/net/
H A Dnetbufs.c90 struct net_buf_region *reg = calloc(1, sizeof(struct net_buf_region)); local
91 if (reg == NULL) {
95 reg->buffer_size = ROUND_UP(buffersize, NETWORKING_BUFFER_ALIGN);
96 reg->buffer_shift = 0;
97 while(!((reg->buffer_size >> reg->buffer_shift) & 0x1)) {
98 reg->buffer_shift++;
101 reg->framecap = frame;
102 reg->pool = bp;
104 err = frame_identify(reg
285 struct net_buf_region *reg = bp->regions; local
[all...]
/barrelfish-master/lib/libc/aarch64/sys/
H A D__vdso_gettc.c43 uint64_t reg; local
45 __asm __volatile("mrs %0, cntvct_el0" : "=r" (reg));
46 return (reg);
52 uint64_t reg; local
54 __asm __volatile("mrs %0, cntpct_el0" : "=r" (reg));
55 return (reg);
/barrelfish-master/lib/libc/arm/sys/
H A D__vdso_gettc.c45 uint64_t reg; local
47 __asm __volatile("mrrc\tp15, 1, %Q0, %R0, c14" : "=r" (reg));
48 return (reg);
54 uint64_t reg; local
56 __asm __volatile("mrrc\tp15, 0, %Q0, %R0, c14" : "=r" (reg));
57 return (reg);
/barrelfish-master/kernel/arch/arm/
H A Dgic_v3.c106 armv8_ICC_SGI1R_EL1_t reg = 0; local
107 reg = armv8_ICC_SGI1R_EL1_INTID_insert(reg, 1);
109 reg = armv8_ICC_SGI1R_EL1_TargetList_insert(reg, 1<<cpuid);
110 reg = armv8_ICC_SGI1R_EL1_Aff3_insert(reg, 0);
111 reg = armv8_ICC_SGI1R_EL1_Aff2_insert(reg, 0);
112 reg
[all...]
/barrelfish-master/usr/arrakismon/
H A Dvmx.h41 * Write the selector, base and limit to a selector reg according to real-mode
45 #define VMCS_WRITE_SEGREG_REALMODE(dcb_cap,reg,selector) \
47 errval_t err_val = invoke_dispatcher_vmwrite(dcb_cap, VMX_GUEST_ ##reg## _SEL, (selector)); \
48 err_val += invoke_dispatcher_vmwrite(dcb_cap, VMX_GUEST_ ##reg## _BASE, (selector) << 4); \
49 err_val += invoke_dispatcher_vmwrite(dcb_cap, VMX_GUEST_ ##reg## _LIM, ((selector) << 4) + 0xffff); \
H A Dsvm.h50 * Write the selector, base and limit to a selector reg according to real-mode
53 #define VMCB_WRITE_SEGREG_REALMODE(vmcb,reg,selector) \
55 amd_vmcb_ ##reg## _selector_wr((vmcb), (selector)); \
56 amd_vmcb_ ##reg## _base_wr((vmcb), (selector) << 4); \
57 amd_vmcb_ ##reg## _limit_wr((vmcb), ((selector) << 4) + 0xffff); \
H A Dlpc.c194 cycle_counter_access_byte (struct lpc *l, int reg) argument
197 if (l->sbytes[reg].u.rw_mode == TCW_RW_LSB_MSB) {
198 switch (l->counter_current_byte[reg]) {
200 l->counter_current_byte[reg] = LPC_PIT_MSB;
203 l->counter_current_byte[reg] = LPC_PIT_LSB;
213 timer_countdown_reg_read (struct lpc *l, int reg)
217 assert(l->counters_next_byte[reg] != LPC_PIT_NONE);
220 if (l->counters_next_byte[reg] != LPC_PIT_LSB) {
221 ret = l->counters[reg] & 0xff;
222 } else if (l->counters_next_byte[reg] !
233 pit_write_current_byte(struct lpc *l, int reg, uint16_t src, uint8_t *dest) argument
246 pit_counter_read(struct lpc *l, int reg) argument
456 int reg; local
493 timer_countdown_reg_write(struct lpc *l, int reg, uint8_t val) argument
[all...]
/barrelfish-master/usr/vmkitmon/
H A Dsvm.h50 * Write the selector, base and limit to a selector reg according to real-mode
53 #define VMCB_WRITE_SEGREG_REALMODE(vmcb,reg,selector) \
55 amd_vmcb_ ##reg## _selector_wr((vmcb), (selector)); \
56 amd_vmcb_ ##reg## _base_wr((vmcb), (selector) << 4); \
57 amd_vmcb_ ##reg## _limit_wr((vmcb), ((selector) << 4) + 0xffff); \
H A Dvmx.h41 * Write the selector, base and limit to a selector reg according to real-mode
45 #define VMCS_WRITE_SEGREG_REALMODE(dcb_cap,reg,selector) \
47 errval_t err_val = invoke_dispatcher_vmwrite(dcb_cap, VMX_GUEST_ ##reg## _SEL, (selector)); \
48 err_val += invoke_dispatcher_vmwrite(dcb_cap, VMX_GUEST_ ##reg## _BASE, (selector) << 4); \
49 err_val += invoke_dispatcher_vmwrite(dcb_cap, VMX_GUEST_ ##reg## _LIM, ((selector) << 4) + 0xffff); \
H A Dlpc.c204 cycle_counter_access_byte (struct lpc *l, int reg) argument
207 if (l->sbytes[reg].u.rw_mode == TCW_RW_LSB_MSB) {
208 switch (l->counter_current_byte[reg]) {
210 l->counter_current_byte[reg] = LPC_PIT_MSB;
213 l->counter_current_byte[reg] = LPC_PIT_LSB;
223 timer_countdown_reg_read (struct lpc *l, int reg)
227 assert(l->counters_next_byte[reg] != LPC_PIT_NONE);
230 if (l->counters_next_byte[reg] != LPC_PIT_LSB) {
231 ret = l->counters[reg] & 0xff;
232 } else if (l->counters_next_byte[reg] !
243 pit_write_current_byte(struct lpc *l, int reg, uint16_t src, uint8_t *dest) argument
256 pit_counter_read(struct lpc *l, int reg) argument
464 int reg; local
501 timer_countdown_reg_write(struct lpc *l, int reg, uint8_t val) argument
[all...]
/barrelfish-master/lib/cxx/unwind/
H A DDwarfParser.hpp388 uint64_t reg;
426 reg = addressSpace.getULEB128(p, instructionsEnd);
429 if (reg > kMaxRegisterNumber) {
431 "malformed DW_CFA_offset_extended DWARF unwind, reg too big");
434 results->savedRegisters[reg].location = kRegisterInCFA;
435 results->savedRegisters[reg].value = offset;
436 _LIBUNWIND_TRACE_DWARF("DW_CFA_offset_extended(reg=%" PRIu64 ", "
438 reg, offset);
441 reg = addressSpace.getULEB128(p, instructionsEnd);
442 if (reg > kMaxRegisterNumbe
[all...]
/barrelfish-master/usr/drivers/enet/
H A Denet_module.c50 enet_mmfr_t reg = 0; local
51 reg = enet_mmfr_pa_insert(reg, phyaddr);
52 reg = enet_mmfr_ra_insert(reg, regaddr);
53 reg = enet_mmfr_data_insert(reg, data);
54 reg = enet_mmfr_st_insert(reg, 0x1);
55 reg
84 enet_mmfr_t reg = 0; local
453 uint64_t reg; local
509 uint64_t reg; local
555 uint64_t reg; local
[all...]
/barrelfish-master/usr/eclipseclp/lib_tcl/
H A Dexample_multi.tcl71 ;# toggle the .reg button
72 .reg configure -command {deregister_for_multi}
73 .reg configure -text "Deregister multitasking"
78 ;# toggle the .reg button
79 .reg configure -command {register_for_multi}
80 .reg configure -text "Register multitasking"
139 .reg configure -state normal
145 .reg configure -state disabled
156 pack [button .reg -state disabled]
/barrelfish-master/lib/barrelfish/arch/arm/
H A Ddebug.c17 #define dpr(reg) debug_printf("%-6s 0x%08"PRIx32 "\n", #reg, archregs->named. reg)
18 #define dpd(reg) debug_printf("%-6s 0x%016"PRIx64 "\n", #reg, archregs->named. reg)
/barrelfish-master/usr/tests/hellotest/
H A Dhellotest.c16 __asm volatile("mov %%cs, %[reg]"
17 : [reg] "=r" (cs));
24 __asm volatile("mov %%cr0, %[reg]"
25 : [reg] "=r" (cr0));

Completed in 219 milliseconds

1234