/barrelfish-master/lib/devif/backends/net/mlx4/drivers/net/mlx4/ |
H A D | cq.c | 66 void mlx4_cq_completion(struct mlx4_priv *priv, u32 cqn) { argument 73 cqn & (priv->dev.caps.num_cqs - 1)); 80 MLX4_DEBUG("Completion event for bogus CQ %08x\n", cqn); 94 void mlx4_cq_event(struct mlx4_priv *priv, u32 cqn, int event_type) 101 cq = radix_tree_lookup(&cq_table->tree, cqn & (priv->dev.caps.num_cqs - 1)); 108 MLX4_DEBUG( "Async event for bogus CQ %08x\n", cqn); 155 err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 1); 183 err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 0); 204 err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 3); 212 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn) { argument 236 mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn) argument [all...] |
H A D | en_resources.c | 47 int is_tx, int rss, int qpn, int cqn, int user_prio, 79 context->cqn_send = cpu_to_be32(cqn); 80 context->cqn_recv = cpu_to_be32(cqn); 46 mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, int is_tx, int rss, int qpn, int cqn, int user_prio, struct mlx4_qp_context *context) argument
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H A D | en_netdev.c | 1638 priv->rx_ring[i]->cqn = cq->mcq.cqn; 1689 err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn,
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H A D | mlx4_en.h | 264 u16 cqn; member in struct:mlx4_en_tx_ring 325 u16 cqn; /* index of port CQ associated with this ring*/ member in struct:mlx4_en_rx_ring 815 int is_tx, int rss, int qpn, int cqn, int user_prio,
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H A D | en_rx.c | 407 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; 855 ring->cqn, -1, context); 953 priv->rx_ring[0]->cqn, -1, &context);
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H A D | en_tx.c | 246 ring->cqn = cq; 258 ring->cqn, user_prio, &ring->context);
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H A D | mlx4.h | 930 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 932 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 1179 void mlx4_cq_completion(struct mlx4_priv *priv, uint32_t cqn); 1181 void mlx4_cq_event(struct mlx4_dev *dev, uint32_t cqn, int event_type);
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H A D | mlx4_devif_queue.c | 1781 int cqn; local 1808 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; 1809 mlx4_cq_completion(priv, cqn); 1950 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); 1954 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff, &slave); 1968 mlx4_cq_event(priv, be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff,
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/barrelfish-master/lib/devif/backends/net/mlx4/drivers/infiniband/hw/mthca/ |
H A D | mthca_cq.c | 75 __be32 cqn; member in struct:mthca_cq_context 210 mthca_write64(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn, incr - 1, 221 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn) argument 225 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1)); 228 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn); 237 void mthca_cq_event(struct mthca_dev *dev, u32 cqn, argument 245 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1)); 252 mthca_warn(dev, "Async event for bogus CQ %08x\n", cqn); 301 qpn, cq->cqn, cq->cons_index, prod_index); 388 cq->cqn, c [all...] |
H A D | mthca_user.h | 83 __u32 cqn; member in struct:mthca_create_cq_resp
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H A D | mthca_eq.c | 131 __be32 cqn; member in struct:mthca_eqe::__anon693::__anon694 148 __be32 cqn; member in struct:mthca_eqe::__anon693::__anon698 218 static inline void disarm_cq(struct mthca_dev *dev, int eqn, int cqn) argument 221 mthca_write64(MTHCA_EQ_DB_DISARM_CQ | eqn, cqn, 275 disarm_cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; 342 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); 343 mthca_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn),
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H A D | mthca_provider.h | 140 * a qp may be locked, with the cq with the lower cqn locked first. 204 int cqn; member in struct:mthca_cq
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H A D | mthca_dev.h | 503 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn); 504 void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
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H A D | mthca_qp.c | 726 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn); 765 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn); 1332 else if (send_cq->cqn < recv_cq->cqn) { 1345 else if (send_cq->cqn < recv_cq->cqn) {
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H A D | mthca_provider.c | 727 if (context && ib_copy_to_udata(udata, &cq->cqn, sizeof (__u32))) { 830 ret = mthca_RESIZE_CQ(dev, cq->cqn, lkey, ilog2(entries), &status);
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/barrelfish-master/lib/devif/backends/net/mlx4/drivers/infiniband/hw/mlx4/ |
H A D | user.h | 80 __u32 cqn; member in struct:mlx4_ib_create_cq_resp
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H A D | srq.c | 79 u32 cqn; local 179 cqn = (init_attr->srq_type == IB_SRQT_XRC) ? 180 to_mcq(init_attr->ext.xrc.cq)->mcq.cqn : 0; 184 err = mlx4_srq_alloc(dev->dev, to_mpd(pd)->pdn, cqn, xrcdn, &srq->mtt,
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H A D | cq.c | 63 "on CQ %06x\n", type, cq->cqn); 243 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32 ))) { 652 MLX4_WARN("CQ %06x with entry for unknown QPN %06x\n", cq->mcq.cqn,
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H A D | qp.c | 1126 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1142 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1867 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn); 1868 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
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/barrelfish-master/lib/devif/backends/net/mlx4/include/linux/mlx4/ |
H A D | cq.h | 163 doorbell[0] = cpu_to_be32(sn << 28 | cmd | cq->cqn);
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H A D | device.h | 649 int cqn; member in struct:mlx4_cq 866 __be32 cqn; member in struct:mlx4_eqe::__anon810::__anon811 883 __be32 cqn; member in struct:mlx4_eqe::__anon810::__anon815 1107 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
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