1#define MLX4_PCI_VENDOR_ID 0x15b3 2 3/* 4 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 5 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 6 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 7 * Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies. All rights reserved. 8 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 9 * 10 * This software is available to you under a choice of one of two 11 * licenses. You may choose to be licensed under the terms of the GNU 12 * General Public License (GPL) Version 2, available from the file 13 * COPYING in the main directory of this source tree, or the 14 * OpenIB.org BSD license below: 15 * 16 * Redistribution and use in source and binary forms, with or 17 * without modification, are permitted provided that the following 18 * conditions are met: 19 * 20 * - Redistributions of source code must retain the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer. 23 * 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials 27 * provided with the distribution. 28 * 29 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 30 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 31 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 32 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 33 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 34 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 35 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 36 * SOFTWARE. 37 */ 38 39#ifndef MLX4_H 40#define MLX4_H 41 42/*#include <linux/mutex.h>*/ 43/* 44 #include <linux/radix-tree.h> 45 #include <linux/timer.h> 46 #include <linux/semaphore.h> 47 */ 48/*#include <linux/workqueue.h>*/ 49#include <linux/device.h> 50#include <linux/io-mapping.h> 51#include <linux/mlx4/device.h> 52 53#include <barrelfish/thread_sync.h> 54 55#include <linux/rbtree.h> 56 57#include <sys/_pthreadtypes.h> 58 59#include <asm/atomic.h> 60/*#include <linux/mlx4/driver.h>*/ 61/* 62 #include <linux/mlx4/doorbell.h> 63 #include <linux/mlx4/cmd.h> 64 */ 65 66#define DRV_NAME "mlx4_core" 67#define PFX DRV_NAME ": " 68#define DRV_VERSION "2.1.6" 69#define DRV_RELDATE __DATE__ 70 71#define DRV_STACK_NAME "Linux-MLNX_OFED" 72#define DRV_STACK_VERSION "2.1" 73#define DRV_NAME_FOR_FW DRV_STACK_NAME","DRV_STACK_VERSION 74 75#define MLX4_FS_UDP_UC_EN (1 << 1) 76#define MLX4_FS_TCP_UC_EN (1 << 2) 77#define MLX4_FS_NUM_OF_L2_ADDR 8 78#define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 79#define MLX4_FS_NUM_MCG (1 << 17) 80/* 81 struct mlx4_set_port_prio2tc_context { 82 uint8_t prio2tc[4]; 83 }; 84 85 struct mlx4_port_scheduler_tc_cfg_be { 86 __be16 pg; 87 __be16 bw_precentage; 88 __be16 max_bw_units; 3-100Mbps, 4-1Gbps, other values - reserved 89 __be16 max_bw_value; 90 }; 91 92 struct mlx4_set_port_scheduler_context { 93 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC]; 94 }; 95 */ 96 97extern bool got_irq; 98 99enum { 100 MLX4_HCR_BASE = 0x80680, 101 MLX4_HCR_SIZE = 0x0001c, 102 MLX4_CLR_INT_SIZE = 0x00008, 103 MLX4_SLAVE_COMM_BASE = 0x0, 104 MLX4_COMM_PAGESIZE = 0x1000, 105 MLX4_CLOCK_SIZE = 0x00008 106}; 107 108enum { 109 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10, 110 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7, 111 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12, 112 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2), 113}; 114 115enum { 116 MLX4_NUM_PDS = 1 << 15 117}; 118 119enum { 120 MLX4_CMPT_TYPE_QP = 0, 121 MLX4_CMPT_TYPE_SRQ = 1, 122 MLX4_CMPT_TYPE_CQ = 2, 123 MLX4_CMPT_TYPE_EQ = 3, 124 MLX4_CMPT_NUM_TYPE 125}; 126 127enum { 128 MLX4_CMPT_SHIFT = 24, MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 129}; 130 131enum mlx4_mpt_state { 132 MLX4_MPT_DISABLED = 0, MLX4_MPT_EN_HW, MLX4_MPT_EN_SW 133}; 134 135#define MLX4_COMM_TIME 10000 136enum { 137 MLX4_COMM_CMD_RESET, 138 MLX4_COMM_CMD_VHCR0, 139 MLX4_COMM_CMD_VHCR1, 140 MLX4_COMM_CMD_VHCR2, 141 MLX4_COMM_CMD_VHCR_EN, 142 MLX4_COMM_CMD_VHCR_POST, 143 MLX4_COMM_CMD_FLR = 254 144}; 145 146/*The flag indicates that the slave should delay the RESET cmd*/ 147#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 148/*indicates how many retries will be done if we are in the middle of FLR*/ 149#define NUM_OF_RESET_RETRIES 10 150#define SLEEP_TIME_IN_RESET (2 * 1000) 151 152enum mlx4_resource { 153 RES_QP, 154 RES_CQ, 155 RES_SRQ, 156 RES_XRCD, 157 RES_MPT, 158 RES_MTT, 159 RES_MAC, 160 RES_VLAN, 161 RES_NPORT_ID, 162 RES_COUNTER, 163 RES_FS_RULE, 164 RES_EQ, 165 MLX4_NUM_OF_RESOURCE_TYPE 166}; 167 168enum mlx4_alloc_mode { 169 RES_OP_RESERVE, RES_OP_RESERVE_AND_MAP, RES_OP_MAP_ICM, 170}; 171 172enum mlx4_res_tracker_free_type { 173 RES_TR_FREE_ALL, RES_TR_FREE_SLAVES_ONLY, RES_TR_FREE_STRUCTS_ONLY, 174}; 175 176/* 177 *Virtual HCR structures. 178 * mlx4_vhcr is the sw representation, in machine endianess 179 * 180 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 181 * to FW to go through communication channel. 182 * It is big endian, and has the same structure as the physical HCR 183 * used by command interface 184 185 struct mlx4_vhcr { 186 uint64_t in_param; 187 uint64_t out_param; 188 uint32_t in_modifier; 189 uint32_t errno; 190 u16 op; 191 u16 token; 192 uint8_t op_modifier; 193 uint8_t e_bit; 194 }; 195 196 struct mlx4_vhcr_cmd { 197 __be64 in_param; 198 __be32 in_modifier; 199 uint32_t reserved1; 200 __be64 out_param; 201 __be16 token; 202 u16 reserved; 203 uint8_t status; 204 uint8_t flags; 205 __be16 opcode; 206 } __packed; 207 208 struct mlx4_cmd_info { 209 u16 opcode; 210 bool has_inbox; 211 bool has_outbox; 212 bool out_is_imm; 213 bool encode_slave_id; 214 bool skip_err_print; 215 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 216 struct mlx4_cmd_mailbox *inbox); 217 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 218 struct mlx4_cmd_mailbox *inbox, 219 struct mlx4_cmd_mailbox *outbox, 220 struct mlx4_cmd_info *cmd); 221 }; 222 223 enum { 224 MLX4_DEBUG_MASK_CMD_TIME = 0x100, 225 }; 226 227 #ifdef CONFIG_MLX4_DEBUG 228 extern int mlx4_debug_level; 229 #else CONFIG_MLX4_DEBUG 230 #define mlx4_debug_level (0) 231 #endif CONFIG_MLX4_DEBUG 232 233 #define mlx4_dbg(mdev, format, arg...) \ 234do { \ 235 if (mlx4_debug_level) \ 236 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \ 237} while (0) 238 239 #define mlx4_err(mdev, format, arg...) \ 240 dev_err(&mdev->pdev->dev, format, ##arg) 241 #define mlx4_info(mdev, format, arg...) \ 242 dev_info(&mdev->pdev->dev, format, ##arg) 243 #define mlx4_warn(mdev, format, arg...) \ 244 dev_warn(&mdev->pdev->dev, format, ##arg) 245 246 extern int mlx4_log_num_mgm_entry_size; 247 */ 248extern int log_mtts_per_seg; 249extern int mlx4_blck_lb; 250/* 251 extern int mlx4_set_4k_mtu; 252 */ 253#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF) 254#define ALL_SLAVES 0xff 255 256struct mlx4_bitmap { 257 uint32_t last; 258 uint32_t top; 259 uint32_t max; 260 uint32_t reserved_top; 261 uint32_t mask; 262 uint32_t avail; 263 struct thread_mutex lock; 264 unsigned long *table; 265}; 266 267struct mlx4_buddy { 268 unsigned long **bits; 269 unsigned int *num_free; 270 uint32_t max_order; 271 spinlock_t lock; 272}; 273 274struct mlx4_icm; 275 276struct mlx4_icm_table { 277 uint64_t virt; 278 int num_icm; 279 uint32_t num_obj; 280 int obj_size; 281 int lowmem; 282 int coherent; 283 struct thread_mutex mutex; 284 struct mlx4_icm **icm; 285}; 286 287#define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28) 288#define MLX4_MPT_FLAG_FREE (0x3UL << 28) 289#define MLX4_MPT_FLAG_MIO (1 << 17) 290#define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15) 291#define MLX4_MPT_FLAG_PHYSICAL (1 << 9) 292#define MLX4_MPT_FLAG_REGION (1 << 8) 293 294#define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27) 295#define MLX4_MPT_PD_FLAG_RAE (1 << 28) 296#define MLX4_MPT_PD_FLAG_EN_INV (3 << 24) 297 298#define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7) 299 300#define MLX4_MPT_STATUS_SW 0xF0 301#define MLX4_MPT_STATUS_HW 0x00 302 303/** Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.*/ 304 305struct mlx4_mpt_entry { 306 __be32 flags; 307 __be32 qpn; 308 __be32 key; 309 __be32 pd_flags; 310 __be64 start; 311 __be64 length; 312 __be32 lkey; 313 __be32 win_cnt; 314 uint8_t reserved1[3]; 315 uint8_t mtt_rep; 316 __be64 mtt_addr; 317 __be32 mtt_sz; 318 __be32 entity_size; 319 __be32 first_byte_offset; 320} __packed; 321 322/** Must be packed because start is 64 bits but only aligned to 32 bits.*/ 323 324struct mlx4_eq_context { 325 __be32 flags; 326 u16 reserved1[3]; 327 __be16 page_offset; 328 uint8_t log_eq_size; 329 uint8_t reserved2[4]; 330 uint8_t eq_period; 331 uint8_t reserved3; 332 uint8_t eq_max_count; 333 uint8_t reserved4[3]; 334 uint8_t intr; 335 uint8_t log_page_size; 336 uint8_t reserved5[2]; 337 uint8_t mtt_base_addr_h; 338 __be32 mtt_base_addr_l; 339 uint32_t reserved6[2]; 340 __be32 consumer_index; 341 __be32 producer_index; 342 uint32_t reserved7[4]; 343}; 344 345struct mlx4_cq_context { 346 __be32 flags; 347 u16 reserved1[3]; 348 __be16 page_offset; 349 __be32 logsize_usrpage; 350 __be16 cq_period; 351 __be16 cq_max_count; 352 uint8_t reserved2[3]; 353 uint8_t comp_eqn; 354 uint8_t log_page_size; 355 uint8_t reserved3[2]; 356 uint8_t mtt_base_addr_h; 357 __be32 mtt_base_addr_l; 358 __be32 last_notified_index; 359 __be32 solicit_producer_index; 360 __be32 consumer_index; 361 __be32 producer_index; 362 uint32_t reserved4[2]; 363 __be64 db_rec_addr; 364}; 365 366struct mlx4_srq_context { 367 __be32 state_logsize_srqn; 368 uint8_t logstride; 369 uint8_t reserved1; 370 __be16 xrcd; 371 __be32 pg_offset_cqn; 372 uint32_t reserved2; 373 uint8_t log_page_size; 374 uint8_t reserved3[2]; 375 uint8_t mtt_base_addr_h; 376 __be32 mtt_base_addr_l; 377 __be32 pd; 378 __be16 limit_watermark; 379 __be16 wqe_cnt; 380 u16 reserved4; 381 __be16 wqe_counter; 382 uint32_t reserved5; 383 __be64 db_rec_addr; 384}; 385 386struct mlx4_eq { 387 struct mlx4_priv *priv; 388 void /*__iomem*/*doorbell; 389 int eqn; 390 uint32_t cons_index; 391 u16 irq; 392 u16 have_irq; 393 int nent; 394 struct mlx4_buf_list *page_list; 395 struct mlx4_mtt mtt; 396}; 397 398struct mlx4_slave_eqe { 399 uint8_t type; 400 uint8_t port; 401 uint32_t param; 402}; 403 404struct mlx4_slave_event_eq_info { 405 int eqn; 406 u16 token; 407}; 408 409struct mlx4_profile { 410 int num_qp; 411 int rdmarc_per_qp; 412 int num_srq; 413 int num_cq; 414 int num_mcg; 415 int num_mpt; 416 unsigned num_mtt_segs; 417}; 418 419struct mlx4_fw { 420 uint64_t clr_int_base; 421 uint64_t catas_offset; 422 uint64_t comm_base; 423 uint64_t clock_offset; 424 struct mlx4_icm *fw_icm; 425 struct mlx4_icm *aux_icm; 426 uint32_t catas_size; 427 u16 fw_pages; 428 uint8_t clr_int_bar; 429 uint8_t catas_bar; 430 uint8_t comm_bar; 431 uint8_t clock_bar; 432}; 433/* 434 struct mlx4_comm { 435 uint32_t slave_write; 436 uint32_t slave_read; 437 }; 438 439 enum { 440 MLX4_MCAST_CONFIG = 0, 441 MLX4_MCAST_DISABLE = 1, 442 MLX4_MCAST_ENABLE = 2, 443 }; 444 445 #define VLAN_FLTR_SIZE 128 446 447 struct mlx4_vlan_fltr { 448 __be32 entry[VLAN_FLTR_SIZE]; 449 }; 450 451 struct mlx4_mcast_entry { 452 struct list_head list; 453 uint64_t addr; 454 }; 455 */ 456struct mlx4_promisc_qp { 457 struct list_head list; 458 uint32_t qpn; 459}; 460 461struct mlx4_steer_index { 462 struct list_head list; 463 unsigned int index; 464 struct list_head duplicates; 465}; 466/* 467 #define MLX4_EVENT_TYPES_NUM 64 468 469 struct mlx4_slave_state { 470 uint8_t comm_toggle; 471 uint8_t last_cmd; 472 uint8_t init_port_mask; 473 bool active; 474 bool old_vlan_api; 475 uint8_t function; 476 dma_addr_t vhcr_dma; 477 u16 mtu[MLX4_MAX_PORTS + 1]; 478 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 479 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 480 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 481 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 482 event type to eq number lookup 483 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; 484 u16 eq_pi; 485 u16 eq_ci; 486 spinlock_t lock; 487 initialized via the kzalloc 488 uint8_t is_slave_going_down; 489 uint32_t cookie; 490 enum slave_port_state port_state[MLX4_MAX_PORTS + 1]; 491 }; 492 493 #define MLX4_VGT 4095 494 #define NO_INDX (-1) 495 496 497 struct mlx4_vport_state { 498 uint64_t mac; 499 u16 default_vlan; 500 uint8_t default_qos; 501 uint32_t tx_rate; 502 bool spoofchk; 503 uint32_t link_state; 504 }; 505 506 struct mlx4_vf_admin_state { 507 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1]; 508 }; 509 510 struct mlx4_vport_oper_state { 511 struct mlx4_vport_state state; 512 int mac_idx; 513 int vlan_idx; 514 }; 515 struct mlx4_vf_oper_state { 516 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1]; 517 }; 518 519 struct slave_list { 520 struct mutex mutex; 521 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 522 }; 523 524 struct resource_allocator { 525 spinlock_t alloc_lock; 526 union { 527 int res_reserved; 528 int res_port_rsvd[MLX4_MAX_PORTS]; 529 }; 530 union { 531 int res_free; 532 int res_port_free[MLX4_MAX_PORTS]; 533 }; 534 int *quota; 535 int *allocated; 536 int *guaranteed; 537 }; 538 539 struct mlx4_resource_tracker { 540 spinlock_t lock; 541 tree for each resources 542 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 543 num_of_slave's lists, one per slave 544 struct slave_list *slave_list; 545 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE]; 546 }; 547 548 #define SLAVE_EVENT_EQ_SIZE 128 549 struct mlx4_slave_event_eq { 550 uint32_t eqn; 551 uint32_t cons; 552 uint32_t prod; 553 spinlock_t event_lock; 554 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 555 }; 556 557 struct mlx4_master_qp0_state { 558 int proxy_qp0_active; 559 int qp0_active; 560 int port_active; 561 }; 562 563 struct mlx4_mfunc_master_ctx { 564 struct mlx4_slave_state *slave_state; 565 struct mlx4_vf_admin_state *vf_admin; 566 struct mlx4_vf_oper_state *vf_oper; 567 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 568 int init_port_ref[MLX4_MAX_PORTS + 1]; 569 u16 max_mtu[MLX4_MAX_PORTS + 1]; 570 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 571 struct mlx4_resource_tracker res_tracker; 572 struct workqueue_struct *comm_wq; 573 struct work_struct comm_work; 574 struct work_struct arm_comm_work; 575 struct work_struct slave_event_work; 576 struct work_struct slave_flr_event_work; 577 spinlock_t slave_state_lock; 578 __be32 comm_arm_bit_vector[4]; 579 struct mlx4_eqe cmd_eqe; 580 struct mlx4_slave_event_eq slave_eq; 581 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 582 }; 583 584 struct mlx4_mfunc { 585 struct mlx4_comm *comm; 586 struct mlx4_vhcr_cmd *vhcr; 587 lpaddr_t vhcr_dma; 588 589 struct mlx4_mfunc_master_ctx master; 590 }; 591 */ 592#define MGM_QPN_MASK 0x00FFFFFF 593#define MGM_BLCK_LB_BIT 30 594 595struct mlx4_mgm { 596 __be32 next_gid_index; 597 __be32 members_count; 598 uint32_t reserved[2]; 599 uint8_t gid[16]; 600 __be32 qp[MLX4_MAX_QP_PER_MGM]; 601}; 602 603struct mlx4_cmd { 604 struct pci_pool *pool; 605 void *hcr; 606 struct thread_mutex hcr_mutex; 607 struct thread_mutex slave_cmd_mutex; 608 struct thread_sem poll_sem; 609 struct thread_sem event_sem; 610 int max_cmds; 611 struct thread_mutex context_lock; 612 int free_head; 613 struct mlx4_cmd_context *context; 614 u16 token_mask; 615 uint8_t use_events; 616 uint8_t toggle; 617 uint8_t comm_toggle; 618}; 619/* 620 enum { 621 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0, 622 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1, 623 }; 624 struct mlx4_vf_immed_vlan_work { 625 struct work_struct work; 626 struct mlx4_priv *priv; 627 int flags; 628 int slave; 629 int vlan_ix; 630 int orig_vlan_ix; 631 uint8_t port; 632 uint8_t qos; 633 u16 vlan_id; 634 u16 orig_vlan_id; 635 }; 636 637 */ 638struct mlx4_uar_table { 639 struct mlx4_bitmap bitmap; 640}; 641 642struct mlx4_mr_table { 643 struct mlx4_bitmap mpt_bitmap; 644 struct mlx4_buddy mtt_buddy; 645 uint64_t mtt_base; 646 uint64_t mpt_base; 647 struct mlx4_icm_table mtt_table; 648 struct mlx4_icm_table dmpt_table; 649}; 650 651struct mlx4_cq_table { 652 struct mlx4_bitmap bitmap; 653 spinlock_t lock; 654 pthread_rwlock_t cq_table_lock; 655 struct radix_tree_root tree; 656 struct mlx4_icm_table table; 657 struct mlx4_icm_table cmpt_table; 658}; 659 660struct mlx4_eq_table { 661 struct mlx4_bitmap bitmap; 662 char *irq_names; 663 void *clr_int; /*__iomem*/ 664 void **uar_map; /*__iomem*/ 665 uint32_t clr_mask; 666 struct mlx4_eq *eq; 667 struct mlx4_icm_table table; 668 struct mlx4_icm_table cmpt_table; 669 int have_irq; 670 uint8_t inta_pin; 671}; 672 673struct mlx4_srq_table { 674 struct mlx4_bitmap bitmap; 675 spinlock_t lock; 676 struct radix_tree_root tree; 677 struct mlx4_icm_table table; 678 struct mlx4_icm_table cmpt_table; 679}; 680 681struct mlx4_qp_table { 682 struct mlx4_bitmap bitmap; 683 uint32_t rdmarc_base; 684 int rdmarc_shift; 685 spinlock_t lock; 686 struct mlx4_icm_table qp_table; 687 struct mlx4_icm_table auxc_table; 688 struct mlx4_icm_table altc_table; 689 struct mlx4_icm_table rdmarc_table; 690 struct mlx4_icm_table cmpt_table; 691}; 692 693struct mlx4_mcg_table { 694 struct thread_mutex mutex; 695 struct mlx4_bitmap bitmap; 696 struct mlx4_icm_table table; 697}; 698/* 699 struct mlx4_catas_err { 700 uint32_t __iomem *map; 701 struct timer_list timer; 702 struct list_head list; 703 }; 704 705 */ 706#define MLX4_MAX_MAC_NUM 128 707#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 708 709struct mlx4_mac_table { 710 __be64 entries[MLX4_MAX_MAC_NUM]; 711 int refs[MLX4_MAX_MAC_NUM]; 712 struct thread_mutex mutex; 713 int total; 714 int max; 715}; 716 717#define MLX4_MAX_VLAN_NUM 128 718/* 719 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 720 */ 721struct mlx4_vlan_table { 722 __be32 entries[MLX4_MAX_VLAN_NUM]; 723 int refs[MLX4_MAX_VLAN_NUM]; 724 struct thread_mutex mutex; 725 int total; 726 int max; 727}; 728 729#define SET_PORT_GEN_ALL_VALID 0x7 730#define SET_PORT_PROMISC_SHIFT 31 731#define SET_PORT_MC_PROMISC_SHIFT 30 732 733enum { 734 MCAST_DIRECT_ONLY = 0, MCAST_DIRECT = 1, MCAST_DEFAULT = 2 735}; 736 737struct mlx4_set_port_general_context { 738 uint8_t reserved[3]; 739 uint8_t flags; 740 u16 reserved2; 741 __be16 mtu; 742 uint8_t pptx; 743 uint8_t pfctx; 744 u16 reserved3; 745 uint8_t pprx; 746 uint8_t pfcrx; 747 u16 reserved4; 748}; 749 750struct mlx4_set_port_rqp_calc_context { 751 __be32 base_qpn; 752 uint8_t rererved; 753 uint8_t n_mac; 754 uint8_t n_vlan; 755 uint8_t n_prio; 756 uint8_t reserved2[3]; 757 uint8_t mac_miss; 758 uint8_t intra_no_vlan; 759 uint8_t no_vlan; 760 uint8_t intra_vlan_miss; 761 uint8_t vlan_miss; 762 uint8_t reserved3[3]; 763 uint8_t no_vlan_prio; 764 __be32 promisc; 765 __be32 mcast; 766}; 767 768struct mlx4_hca_info { 769 struct mlx4_priv *priv; 770/* struct device_attribute firmware_attr; 771 struct device_attribute hca_attr; 772 struct device_attribute board_attr;*/ 773}; 774 775struct mlx4_port_info { 776 struct mlx4_priv *priv; 777 int port; 778 char dev_name[16]; 779 /*struct device_attribute port_attr;*/ 780 enum mlx4_port_type tmp_type; 781 char dev_mtu_name[16]; 782 /*struct device_attribute port_mtu_attr;*/ 783 struct mlx4_mac_table mac_table; 784 struct mlx4_vlan_table vlan_table; 785 int base_qpn; 786}; 787 788struct mlx4_sense { 789 struct mlx4_priv *priv; 790 uint8_t do_sense_port[MLX4_MAX_PORTS + 1]; 791 uint8_t sense_allowed[MLX4_MAX_PORTS + 1]; 792/*struct delayed_work sense_poll;*/ 793}; 794 795struct mlx4_msix_ctl { 796 uint64_t pool_bm; 797 struct thread_mutex pool_lock; 798}; 799 800struct mlx4_steer { 801 struct list_head promisc_qps[MLX4_NUM_STEERS]; 802 struct list_head steer_entries[MLX4_NUM_STEERS]; 803}; 804 805enum { 806 MLX4_PCI_DEV_IS_VF = 1 << 0, MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1, 807}; 808 809struct mlx4_roce_gid_entry { 810 uint8_t raw[16]; 811}; 812 813struct counter_index { 814 struct list_head list; 815 uint32_t index; 816}; 817 818struct mlx4_counters { 819 struct mlx4_bitmap bitmap; 820 struct list_head global_port_list[MLX4_MAX_PORTS]; 821 struct list_head vf_list[MLX4_MAX_NUM_VF][MLX4_MAX_PORTS]; 822 struct thread_mutex mutex; 823}; 824/* 825 enum { 826 MLX4_NO_RR = 0, 827 MLX4_USE_RR = 1, 828 }; 829 */ 830struct mlx4_priv { 831 struct mlx4_dev dev; 832 833 struct list_head dev_list; 834 struct list_head ctx_list; 835 spinlock_t ctx_lock; 836 837 int pci_dev_data; 838 839 struct list_head pgdir_list; 840 struct thread_mutex pgdir_mutex; 841 842 struct mlx4_fw fw; 843 struct mlx4_cmd cmd; 844 /*struct mlx4_mfunc mfunc;*/ 845 846 struct mlx4_bitmap pd_bitmap; 847 struct mlx4_bitmap xrcd_bitmap; 848 struct mlx4_uar_table uar_table; 849 struct mlx4_mr_table mr_table; 850 struct mlx4_cq_table cq_table; 851 struct mlx4_eq_table eq_table; 852 struct mlx4_srq_table srq_table; 853 struct mlx4_qp_table qp_table; 854 struct mlx4_mcg_table mcg_table; 855 struct mlx4_counters counters_table; 856 857 /*struct mlx4_catas_err catas_err;*/ 858 859 void *clr_base; /*__iomem*/ 860 861 struct mlx4_uar driver_uar; 862 void *kar; /*__iomem*/ 863 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 864 struct mlx4_hca_info hca_info; 865 struct mlx4_sense sense; 866 struct thread_mutex port_mutex; 867 struct mlx4_msix_ctl msix_ctl; 868 struct mlx4_steer *steer; 869 struct list_head bf_list; 870 struct thread_mutex bf_mutex; 871 /*struct io_mapping*/void *bf_mapping; 872 void *clock_mapping; /*__iomem*/ 873 int reserved_mtts; 874 int fs_hash_mode; 875 uint8_t virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; 876 __be64 slave_node_guids[MLX4_MFUNC_MAX]; 877 struct mlx4_roce_gid_entry roce_gids[MLX4_MAX_PORTS][128]; 878 atomic_t opreq_count; 879/*struct work_struct opreq_task;*/ 880}; 881 882static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) { 883 return container_of(dev, struct mlx4_priv, dev); 884} 885#define MLX4_SENSE_RANGE (HZ * 3) 886/* 887 extern struct workqueue_struct *mlx4_wq; 888 */ 889uint32_t mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 890/* 891 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, uint32_t obj, int use_rr); 892 */ 893uint32_t mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align, 894 uint32_t skip_mask); 895void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, uint32_t obj, int cnt, 896 int use_rr); 897uint32_t mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 898int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, uint32_t num, uint32_t mask, 899 uint32_t reserved_bot, uint32_t resetrved_top); 900void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 901int mlx4_reset(struct mlx4_priv *priv); 902int mlx4_alloc_eq_table(struct mlx4_priv *priv); 903/* 904 void mlx4_free_eq_table(struct mlx4_priv *priv); 905 */ 906int mlx4_init_pd_table(struct mlx4_priv *priv); 907int mlx4_init_xrcd_table(struct mlx4_priv *priv); 908int mlx4_init_uar_table(struct mlx4_priv *priv); 909int mlx4_init_mr_table(struct mlx4_priv *priv); 910int mlx4_init_eq_table(struct mlx4_priv *priv); 911int mlx4_init_cq_table(struct mlx4_priv *priv); 912int mlx4_init_qp_table(struct mlx4_priv *priv); 913int mlx4_init_srq_table(struct mlx4_priv *priv); 914int mlx4_init_mcg_table(struct mlx4_priv *priv); 915/* 916 void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 917 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 918 void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 919 void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 920 void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 921 void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 922 void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 923 void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 924 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 925 */ 926int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn); 927/* 928 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 929 */ 930int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 931/* 932 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 933 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 934 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 935 */ 936int __mlx4_mpt_reserve(struct mlx4_priv *priv); 937/* 938 void __mlx4_mpt_release(struct mlx4_dev *dev, uint32_t index); 939 */ 940int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, uint32_t index); 941/* 942 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, uint32_t index); 943 */ 944uint32_t __mlx4_alloc_mtt_range(struct mlx4_priv *priv, int order); 945/* 946 void __mlx4_free_mtt_range(struct mlx4_dev *dev, uint32_t first_seg, int order); 947 948 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 949 struct mlx4_vhcr *vhcr, 950 struct mlx4_cmd_mailbox *inbox, 951 struct mlx4_cmd_mailbox *outbox, 952 struct mlx4_cmd_info *cmd); 953 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 954 struct mlx4_vhcr *vhcr, 955 struct mlx4_cmd_mailbox *inbox, 956 struct mlx4_cmd_mailbox *outbox, 957 struct mlx4_cmd_info *cmd); 958 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 959 struct mlx4_vhcr *vhcr, 960 struct mlx4_cmd_mailbox *inbox, 961 struct mlx4_cmd_mailbox *outbox, 962 struct mlx4_cmd_info *cmd); 963 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 964 struct mlx4_vhcr *vhcr, 965 struct mlx4_cmd_mailbox *inbox, 966 struct mlx4_cmd_mailbox *outbox, 967 struct mlx4_cmd_info *cmd); 968 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 969 struct mlx4_vhcr *vhcr, 970 struct mlx4_cmd_mailbox *inbox, 971 struct mlx4_cmd_mailbox *outbox, 972 struct mlx4_cmd_info *cmd); 973 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 974 struct mlx4_vhcr *vhcr, 975 struct mlx4_cmd_mailbox *inbox, 976 struct mlx4_cmd_mailbox *outbox, 977 struct mlx4_cmd_info *cmd); 978 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 979 struct mlx4_vhcr *vhcr, 980 struct mlx4_cmd_mailbox *inbox, 981 struct mlx4_cmd_mailbox *outbox, 982 struct mlx4_cmd_info *cmd); 983 */ 984int __mlx4_qp_reserve_range(struct mlx4_priv *priv, int cnt, int align, 985 int *base, uint8_t flags); 986/* 987 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 988 */ 989int __mlx4_register_mac(struct mlx4_dev *dev, uint8_t port, uint64_t mac); 990/* 991 void __mlx4_unregister_mac(struct mlx4_dev *dev, uint8_t port, uint64_t mac); 992 */ 993int __mlx4_write_mtt(struct mlx4_priv *priv, struct mlx4_mtt *mtt, 994 int start_index, int npages, uint64_t *page_list); 995int __mlx4_counter_alloc(struct mlx4_dev *dev, int slave, int port, int *idx); 996/* 997 void __mlx4_counter_free(struct mlx4_dev *dev, int slave, int port, uint32_t idx); 998 999 int __mlx4_slave_counters_free(struct mlx4_dev *dev, int slave); 1000 int __mlx4_clear_if_stat(struct mlx4_dev *dev, 1001 uint8_t counter_index); 1002 uint8_t mlx4_get_default_counter_index(struct mlx4_dev *dev, int slave, int port); 1003 1004 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, uint32_t *xrcdn); 1005 void __mlx4_xrcd_free(struct mlx4_dev *dev, uint32_t xrcdn); 1006 1007 void mlx4_start_catas_poll(struct mlx4_dev *dev); 1008 void mlx4_stop_catas_poll(struct mlx4_dev *dev); 1009 void mlx4_catas_init(void); 1010 int mlx4_restart_one(struct pci_dev *pdev); 1011 int mlx4_register_device(struct mlx4_dev *dev); 1012 void mlx4_unregister_device(struct mlx4_dev *dev); 1013 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, 1014 unsigned long param); 1015 */ 1016struct mlx4_dev_cap; 1017struct mlx4_init_hca_param; 1018 1019uint64_t mlx4_make_profile(struct mlx4_priv *priv, struct mlx4_profile *request, 1020 struct mlx4_dev_cap *dev_cap, struct mlx4_init_hca_param *init_hca); 1021/* 1022 void mlx4_master_comm_channel(struct work_struct *work); 1023 void mlx4_master_arm_comm_channel(struct work_struct *work); 1024 void mlx4_gen_slave_eqe(struct work_struct *work); 1025 void mlx4_master_handle_slave_flr(struct work_struct *work); 1026 1027 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 1028 struct mlx4_vhcr *vhcr, 1029 struct mlx4_cmd_mailbox *inbox, 1030 struct mlx4_cmd_mailbox *outbox, 1031 struct mlx4_cmd_info *cmd); 1032 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 1033 struct mlx4_vhcr *vhcr, 1034 struct mlx4_cmd_mailbox *inbox, 1035 struct mlx4_cmd_mailbox *outbox, 1036 struct mlx4_cmd_info *cmd); 1037 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 1038 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 1039 struct mlx4_cmd_mailbox *outbox, 1040 struct mlx4_cmd_info *cmd); 1041 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 1042 struct mlx4_vhcr *vhcr, 1043 struct mlx4_cmd_mailbox *inbox, 1044 struct mlx4_cmd_mailbox *outbox, 1045 struct mlx4_cmd_info *cmd); 1046 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 1047 struct mlx4_vhcr *vhcr, 1048 struct mlx4_cmd_mailbox *inbox, 1049 struct mlx4_cmd_mailbox *outbox, 1050 struct mlx4_cmd_info *cmd); 1051 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 1052 struct mlx4_vhcr *vhcr, 1053 struct mlx4_cmd_mailbox *inbox, 1054 struct mlx4_cmd_mailbox *outbox, 1055 struct mlx4_cmd_info *cmd); 1056 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1057 struct mlx4_vhcr *vhcr, 1058 struct mlx4_cmd_mailbox *inbox, 1059 struct mlx4_cmd_mailbox *outbox, 1060 struct mlx4_cmd_info *cmd); 1061 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1062 struct mlx4_vhcr *vhcr, 1063 struct mlx4_cmd_mailbox *inbox, 1064 struct mlx4_cmd_mailbox *outbox, 1065 struct mlx4_cmd_info *cmd); 1066 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1067 struct mlx4_vhcr *vhcr, 1068 struct mlx4_cmd_mailbox *inbox, 1069 struct mlx4_cmd_mailbox *outbox, 1070 struct mlx4_cmd_info *cmd); 1071 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1072 struct mlx4_vhcr *vhcr, 1073 struct mlx4_cmd_mailbox *inbox, 1074 struct mlx4_cmd_mailbox *outbox, 1075 struct mlx4_cmd_info *cmd); 1076 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1077 struct mlx4_vhcr *vhcr, 1078 struct mlx4_cmd_mailbox *inbox, 1079 struct mlx4_cmd_mailbox *outbox, 1080 struct mlx4_cmd_info *cmd); 1081 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1082 struct mlx4_vhcr *vhcr, 1083 struct mlx4_cmd_mailbox *inbox, 1084 struct mlx4_cmd_mailbox *outbox, 1085 struct mlx4_cmd_info *cmd); 1086 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1087 struct mlx4_vhcr *vhcr, 1088 struct mlx4_cmd_mailbox *inbox, 1089 struct mlx4_cmd_mailbox *outbox, 1090 struct mlx4_cmd_info *cmd); 1091 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1092 struct mlx4_vhcr *vhcr, 1093 struct mlx4_cmd_mailbox *inbox, 1094 struct mlx4_cmd_mailbox *outbox, 1095 struct mlx4_cmd_info *cmd); 1096 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 1097 struct mlx4_vhcr *vhcr, 1098 struct mlx4_cmd_mailbox *inbox, 1099 struct mlx4_cmd_mailbox *outbox, 1100 struct mlx4_cmd_info *cmd); 1101 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1102 struct mlx4_vhcr *vhcr, 1103 struct mlx4_cmd_mailbox *inbox, 1104 struct mlx4_cmd_mailbox *outbox, 1105 struct mlx4_cmd_info *cmd); 1106 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1107 struct mlx4_vhcr *vhcr, 1108 struct mlx4_cmd_mailbox *inbox, 1109 struct mlx4_cmd_mailbox *outbox, 1110 struct mlx4_cmd_info *cmd); 1111 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 1112 struct mlx4_vhcr *vhcr, 1113 struct mlx4_cmd_mailbox *inbox, 1114 struct mlx4_cmd_mailbox *outbox, 1115 struct mlx4_cmd_info *cmd); 1116 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1117 struct mlx4_vhcr *vhcr, 1118 struct mlx4_cmd_mailbox *inbox, 1119 struct mlx4_cmd_mailbox *outbox, 1120 struct mlx4_cmd_info *cmd); 1121 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1122 struct mlx4_vhcr *vhcr, 1123 struct mlx4_cmd_mailbox *inbox, 1124 struct mlx4_cmd_mailbox *outbox, 1125 struct mlx4_cmd_info *cmd); 1126 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1127 struct mlx4_vhcr *vhcr, 1128 struct mlx4_cmd_mailbox *inbox, 1129 struct mlx4_cmd_mailbox *outbox, 1130 struct mlx4_cmd_info *cmd); 1131 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave, 1132 struct mlx4_vhcr *vhcr, 1133 struct mlx4_cmd_mailbox *inbox, 1134 struct mlx4_cmd_mailbox *outbox, 1135 struct mlx4_cmd_info *cmd); 1136 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1137 struct mlx4_vhcr *vhcr, 1138 struct mlx4_cmd_mailbox *inbox, 1139 struct mlx4_cmd_mailbox *outbox, 1140 struct mlx4_cmd_info *cmd); 1141 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1142 struct mlx4_vhcr *vhcr, 1143 struct mlx4_cmd_mailbox *inbox, 1144 struct mlx4_cmd_mailbox *outbox, 1145 struct mlx4_cmd_info *cmd); 1146 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1147 struct mlx4_vhcr *vhcr, 1148 struct mlx4_cmd_mailbox *inbox, 1149 struct mlx4_cmd_mailbox *outbox, 1150 struct mlx4_cmd_info *cmd); 1151 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 1152 struct mlx4_vhcr *vhcr, 1153 struct mlx4_cmd_mailbox *inbox, 1154 struct mlx4_cmd_mailbox *outbox, 1155 struct mlx4_cmd_info *cmd); 1156 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave, 1157 struct mlx4_vhcr *vhcr, 1158 struct mlx4_cmd_mailbox *inbox, 1159 struct mlx4_cmd_mailbox *outbox, 1160 struct mlx4_cmd_info *cmd); 1161 1162 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 1163 */ 1164int mlx4_cmd_init(struct mlx4_priv *priv); 1165/* 1166 void mlx4_cmd_cleanup(struct mlx4_dev *dev); 1167 int mlx4_multi_func_init(struct mlx4_dev *dev); 1168 void mlx4_multi_func_cleanup(struct mlx4_dev *dev); 1169 */ 1170void mlx4_cmd_event(struct mlx4_priv *priv, u16 token, uint8_t status, 1171 uint64_t out_param); 1172int mlx4_cmd_use_events(struct mlx4_priv *priv); 1173/* 1174 void mlx4_cmd_use_polling(struct mlx4_dev *dev); 1175 1176 int mlx4_comm_cmd(struct mlx4_dev *dev, uint8_t cmd, u16 param, 1177 unsigned long timeout); 1178 */ 1179void mlx4_cq_completion(struct mlx4_priv *priv, uint32_t cqn); 1180/* 1181 void mlx4_cq_event(struct mlx4_dev *dev, uint32_t cqn, int event_type); 1182 */ 1183void mlx4_qp_event(struct mlx4_priv *priv, uint32_t qpn, int event_type); 1184void mlx4_srq_event(struct mlx4_priv *priv, uint32_t srqn, int event_type); 1185/* 1186 void mlx4_handle_catas_err(struct mlx4_dev *dev); 1187 1188 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 1189 enum mlx4_port_type *type); 1190 void mlx4_do_sense_ports(struct mlx4_dev *dev, 1191 enum mlx4_port_type *stype, 1192 enum mlx4_port_type *defaults); 1193 void mlx4_start_sense(struct mlx4_dev *dev); 1194 void mlx4_stop_sense(struct mlx4_dev *dev); 1195 void mlx4_sense_init(struct mlx4_dev *dev); 1196 int mlx4_check_port_params(struct mlx4_dev *dev, 1197 enum mlx4_port_type *port_type); 1198 int mlx4_change_port_types(struct mlx4_dev *dev, 1199 enum mlx4_port_type *port_types); 1200 */ 1201void mlx4_init_mac_table(struct mlx4_priv *priv, struct mlx4_mac_table *table); 1202void mlx4_init_vlan_table(struct mlx4_priv *priv, struct mlx4_vlan_table *table); 1203/* 1204 void __mlx4_unregister_vlan(struct mlx4_dev *dev, uint8_t port, u16 vlan); 1205 int __mlx4_register_vlan(struct mlx4_dev *dev, uint8_t port, u16 vlan, int *index); 1206 */ 1207int mlx4_SET_PORT(struct mlx4_priv *priv, uint8_t port, int pkey_tbl_sz); 1208/* 1209 resource tracker functions 1210 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 1211 enum mlx4_resource resource_type, 1212 uint64_t resource_id, int *slave); 1213 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 1214 int mlx4_init_resource_tracker(struct mlx4_dev *dev); 1215 1216 void mlx4_free_resource_tracker(struct mlx4_dev *dev, 1217 enum mlx4_res_tracker_free_type type); 1218 1219 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1220 struct mlx4_vhcr *vhcr, 1221 struct mlx4_cmd_mailbox *inbox, 1222 struct mlx4_cmd_mailbox *outbox, 1223 struct mlx4_cmd_info *cmd); 1224 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 1225 struct mlx4_vhcr *vhcr, 1226 struct mlx4_cmd_mailbox *inbox, 1227 struct mlx4_cmd_mailbox *outbox, 1228 struct mlx4_cmd_info *cmd); 1229 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1230 struct mlx4_vhcr *vhcr, 1231 struct mlx4_cmd_mailbox *inbox, 1232 struct mlx4_cmd_mailbox *outbox, 1233 struct mlx4_cmd_info *cmd); 1234 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1235 struct mlx4_vhcr *vhcr, 1236 struct mlx4_cmd_mailbox *inbox, 1237 struct mlx4_cmd_mailbox *outbox, 1238 struct mlx4_cmd_info *cmd); 1239 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1240 struct mlx4_vhcr *vhcr, 1241 struct mlx4_cmd_mailbox *inbox, 1242 struct mlx4_cmd_mailbox *outbox, 1243 struct mlx4_cmd_info *cmd); 1244 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1245 struct mlx4_vhcr *vhcr, 1246 struct mlx4_cmd_mailbox *inbox, 1247 struct mlx4_cmd_mailbox *outbox, 1248 struct mlx4_cmd_info *cmd); 1249 */ 1250int mlx4_get_port_ib_caps(struct mlx4_priv *priv, uint8_t port, __be32 *caps); 1251/* 1252 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, uint8_t port, 1253 int *gid_tbl_len, int *pkey_tbl_len); 1254 1255 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1256 struct mlx4_vhcr *vhcr, 1257 struct mlx4_cmd_mailbox *inbox, 1258 struct mlx4_cmd_mailbox *outbox, 1259 struct mlx4_cmd_info *cmd); 1260 1261 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1262 struct mlx4_vhcr *vhcr, 1263 struct mlx4_cmd_mailbox *inbox, 1264 struct mlx4_cmd_mailbox *outbox, 1265 struct mlx4_cmd_info *cmd); 1266 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, uint8_t gid[16], 1267 enum mlx4_protocol prot, enum mlx4_steer_type steer); 1268 */ 1269int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, 1270 uint8_t gid[16], int block_mcast_loopback, enum mlx4_protocol prot, 1271 enum mlx4_steer_type steer); 1272int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, 1273 uint8_t gid[16], uint8_t port, int block_mcast_loopback, 1274 enum mlx4_protocol prot, uint64_t *reg_id); 1275/* 1276 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, uint8_t port, uint64_t mac, uint64_t clear, uint8_t mode); 1277 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1278 struct mlx4_vhcr *vhcr, 1279 struct mlx4_cmd_mailbox *inbox, 1280 struct mlx4_cmd_mailbox *outbox, 1281 struct mlx4_cmd_info *cmd); 1282 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1283 struct mlx4_vhcr *vhcr, 1284 struct mlx4_cmd_mailbox *inbox, 1285 struct mlx4_cmd_mailbox *outbox, 1286 struct mlx4_cmd_info *cmd); 1287 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1288 int port, void *buf); 1289 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1290 struct mlx4_vhcr *vhcr, 1291 struct mlx4_cmd_mailbox *inbox, 1292 struct mlx4_cmd_mailbox *outbox, 1293 struct mlx4_cmd_info *cmd); 1294 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1295 struct mlx4_vhcr *vhcr, 1296 struct mlx4_cmd_mailbox *inbox, 1297 struct mlx4_cmd_mailbox *outbox, 1298 struct mlx4_cmd_info *cmd); 1299 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1300 struct mlx4_vhcr *vhcr, 1301 struct mlx4_cmd_mailbox *inbox, 1302 struct mlx4_cmd_mailbox *outbox, 1303 struct mlx4_cmd_info *cmd); 1304 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1305 struct mlx4_vhcr *vhcr, 1306 struct mlx4_cmd_mailbox *inbox, 1307 struct mlx4_cmd_mailbox *outbox, 1308 struct mlx4_cmd_info *cmd); 1309 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, 1310 struct mlx4_vhcr *vhcr, 1311 struct mlx4_cmd_mailbox *inbox, 1312 struct mlx4_cmd_mailbox *outbox, 1313 struct mlx4_cmd_info *cmd); 1314 int mlx4_MOD_STAT_CFG_wrapper(struct mlx4_dev *dev, int slave, 1315 struct mlx4_vhcr *vhcr, 1316 struct mlx4_cmd_mailbox *inbox, 1317 struct mlx4_cmd_mailbox *outbox, 1318 struct mlx4_cmd_info *cmd); 1319 */ 1320int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); 1321int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); 1322 1323static inline void set_param_l(uint64_t *arg, uint32_t val) { 1324 *arg = (*arg & 0xffffffff00000000ULL) | (uint64_t) val; 1325} 1326 1327static inline void set_param_h(uint64_t *arg, uint32_t val) { 1328 *arg = (*arg & 0xffffffff) | ((uint64_t) val << 32); 1329} 1330 1331static inline uint32_t get_param_l(uint64_t *arg) { 1332 return (uint32_t) (*arg & 0xffffffff); 1333} 1334/* 1335 static inline uint32_t get_param_h(uint64_t *arg) 1336 { 1337 return (uint32_t)(*arg >> 32); 1338 } 1339 1340 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1341 { 1342 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1343 } 1344 */ 1345#define NOT_MASKED_PD_BITS 17 1346/* 1347 void sys_tune_init(void); 1348 void sys_tune_fini(void); 1349 */ 1350void mlx4_init_quotas(struct mlx4_priv *priv); 1351/* 1352 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave); 1353 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave); 1354 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work); 1355 */ 1356 1357#endif /*MLX4_H*/ 1358