| /barrelfish-master/lib/devif/backends/net/mlx4/drivers/net/mlx4/ |
| H A D | en_tx.c | 401 u32 cons_index = mcq->cons_index; local
410 index = cons_index & size_mask;
416 if (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, cons_index & size)) {
458 ++cons_index;
459 index = cons_index & size_mask;
469 mcq->cons_index = cons_index;
496 u32 cons_index = mcq->cons_index; local
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| H A D | en_rx.c | 573 u32 cons_index = mcq->cons_index; local
580 index = cons_index & size_mask;
583 // printf("cqe->owner_sr_opcode %d; cons_index %d:%d; size %d; cq->buf %p; index %d; qpn %x\n",
584 // cqe->owner_sr_opcode, cons_index, ring->prod, size, cq->buf, index, cqe->vlan_my_qpn);
587 if (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, cons_index & size)) {
616 mcq->cons_index = cons_index + 1;
620 ring->cons = mcq->cons_index;
653 u32 cons_index local
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| H A D | eq.c | 109 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
133 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor);
134 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
504 eq->eqn, eq->cons_index, ret);
535 eq->eqn, eq->cons_index, ret);
630 eq->eqn, eq->cons_index, ret);
726 eq->cons_index, eqe->owner, eq->nent,
729 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
752 eq->cons_index, eqe->owner, eq->nent,
754 !!(eq->cons_index
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| H A D | cq.c | 331 cq->cons_index = 0;
|
| H A D | mlx4_devif_queue.c | 1765 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor);
1766 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ?
1772 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
1831 eq->eqn, eq->cons_index, ret);
1858 eq->eqn, eq->cons_index, ret);
1959 eq->eqn, eq->cons_index, ret);
2056 eqe->subtype, eq->eqn, eq->cons_index, eqe->owner,
2058 !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ?
2084 eqe->subtype, eq->eqn, eq->cons_index, eqe->owner,
2086 !!(eqe->owner & 0x80) ^ !!(eq->cons_index
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| H A D | mlx4.h | 390 uint32_t cons_index; member in struct:mlx4_eq
|
| /barrelfish-master/lib/devif/backends/net/mlx4/drivers/infiniband/hw/mthca/ |
| H A D | mthca_cq.c | 180 return cqe_sw(get_cqe(cq, cq->cons_index & cq->ibcq.cqe));
200 * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
207 *cq->set_ci_db = cpu_to_be32(cq->cons_index);
293 for (prod_index = cq->cons_index;
296 if (prod_index == cq->cons_index + cq->ibcq.cqe)
301 qpn, cq->cqn, cq->cons_index, prod_index);
307 while ((int) --prod_index - (int) cq->cons_index >= 0) {
320 set_cqe_hw(get_cqe(cq, (cq->cons_index + i) & cq->ibcq.cqe));
322 cq->cons_index += nfreed;
341 cq->cons_index
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| H A D | mthca_provider.h | 109 u32 cons_index; member in struct:mthca_eq
205 u32 cons_index; member in struct:mthca_cq
|
| H A D | mthca_eq.c | 236 eqe = get_eqe(eq, eq->cons_index);
362 ++eq->cons_index;
378 set_eq_ci(dev, eq, eq->cons_index);
410 dev->eq_table.eq[i].cons_index);
423 tavor_set_eq_ci(dev, eq, eq->cons_index);
443 dev->eq_table.eq[i].cons_index);
457 arbel_set_eq_ci(dev, eq, eq->cons_index);
561 eq->cons_index = 0;
|
| /barrelfish-master/lib/devif/backends/net/mlx4/include/linux/mlx4/ |
| H A D | cq.h | 154 ci = cq->cons_index & 0xffffff;
170 *cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff);
|
| H A D | device.h | 643 u32 cons_index; member in struct:mlx4_cq
|
| /barrelfish-master/lib/devif/backends/net/mlx4/drivers/infiniband/hw/mlx4/ |
| H A D | cq.c | 93 return get_sw_cqe(cq, cq->mcq.cons_index);
326 i = cq->mcq.cons_index;
330 return i - cq->mcq.cons_index;
340 i = cq->mcq.cons_index;
355 ++cq->mcq.cons_index;
606 ++cq->mcq.cons_index;
839 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
840 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
847 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
867 cq->mcq.cons_index
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