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/barrelfish-2018-10-04/lib/libc/aarch64/
H A Dgd_qnan.h11 #define d_QNAN0 0x0
13 #define ld_QNAN0 0x0
14 #define ld_QNAN1 0x0
15 #define ld_QNAN2 0x0
17 #define ldus_QNAN0 0x0
18 #define ldus_QNAN1 0x0
19 #define ldus_QNAN2 0x0
20 #define ldus_QNAN3 0x0
21 #define ldus_QNAN4 0x0
/barrelfish-2018-10-04/lib/libc/riscv/
H A Dgd_qnan.h11 #define d_QNAN0 0x0
13 #define ld_QNAN0 0x0
15 #define ld_QNAN2 0x0
16 #define ld_QNAN3 0x0
17 #define ldus_QNAN0 0x0
18 #define ldus_QNAN1 0x0
19 #define ldus_QNAN2 0x0
21 #define ldus_QNAN4 0x0
/barrelfish-2018-10-04/lib/libc/amd64/
H A Dgd_qnan.h11 #define d_QNAN0 0x0
13 #define ld_QNAN0 0x0
16 #define ld_QNAN3 0x0
17 #define ldus_QNAN0 0x0
18 #define ldus_QNAN1 0x0
19 #define ldus_QNAN2 0x0
/barrelfish-2018-10-04/lib/libc/arm/
H A Dgd_qnan.h13 #define d_QNAN0 0x0
15 #define ld_QNAN0 0x0
18 #define ld_QNAN3 0x0
19 #define ldus_QNAN0 0x0
20 #define ldus_QNAN1 0x0
21 #define ldus_QNAN2 0x0
/barrelfish-2018-10-04/lib/libc/aarch64/gen/
H A D_setjmp.S41 stp x8, x9, [x0], #16
44 stp x19, x20, [x0], #16
45 stp x21, x22, [x0], #16
46 stp x23, x24, [x0], #16
47 stp x25, x26, [x0], #16
48 stp x27, x28, [x0], #16
49 stp x29, lr, [x0], #16
53 stp d8, d9, [x0], #16
54 stp d10, d11, [x0], #16
55 stp d12, d13, [x0], #1
[all...]
H A Dsetjmp.S39 stp x0, lr, [sp]
42 add x2, x0, #(_JB_SIGMASK * 8) /* oset */
44 mov x0, #1 /* SIG_BLOCK */
47 ldp x0, lr, [sp]
53 stp x8, x9, [x0], #16
56 stp x19, x20, [x0], #16
57 stp x21, x22, [x0], #16
58 stp x23, x24, [x0], #16
59 stp x25, x26, [x0], #16
60 stp x27, x28, [x0], #1
[all...]
H A D_ctx_start.S35 mov x0, x20 /* Load ucp saved in makecontext */
/barrelfish-2018-10-04/lib/barrelfish/arch/aarch64/
H A Dcontext.S7 * x0-x18 are expected to be clobbered, and will have been saved by the
8 * caller, if required. We are passed the base of the save area in x0. */
11 stp x19, x20, [x0, #(19 * 8)]
12 stp x21, x22, [x0, #(21 * 8)]
13 stp x23, x24, [x0, #(23 * 8)]
14 stp x25, x26, [x0, #(25 * 8)]
15 stp x27, x28, [x0, #(27 * 8)]
16 stp x29, x30, [x0, #(29 * 8)]
21 stp x1, x2, [x0, #(31 * 8)]
/barrelfish-2018-10-04/tools/fastmodels/
H A Dshim.S17 adr x0, shim_stack
18 add sp, x0, #(SHIM_STACK - 8)
24 ldr x0, p_kernel_table
25 msr ttbr0_el3, x0
29 mov x0, #0x00ff
30 msr mair_el3, x0
45 mrs x0, sctlr_el3
46 orr x0, x0, #(1<<0) /* MMU control bit. */
47 msr sctlr_el3, x0
[all...]
/barrelfish-2018-10-04/lib/compiler-rt/test/
H A Dfloatunsitf_test.c42 if (test__floatunsitf(0x7fffffff, UINT64_C(0x401dfffffffc0000), UINT64_C(0x0)))
44 if (test__floatunsitf(0, UINT64_C(0x0), UINT64_C(0x0)))
46 if (test__floatunsitf(0xffffffff, UINT64_C(0x401efffffffe0000), UINT64_C(0x0)))
48 if (test__floatunsitf(0x12345678, UINT64_C(0x401b234567800000), UINT64_C(0x0)))
H A Dfloatsitf_test.c43 if (test__floatsitf(0x80000000, UINT64_C(0xc01e000000000000), UINT64_C(0x0)))
45 if (test__floatsitf(0x7fffffff, UINT64_C(0x401dfffffffc0000), UINT64_C(0x0)))
47 if (test__floatsitf(0, UINT64_C(0x0), UINT64_C(0x0)))
49 if (test__floatsitf(0xffffffff, UINT64_C(0xbfff000000000000), UINT64_C(0x0)))
51 if (test__floatsitf(0x12345678, UINT64_C(0x401b234567800000), UINT64_C(0x0)))
53 if (test__floatsitf(-0x12345678, UINT64_C(0xc01b234567800000), UINT64_C(0x0)))
H A Dextendsftf2_test.c46 UINT64_C(0x0)))
51 UINT64_C(0x0)))
56 UINT64_C(0x0)))
59 if (test__extendsftf2(0.0f, UINT64_C(0x0), UINT64_C(0x0)))
64 UINT64_C(0x0)))
68 UINT64_C(0x0)))
72 UINT64_C(0x0)))
76 UINT64_C(0x0)))
H A Dfloatditf_test.c49 if (test__floatditf(0x2, UINT64_C(0x4000000000000000), UINT64_C(0x0)))
51 if (test__floatditf(0x1, UINT64_C(0x3fff000000000000), UINT64_C(0x0)))
53 if (test__floatditf(0x0, UINT64_C(0x0), UINT64_C(0x0)))
55 if (test__floatditf(0xffffffffffffffff, UINT64_C(0xbfff000000000000), UINT64_C(0x0)))
57 if (test__floatditf(0xfffffffffffffffe, UINT64_C(0xc000000000000000), UINT64_C(0x0)))
61 if (test__floatditf(0x8000000000000000, UINT64_C(0xc03e000000000000), UINT64_C(0x0)))
H A Dmodsi3_test.c45 if (test__modsi3(0x80000000, 1, 0x0))
47 if (test__modsi3(0x80000000, 2, 0x0))
49 if (test__modsi3(0x80000000, -2, 0x0))
/barrelfish-2018-10-04/lib/libc/aarch64/sys/
H A Dcerror.S34 stp x0, lr, [sp]
37 str x1, [x0]
38 movn x0, #0
H A Dvfork.S39 and x0, x0, x1
/barrelfish-2018-10-04/kernel/arch/armv8/
H A Dexceptions.S24 stp x0, x1, [sp]
41 mrs x0, sp_el0
42 stp x30, x0, [sp, #(30 * 8)]
44 mrs x0, elr_el1
46 stp x0, x1, [sp, #(32 * 8)]
57 /* Arguments: x0 = EPC, x1 = SPSR, x2 = ESR, x3 = vector, x4 = save area. */
111 * when coming from a syscall (SVC) the arguments are in registers x0-x11
118 * Registers x0-x11 contain the syscall arguments. We use x12-, as these won't
120 * preserve x0-x6 in registers unless we branch to the abort path, so that they're
177 stp x0, x
[all...]
H A Dsmc_hvc.S30 stp x0, x1, [x4]
41 stp x0, x1, [x4]
H A Dsysreg.S31 stp x0, x1, [sp, #16 * 0]
40 mrs x0, clidr_el1
84 ldp x0, x1, [sp], #16
95 mov x0, #0
107 mov x0, #0
115 stp x0, x1, [sp, #16 * 0]
126 ldp x0, x1, [sp], #16
146 ldr x0, =0xff440c0400
147 msr mair_el1, x0
157 ldr x0,
[all...]
/barrelfish-2018-10-04/lib/tommath/
H A Dbn_mp_karatsuba_mul.c49 mp_int x0, x1, y0, y1, t1, x0y0, x1y1; local
62 if (mp_init_size (&x0, B) != MP_OKAY)
80 x0.used = y0.used = B;
94 tmpx = x0.dp;
115 mp_clamp (&x0);
119 /* after this x0 is no longer required, free temp [x0==t2]! */
120 if (mp_mul (&x0, &y0, &x0y0) != MP_OKAY)
121 goto X1Y1; /* x0y0 = x0*y0 */
125 /* now calc x1+x0 an
[all...]
/barrelfish-2018-10-04/usr/drivers/omap44xx/mmchs/
H A Dctrlmod.c67 omap44xx_sysctrl_padconf_core_control_pbiaslite_mmc1_pbiaslite_pwrdnz_wrf(&st->ctrlmod, 0x0);
68 omap44xx_sysctrl_padconf_core_control_pbiaslite_mmc1_pwrdnz_wrf(&st->ctrlmod, 0x0);
73 omap44xx_sysctrl_padconf_core_control_pbiaslite_mmc1_pbiaslite_hiz_mode_wrf(&st->ctrlmod, 0x0);
81 // 4. set MMC1 speed control to 26MHz@30pF (0x0) -- alternative 65MHz@30pF (0x1)
83 0x0);
85 0x0);
87 0x0);
89 // 5. set MMC1 pullup strength to 10-50kOhm (0x1) -- alt. 50-110kOhm (0x0)
91 0x0);
93 0x0);
[all...]
/barrelfish-2018-10-04/tools/arm_molly/
H A Dmolly_boot64.S21 * x0 contains zero
53 mov x30, x0
54 mov x0, x1
/barrelfish-2018-10-04/lib/libc/xdr/
H A Dxdr_float.c90 {{ 0x7f, 0xff, 0x0, 0xffff }, /* Max Vax */
91 { 0x0, 0xff, 0x0 }}, /* Max IEEE */
92 {{ 0x0, 0x0, 0x0, 0x0 }, /* Min Vax */
93 { 0x0, 0x0, 0x0 }} /* Mi
[all...]
/barrelfish-2018-10-04/lib/openssl-1.0.0d/crypto/rc2/
H A Drc2_cbc.c140 register RC2_INT x0,x1,x2,x3,t; local
144 x0=(RC2_INT)l&0xffff;
156 t=(x0+(x1& ~x3)+(x2&x3)+ *(p0++))&0xffff;
157 x0=(t<<1)|(t>>15);
158 t=(x1+(x2& ~x0)+(x3&x0)+ *(p0++))&0xffff;
160 t=(x2+(x3& ~x1)+(x0&x1)+ *(p0++))&0xffff;
162 t=(x3+(x0& ~x2)+(x1&x2)+ *(p0++))&0xffff;
170 x0+=p1[x3&0x3f];
171 x1+=p1[x0
185 register RC2_INT x0,x1,x2,x3,t; local
[all...]
/barrelfish-2018-10-04/lib/gdtoa/
H A Dhexnan.c54 hexnan(sp, fpi, x0)
55 CONST char **sp; FPI *fpi; ULong *x0;
57 hexnan( CONST char **sp, FPI *fpi, ULong *x0)
67 x = x0 + (nbits >> kshift);
86 if (x <= x0) {
118 if (x <= x0)
129 if (x > x0) {
130 x1 = x0;
144 if (x1 == x0) {

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