Searched refs:masked (Results 1 - 5 of 5) sorted by relevance

/barrelfish-2018-10-04/kernel/include/arch/armv8/
H A Darm_hal.h49 void pit_mask_irq(bool masked, uint8_t pit_id);
/barrelfish-2018-10-04/kernel/include/arch/x86/
H A Dapic.h49 void apic_timer_init(bool masked, bool periodic);
/barrelfish-2018-10-04/kernel/arch/x86/
H A Dapic.c50 * \param masked Mask interrupt
53 void apic_timer_init(bool masked, bool periodic) argument
57 t = xapic_lvt_timer_mask_insert(t, masked ? xapic_masked : xapic_not_masked);
59 (use_tsc_deadline && !masked ? xapic_tsc_deadline : xapic_one_shot));
/barrelfish-2018-10-04/usr/eclipseclp/documents/mpslib/
H A Declipse.tex68 that these latencies can be masked, for example by multi-threading and/or
/barrelfish-2018-10-04/doc/022-armv8/
H A Dreport.tex900 msr daifset, #3 /* IRQ and FIQ masked, Debug and Abort enabled. */

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