/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/sound/soc/s3c24xx/ |
H A D | s3c-pcm.h | 26 #define S3C_PCM_CTL_TXDMA_EN (0x1<<6) 27 #define S3C_PCM_CTL_RXDMA_EN (0x1<<5) 28 #define S3C_PCM_CTL_TXMSB_AFTER_FSYNC (0x1<<4) 29 #define S3C_PCM_CTL_RXMSB_AFTER_FSYNC (0x1<<3) 30 #define S3C_PCM_CTL_TXFIFO_EN (0x1<<2) 31 #define S3C_PCM_CTL_RXFIFO_EN (0x1<<1) 32 #define S3C_PCM_CTL_ENABLE (0x1<<0) 35 #define S3C_PCM_CLKCTL_SERCLK_EN (0x1<<19) 36 #define S3C_PCM_CLKCTL_SERCLKSEL_PCLK (0x1<<18) 43 #define S3C_PCM_TXFIFO_DVALID (0x1<<1 [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/sound/soc/s3c24xx/ |
H A D | s3c-pcm.h | 26 #define S3C_PCM_CTL_TXDMA_EN (0x1<<6) 27 #define S3C_PCM_CTL_RXDMA_EN (0x1<<5) 28 #define S3C_PCM_CTL_TXMSB_AFTER_FSYNC (0x1<<4) 29 #define S3C_PCM_CTL_RXMSB_AFTER_FSYNC (0x1<<3) 30 #define S3C_PCM_CTL_TXFIFO_EN (0x1<<2) 31 #define S3C_PCM_CTL_RXFIFO_EN (0x1<<1) 32 #define S3C_PCM_CTL_ENABLE (0x1<<0) 35 #define S3C_PCM_CLKCTL_SERCLK_EN (0x1<<19) 36 #define S3C_PCM_CLKCTL_SERCLKSEL_PCLK (0x1<<18) 43 #define S3C_PCM_TXFIFO_DVALID (0x1<<1 [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/media/video/ivtv/ |
H A D | ivtv-irq.h | 25 #define IVTV_IRQ_ENC_START_CAP (0x1 << 31) 26 #define IVTV_IRQ_ENC_EOS (0x1 << 30) 27 #define IVTV_IRQ_ENC_VBI_CAP (0x1 << 29) 28 #define IVTV_IRQ_ENC_VIM_RST (0x1 << 28) 29 #define IVTV_IRQ_ENC_DMA_COMPLETE (0x1 << 27) 30 #define IVTV_IRQ_ENC_PIO_COMPLETE (0x1 << 25) 31 #define IVTV_IRQ_DEC_AUD_MODE_CHG (0x1 << 24) 32 #define IVTV_IRQ_DEC_DATA_REQ (0x1 << 22) 33 #define IVTV_IRQ_DEC_DMA_COMPLETE (0x1 << 20) 34 #define IVTV_IRQ_DEC_VBI_RE_INSERT (0x1 << 1 [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/media/video/ivtv/ |
H A D | ivtv-irq.h | 25 #define IVTV_IRQ_ENC_START_CAP (0x1 << 31) 26 #define IVTV_IRQ_ENC_EOS (0x1 << 30) 27 #define IVTV_IRQ_ENC_VBI_CAP (0x1 << 29) 28 #define IVTV_IRQ_ENC_VIM_RST (0x1 << 28) 29 #define IVTV_IRQ_ENC_DMA_COMPLETE (0x1 << 27) 30 #define IVTV_IRQ_ENC_PIO_COMPLETE (0x1 << 25) 31 #define IVTV_IRQ_DEC_AUD_MODE_CHG (0x1 << 24) 32 #define IVTV_IRQ_DEC_DATA_REQ (0x1 << 22) 33 #define IVTV_IRQ_DEC_DMA_COMPLETE (0x1 << 20) 34 #define IVTV_IRQ_DEC_VBI_RE_INSERT (0x1 << 1 [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/testsuite/sim/sh/ |
H A D | pdmsb.s | 12 lds r0, x1 19 L0: pdmsb x0, x1 20 # assert_sreg 31<<16, x1 21 set_sreg 0x1, x0 22 L1: pdmsb x0, x1 23 assert_sreg 30<<16, x1 25 L2: pdmsb x0, x1 26 assert_sreg 29<<16, x1 28 L3: pdmsb x0, x1 29 assert_sreg 28<<16, x1 [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/testsuite/sim/sh/ |
H A D | pdmsb.s | 12 lds r0, x1 19 L0: pdmsb x0, x1 20 # assert_sreg 31<<16, x1 21 set_sreg 0x1, x0 22 L1: pdmsb x0, x1 23 assert_sreg 30<<16, x1 25 L2: pdmsb x0, x1 26 assert_sreg 29<<16, x1 28 L3: pdmsb x0, x1 29 assert_sreg 28<<16, x1 [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/testsuite/sim/sh/ |
H A D | pdmsb.s | 12 lds r0, x1 19 L0: pdmsb x0, x1 20 # assert_sreg 31<<16, x1 21 set_sreg 0x1, x0 22 L1: pdmsb x0, x1 23 assert_sreg 30<<16, x1 25 L2: pdmsb x0, x1 26 assert_sreg 29<<16, x1 28 L3: pdmsb x0, x1 29 assert_sreg 28<<16, x1 [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/include/asm/ |
H A D | segment.h | 7 #define __USER_CS 0x1 8 #define __USER_DS 0x1
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/include/asm/ |
H A D | segment.h | 7 #define __USER_CS 0x1 8 #define __USER_DS 0x1
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/gpu/drm/radeon/ |
H A D | rv250d.h | 35 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) 36 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) 38 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) 39 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) 41 #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) 42 #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) 44 #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) 45 #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) 47 #define S_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 7) 48 #define G_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) >> 7) & 0x1) [all...] |
H A D | r100d.h | 80 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 81 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 83 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 84 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 86 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) 87 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) 89 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 90 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 92 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 93 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) [all...] |
H A D | r520d.h | 41 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 42 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 44 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 45 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 47 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 48 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 50 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 51 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 53 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 54 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) [all...] |
H A D | rs600d.h | 33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) 34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) 36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) 37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) 39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) 40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) 42 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) 43 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) 45 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) 46 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) [all...] |
H A D | rv350d.h | 33 #define S_00000D_FORCE_VAP(x) (((x) & 0x1) << 21) 34 #define G_00000D_FORCE_VAP(x) (((x) >> 21) & 0x1) 36 #define S_00000D_FORCE_SR(x) (((x) & 0x1) << 25) 37 #define G_00000D_FORCE_SR(x) (((x) >> 25) & 0x1) 39 #define S_00000D_FORCE_PX(x) (((x) & 0x1) << 26) 40 #define G_00000D_FORCE_PX(x) (((x) >> 26) & 0x1) 42 #define S_00000D_FORCE_TX(x) (((x) & 0x1) << 27) 43 #define G_00000D_FORCE_TX(x) (((x) >> 27) & 0x1) 45 #define S_00000D_FORCE_US(x) (((x) & 0x1) << 28) 46 #define G_00000D_FORCE_US(x) (((x) >> 28) & 0x1) [all...] |
H A D | r420d.h | 35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) 36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) 43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 49 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 50 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 52 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 53 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/gpu/drm/radeon/ |
H A D | rv250d.h | 35 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) 36 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) 38 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) 39 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) 41 #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) 42 #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) 44 #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) 45 #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) 47 #define S_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 7) 48 #define G_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) >> 7) & 0x1) [all...] |
H A D | r100d.h | 80 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 81 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 83 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 84 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 86 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) 87 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) 89 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 90 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 92 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 93 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) [all...] |
H A D | r520d.h | 41 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 42 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 44 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 45 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 47 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 48 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 50 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 51 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 53 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 54 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) [all...] |
H A D | rs600d.h | 33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) 34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) 36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) 37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) 39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) 40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) 42 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) 43 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) 45 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) 46 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) [all...] |
H A D | rv350d.h | 33 #define S_00000D_FORCE_VAP(x) (((x) & 0x1) << 21) 34 #define G_00000D_FORCE_VAP(x) (((x) >> 21) & 0x1) 36 #define S_00000D_FORCE_SR(x) (((x) & 0x1) << 25) 37 #define G_00000D_FORCE_SR(x) (((x) >> 25) & 0x1) 39 #define S_00000D_FORCE_PX(x) (((x) & 0x1) << 26) 40 #define G_00000D_FORCE_PX(x) (((x) >> 26) & 0x1) 42 #define S_00000D_FORCE_TX(x) (((x) & 0x1) << 27) 43 #define G_00000D_FORCE_TX(x) (((x) >> 27) & 0x1) 45 #define S_00000D_FORCE_US(x) (((x) & 0x1) << 28) 46 #define G_00000D_FORCE_US(x) (((x) >> 28) & 0x1) [all...] |
H A D | r420d.h | 35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) 36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) 43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 49 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 50 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 52 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 53 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/infiniband/hw/qib/ |
H A D | qib_7220_regs.h | 39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1 41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1 57 #define QIB_7220_Control_SyncResetExceptPcieIRAMRST_RMASK 0x1 59 #define QIB_7220_Control_PCIECplQDiagEn_RMASK 0x1 61 #define QIB_7220_Control_Reserved_RMASK 0x1 63 #define QIB_7220_Control_TxLatency_RMASK 0x1 65 #define QIB_7220_Control_PCIERetryBufDiagEn_RMASK 0x1 67 #define QIB_7220_Control_LinkEn_RMASK 0x1 68 #define QIB_7220_Control_FreezeMode_LSB 0x1 69 #define QIB_7220_Control_FreezeMode_RMASK 0x1 [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/infiniband/hw/qib/ |
H A D | qib_7220_regs.h | 39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1 41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1 57 #define QIB_7220_Control_SyncResetExceptPcieIRAMRST_RMASK 0x1 59 #define QIB_7220_Control_PCIECplQDiagEn_RMASK 0x1 61 #define QIB_7220_Control_Reserved_RMASK 0x1 63 #define QIB_7220_Control_TxLatency_RMASK 0x1 65 #define QIB_7220_Control_PCIERetryBufDiagEn_RMASK 0x1 67 #define QIB_7220_Control_LinkEn_RMASK 0x1 68 #define QIB_7220_Control_FreezeMode_LSB 0x1 69 #define QIB_7220_Control_FreezeMode_RMASK 0x1 [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/include/linux/ |
H A D | amifdreg.h | 8 #define DSKRDY (0x1<<5) /* disk ready when low */ 9 #define DSKTRACK0 (0x1<<4) /* head at track zero when low */ 10 #define DSKPROT (0x1<<3) /* disk protected when low */ 11 #define DSKCHANGE (0x1<<2) /* low when disk removed */ 17 #define DSKMOTOR (0x1<<7) /* motor on when low */ 18 #define DSKSEL3 (0x1<<6) /* select drive 3 when low */ 19 #define DSKSEL2 (0x1<<5) /* select drive 2 when low */ 20 #define DSKSEL1 (0x1<<4) /* select drive 1 when low */ 21 #define DSKSEL0 (0x1<<3) /* select drive 0 when low */ 22 #define DSKSIDE (0x1<< [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/include/linux/ |
H A D | amifdreg.h | 8 #define DSKRDY (0x1<<5) /* disk ready when low */ 9 #define DSKTRACK0 (0x1<<4) /* head at track zero when low */ 10 #define DSKPROT (0x1<<3) /* disk protected when low */ 11 #define DSKCHANGE (0x1<<2) /* low when disk removed */ 17 #define DSKMOTOR (0x1<<7) /* motor on when low */ 18 #define DSKSEL3 (0x1<<6) /* select drive 3 when low */ 19 #define DSKSEL2 (0x1<<5) /* select drive 2 when low */ 20 #define DSKSEL1 (0x1<<4) /* select drive 1 when low */ 21 #define DSKSEL0 (0x1<<3) /* select drive 0 when low */ 22 #define DSKSIDE (0x1<< [all...] |